QRP Labs QCX-mini, Assembly Instructions Manual

Page: 98 / 133

4.3 Synthesized oscillator
I always start with building the VFO of a radio. It was the hardest thing to get right. How to
get that analogue LC-tuned VFO accurate, free of drift, free of chirp, tuning over the
required range, and with mechanical gearing to be able to make fine frequency
adjustments? A real challenge. Not anymore! Now we have Direct Digital Synthesis (DDS)
ICs and Digital Phase Locked Loop (PLL) ICs, inexpensive and easy to use, that solve all
the problems.
The Si5351A Synthesizer chip used in
this design provides three separate
frequency outputs, with a frequency
range spanning 3.5kHz to 200MHz. The
frequency stability is governed by the
27MHz crystal reference. Pretty stable, in
other words.
The block diagram (right) is taken from
the SiLabs Si5351A datasheet. Briefly, the 27MHz reference oscillator is multiplied up to an
internal Voltage Controlled Oscillator in the range 600-900MHz (the PLL), then divided
down to produce the final output frequency. The multiplication up and the division down are
both fractional and so the frequency
resolution is extremely finely controlled.
The chip has two PLLs and three output
divider units.
For best jitter performance, the Si5351A
datasheet recommends the use of even
integer dividers (no fractional
component) in the MultiSynth dividers
and in this CW transceiver design, this
recommendation is followed.
The synthesizer section of the circuit
diagram is shown here (right). The Si5351A datasheet dictates the use of a 25 or 27MHz
crystal. QRP Labs has always used the 27MHz crystal in our designs because it allowed us
to obtain precise 1.46Hz tone spacing for WSPR transmissions all the way up to the 2m
amateur band (145MHz). Those calculations don’t work out with the 25MHz crystal. This
requirement doesn’t apply to this CW transceiver design but economies of scale means
there are advantages to sticking with the same component values, all other things being
equal!
The Si5351A has a large number of internal 8-bit registers to control the synthesizer
behaviour, and these are programmed by the microcontroller using the I2C serial protocol.
1K resistors R3 and R4 are pull-ups required for the operation of the bus at 400kHz.
The Si5351A chip requires a 3.0 to 3.6V supply (nominally 3.3V) but the rest of this
transceiver’s digital circuits operate with a 5V supply. For the reduction of complexity and
costs, two 1N4148 diodes in series are used here to drop the 5V to a suitable voltage for
the Si5351A. It works well.
There are three outputs of the Si5351A synthesizer and these are all used to good
advantage. The Clk2 output is used to feed the transmit power amplifier, and the Clk0/1
outputs are used to drive the Quadrature Sampling Detector (QSD) during receive. These
QCX-mini assembly Rev 1.05_Fr
98