Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
92
©1989-2021 Lauterbach GmbH
SYStem.Option DISableShortSequence
Short reset sequence handling
Some processors support a feature called short reset sequence, which is enabled through the RGM_FESS
register. When the short reset sequence is enabled, a part of the reset phases (e.g. the BIST) are skipped at
reset (including reset asserted by the debugger, e.g. for
Having an incomplete reset can cause problems to the debugger, for example, flash programming can fail.
Therefore, by default setting (ON), the debugger disable the short reset sequence for external and JTAG
resets.
Some boot loaders can not cope with the debugger’s behavior, because they blindly assume that the short
sequence is enabled without checking the actual setting of the RGM_FESS register. This can cause the
application to crash (e.g. by accessing uninitialized SRAM).
The ideal solution is to modify the boot loader so that it evaluates RGM_FESS when deciding if the short
sequence is enabled or not.
Set this option to OFF for boot loaders which have problems when the debugger disables the short
sequence. The target will require a power cycle in order to recover from the debugger’s intervention.
Another use case of this option is to debug the reset scenario with short sequence enabled.
SYStem.Option DisMode
Disassembler operation mode
MPC5XXX/SPC5XX with VLE instruction set support only.
Format:
SYStem.Option DISableShortSequence
[
ON
|
OFF
]
NOTE:
•
The debugger will print a warning to the message area / status line when
is performed when this option is set to OFF and short
sequence is enabled.
•
If you should experience debugging / flash programming problems while
this option is set to OFF, you have to turn it ON again and perform
another
Format:
SYStem.Option DisMode
<mode>
<mode>
:
ACCESS
AUTO
FLE
VLE
