Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
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©1989-2021 Lauterbach GmbH
Debug port parameters
:
JTAG parameters
below):
CORE
The parameter
<core_index>
defines which core the PowerView instance
controls. Counting starts with 1, i.e. 1: core_0, 2: core_1, 3: core_2...
The parameter
<chip_index>
is important for multi-chip targets. All
PowerView instances which control cores on the same physical chip must
use the same
<chip_index>
value. Although any value > 0 is allowed, it is
recommended to use 1 for single-chip targets. See
for details and examples.
DEBUGPORT
Use this command to select the debug port to use for JTAG
communication. On TRACE32 PowerTools hardware, the debug port can
be either
DebugCable0
or
Analyzer0
, if a Nexus adapter is connected. If
TRACE32 is operated on software-only mode, DebugPort
XCP0
allows
debugging via a 3rd party XCP slave.
Slave
(default: OFF) If more than one PowerView instance is using the same
JTAG port, all except one must have this option active. Only one
debugger - the “master” - is allowed to control the signals nTRST/JCOMP
and (nRESET).
TriState
(default: OFF) If more than one debugger share the same JTAG port, this
option is required. The debugger switches to tristate mode after each
JTAG access. Then other debuggers can access the port.
DRPRE
(default: 0)
<number>
of TAPs in the JTAG chain between the core of
interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
DRPOST
(default: 0)
<number>
of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
(default: 0)
<number>
of instruction register bits in the JTAG chain
between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
IRPOST
(default: 0)
<number>
of instruction register bits in the JTAG chain
between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
