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Qorivva MPC5 Series, Manual

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Qorivva MPC5 Series Manual Download Page 111

  Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace

 

    111     

  

©1989-2021 Lauterbach GmbH

MPC551X:

SWE

SWRWH

RO

Debugger Action

off

don’t care

don’t care

none

on

off

don’t care

none

on

on

off

disable SWRWH

on

on

on

service watchdog (see note)

NOTE:

All CPUs: servicing watchdog

If the debugger is servicing the watchdog, conditions might occur, where the 
watchdog times out before the debugger is able to service it. Unintended resets 
or interrupts can occur.
Further, SWT window mode is not supported by the debugger.

MPC5516, revision 0

If the system option is ON, the debugger will configure the watchdog to the 
longest timeout period on SYStem.Up and SYStem.Mode.StandBy. During 
debugging, the watchdog timer will be serviced if SWE is on.

Summary of Contents for MPC5 Series

Page 1: ...parallel NEXUS 10 Co Processor Debugging eTPU GTM SPT 10 Multicore Debugging 10 Software only Debugging HostMCI via XCP 10 Software Installation 11 Hardware Installation 12 JTAG Debugger 12 Parallel N...

Page 2: ...splaying Peripheral Module Registers 35 Peripheral Registers Modified by TRACE32 36 Debugging and Tracing Through Reset 37 Multicore Debugging 39 SMP Debugging 40 AMP Debugging 41 Watchdog Timer Suppo...

Page 3: ...ls 63 Example Event Counter 64 Tracing Peripheral Modules Bus Masters 64 Example Filter by Address Range 64 Example Event Controlled Trace Start and End 64 Trace Filtering and Triggering Features Prov...

Page 4: ...ile HLL single stepping 96 SYStem Option KEYCODE Inhibit censorship protection 96 SYStem Option LPMDebug Enable low power mode debug handshake 98 SYStem Option LockStepDebug Enable lock step core regi...

Page 5: ...MC target RAM 130 NEXUS CLIENT x MODE Set data trace mode of nexus client 130 NEXUS CLIENT x SELECT Select a nexus client for data tracing 131 NEXUS CLIENT3 SPTACQMASTER Trace individual SPT masters 1...

Page 6: ...al breakpoint function 146 TrOnchip DISable Disable NEXUS trace register control 146 TrOnchip Echo Set special breakpoint function 146 TrOnchip ENable Enable NEXUS trace register control 147 TrOnchip...

Page 7: ...Qorivva MPC5xxx SPC5xx Debugger and NEXUS Trace 7 1989 2021 Lauterbach GmbH Qorivva MPC5xxx SPC5xx Debugger and NEXUS Trace Version 30 Apr 2021...

Page 8: ...ach TRACE32 tools for MPC5XXX SPC5XX processors JTAG OnCE Debugger Debugging MPC5XXX SPC5XX requires a Lauterbach Debug Cable together with a Lauterbach PowerDebug Module The following debug cables ar...

Page 9: ...tive_debug_cables pdf On chip Trace On chip tracing requires no extra Lauterbach hardware it can be configured and read out with a regular JTAG OnCE Debugger Depending on the on chip trace module impl...

Page 10: ...charge i e there is no additional license required For details about coprocessor debugging see the specific Processor Architecture Manuals eTPU Debugger and Trace debugger_etpu pdf GTM Debugger and T...

Page 11: ...tware Installation Please follow chapter Software Installation icd_quick_installation pdf on how to install the TRACE32 software An installer is available for a complete TRACE32 installation under Win...

Page 12: ...C5xx Debugger and NEXUS Trace 12 1989 2021 Lauterbach GmbH Hardware Installation JTAG Debugger POWER DEBUG USB INTERFACE USB 3 POWER DEBUG INTERFACE USB 3 PC or Workstation USB Cable Target Debug Conn...

Page 13: ...e 13 1989 2021 Lauterbach GmbH Parallel Nexus Debugger and Trace POWER DEBUG PRO POWER TRACE II POWER DEBUG PRO POWER TRACE II SWITCH PC or Workstation 1 GBit Ethernet Ethernet Cable Target CABLE C B...

Page 14: ...H Aurora Nexus Debugger and Trace POWER DEBUG PRO POWER TRACE II POWER DEBUG PRO POWER TRACE II SWITCH PC or Workstation 1 GBit Ethernet Ethernet Cable Target Debug Cable CABLE C B A Aurora JTAG Adapt...

Page 15: ...5XXX Tools Start Demo WARNING To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is OFF Recommendation for the software s...

Page 16: ...rogramming algorithm binaries for on chip and external flash See chapter FLASH programming for more information etc Examples for various PowerPC related debugger features kernel Example scripts for RT...

Page 17: ...l OS Awareness Manuals rtos_ os pdf TRACE32 PowerView can be extended for operating system aware debugging The appropriate OS Awareness manual informs you how to enable the OS aware debugging XCP Debu...

Page 18: ...ptimized download performance Ensure that JTAG RESET is connected directly to the RESET of the processor This will provide the ability for the debugger to drive and sense the status of RESET The targe...

Page 19: ...to run an application from SRAM set up the required TLBs manually For run time memory access the debugger requires a static translation table As the core is halted and MMU set up we can take the tran...

Page 20: ...RAM must be initialized ECC before usage 7 Load the program 8 Run program e g until function main 9 Display ASM HLL core at current instruction pointer Data Set EA 0x40000000 0x4000FFFF Quad 0x1122334...

Page 21: ...d the RCHW form FLASH 4 Cores with MMU For run time memory access the debugger requires a static translation table As the core s MMU is not set up right now copying the translation from the core is no...

Page 22: ...e As the core s MMU is not accessible while the core is running copying the translation from the core is not possible As projects usually use 1 1 translation a manual declaration can be performed 5 Ob...

Page 23: ...Qorivva MPC5xxx SPC5xx Debugger and NEXUS Trace 23 1989 2021 Lauterbach GmbH FAQ Please refer to our Frequently Asked Questions page on the Lauterbach website...

Page 24: ...Total amount of available on chip breakpoints Instruction address breakpoints Number of on chip breakpoints that can be used to set Program breakpoints into ROM FLASH EEPROM Data address breakpoints...

Page 25: ...2 breakpoint ranges 2 single breakpoints or 1 breakpoint range none e200z335 4 instruction 2 read write 2 data value 2 counters 4 single breakpoints or 2 breakpoint ranges 2 single breakpoints or 1 br...

Page 26: ...ngle address has a granularity of 1 byte Equal to program address breakpoints data address breakpoints can be configured to stop if the break event occurred a given number of times Data address breakp...

Page 27: ...ata value breakpoint is set the debugger will use one of the data address breakpoints When the core hits that breakpoint the target application will stop and the debugger will evaluate if the data val...

Page 28: ...le Break when the value 0x1233 is written to the 16 bit word at 0x40000200 Break Set 0x40000200 Write Data Word 0x1233 Break when a value not equal 0x98 is written to the 8 bit variable xval Break Set...

Page 29: ...ilable In addition to the access classes there are access class attributes Command Effect List P 0x1000 Opens a List window displaying program memory Data dump D 0xFF800000 LONG Opens a DUMP window at...

Page 30: ...ng the register number after the access class Access Class Attributes Description E Use real time memory access This attribute has no effect if SYStem MemAccess is set to Disabled A Given address is p...

Page 31: ...ting to the NEXUS registers TLB access mask Description TLB 0x8100iiiM legacy access TLB 0x0000iiiM Access to TLB1 table MMU iii TLB index M Byte offset to TLB content as represented in MAS registers...

Page 32: ...che Memory Coherency During run time Memory Access Some e200 cores only support run time access to uncached memory The affected cores are e200 cores which implement data or unified cache and which sup...

Page 33: ...he processor performance Global configuration settings like done via L1CSR have more impact than settings for small address ranges Therefore it is recommended to control the access via TLB settings an...

Page 34: ...igured used as described below If the cache lines are used as data memory ensure that SYStem Option DCREAD is set to ON default l or ll Way locked MPC55XX with unified cache not locked I locked for in...

Page 35: ...on files per so called PER files for the on chip peripherals are included in TRACE32 PER files for recent processors are usually not included in updates but are available upon request For external per...

Page 36: ...d NC for no cache Address here 0xfff48000 Bit position TRACE32 bit index here 5 Bit position Power Architecture bit numbering here 26 Full name here Vector Table Entry Size Peripheral Registers Modifi...

Page 37: ...ls On some processors the I Os used for the NEXUS port are set to GPIO functionality be default To enable trace through reset functionality these processors also require SYStem Option ResetDetection t...

Page 38: ...will be a delay from releasing reset until commands are executed On chip breakpoints can be used to stop the core after reset e g at the start of the user program If set to the reset address the CPU...

Page 39: ...lso supports mixed AMP SMP operation E g MPC5746M can be controlled with two PowerView instances one for core_2 IOP and one controlling core_0 and core_1 in SMP mode core index MPC55xx MPC563xM MPC564...

Page 40: ...detection 2 Assign cores to this PowerView instance Look up the core index of each core in above list The order of the cores must match to the core order used by the kernel 3 Start debug session and c...

Page 41: ...anges see command SYnch An easy way to start multiple PowerView instances is to use T32Start It is also possible to start further instances from a PRACTICE script The following steps demonstrate the s...

Page 42: ...Core Watchdog TCR TSR The e200 core watchdog is configured and controlled through the TCR and TSR special purpose registers There is no dedicated command to control this watchdog but it is indirectly...

Page 43: ...ata TIMER can be used to perform the required accesses while the core is halted 3 Some debug cables and NEXUS adapters support controlling a chip external watchdog with a dedicated pin This pin is con...

Page 44: ...X SPC58X and S32R processors On MPC57XX SPC57X SPC58X and S32R processors the censorship unlock is possible without asserting reset and also if functional reset is asserted For the unlock during SYSte...

Page 45: ...unlocked and SYStem Up will fail If the time is too long the processor will execute many instructions before the debug request is sent With a little fine tuning it is usually possible to halt the cor...

Page 46: ...scalation In either case it can be required to perform a power cycle to connect and recover the processor The effects of a bad application image may not become effective directly after programming the...

Page 47: ...est before the unlock took place However is the time is too long the processor may execute the problematic code before the debug request can halt the core It is recommended to find a suitable timing u...

Page 48: ...ure boot are blown it is important to halt the processor not before BootROM execution has completed This can be achieved using SYStem Option ResBreak OFF Doing so will halt the processor usually at th...

Page 49: ...ason target power fail Target has no power or debug cable is not connected Check if the JTAG VCC pin is driven by the target emulation pod configuration error The installed debugger software version i...

Page 50: ...cording after the problem occurred If the error occurs during a memory access the used address or address range possibly pointed to an unimplemented memory location or to a peripheral module that is d...

Page 51: ...PCFIFO and NEXUS trace in parallel The PCFIFO has no configurable options It is always enabled None of the trace related command groups SYStem NEXUS TrOnchip Onchip has an effect on the PCFIFO operat...

Page 52: ...configuration can also be scripted depending on connected processor and debug tool See Onchip TBARange for an example The configuration of trace methods and clients is done through the NEXUS and TrOn...

Page 53: ...ortSize The trace port frequency divider must be selected so that the resulting trace port frequency does not exceed the maximum specified frequency in the processor s data sheet Many processors suppo...

Page 54: ...essage FIFO i e loss of trace data Setup of for branch trace messaging History Trace Messaging HTM In history tracing mode the e200 core only sends trace messages for indirect branches Information abo...

Page 55: ...ess task thread etc changes One method is using the data trace the other method uses Ownership Trace Messaging OTM In order to have the debugger process and display task information properly it is req...

Page 56: ...ther information Example for tracing context switches using OTM for an operating system using the OSEK Runtime Interface ORTI Trace Based Run time Measurement Timestamping In order to enable trace bas...

Page 57: ...ision on sub function level or when trace filtering is performed Run time measurements on function level as well as average measurements usually do not lose precision It is recommended to not use trac...

Page 58: ...n the recordings can be correlated manually see Trace ZERO As the clock sources of tool generated and processor generated timestamps are not synchronized the time offset can increase with higher dista...

Page 59: ...to act as input event for selective tracing TRACE32 offers a variety of features based on watchpoints Watchpoints are set using the command Break Set similar to breakpoints that halt the core but add...

Page 60: ...PowerProbe or to control external devices using the trigger connector of the PowerDebug PowerTrace module see TrBus BusCount The specified event is used as input for the counter of the PowerDebug Pow...

Page 61: ...rate a trace message when the instruction at address 0x00008230 is executed Break Set 0x00008230 Program TraceEnable Only generate a trace message when the core writes to variable flags 3 Var Break Se...

Page 62: ...able can be used for time measurements only if the processor generates trace messages with timestamps See NEXUS TimeStamps for details If the processor does not support timestamp generation do not use...

Page 63: ...ReadWrite Break Set func2 Program Onchip Alpha TrOnchip Alpha ProgramTraceON Var Break Set flags 8 ReadWrite Onchip Beta TrOnchip Beta ProgramTraceOFF In addition to full program trace enable disable...

Page 64: ...configurable address ranges The client will only generate trace messages if the read or write address is inside one of those address ranges The range only applies to the selected clients Other clients...

Page 65: ...ompiled for which encoding The debugger will show wrong information in the List window and there will be flow errors in the Trace analysis if one of below situations occur If debug symbols have not be...

Page 66: ...e it was observed that all debug symbols were aligned to 4 byte boundaries while the actual code was aligned at 2 byte boundaries Check linker version and linker configuration Early complier versions...

Page 67: ...arameters are optional Manufacturer Filename Freescale demo powerpc flash mpc5 cmm STMicroelectronics demo powerpc flash spc5 cmm Freescale STM JDP Joint Development Program demo powerpc flash jpc5 cm...

Page 68: ...on the target design and processor Use carefully because overclocking can damage the processor prepare flash programming DO demo powerpc flash mpc5xxx cmm PREPAREONLY activate flash programming erasin...

Page 69: ...H Program to program flash FLASH ReProgram will merge all data loaded by Data LOAD or Data Set before programming the device This way TRACE32 will ensure that no 64 bit unit will be programmed more th...

Page 70: ...ash programming example scripts included with TRACE32 declare the shadow row sector but the sector is set to flash algorithm NOP instead of TARGET This way the sector is protected against accidental e...

Page 71: ...is set to type TARGET it can be erased and programmed The censorship word is however still protected Every time the shadow row is erased the debugger will force restore the default censorship word Th...

Page 72: ...to enable censored mode FLASH AUTO shadow_row_base size CENSORSHIP Data Set censorship_address QUAD 0x55AA1234FFFFFFFF for C90FL H7F Data Set censorship_address QUAD 0x55AA123455AA1234 for C90LC Data...

Page 73: ...cidental programming Any FLASH command that makes use of the erase feature i e FLASH Erase FLASH AUTO FLASH ReProgram will omit sectors declared as OTP OTP sectors must be programmed using FLASH Progr...

Page 74: ...ect refer to the processor reference manual for invalid unused DCF chip selects As an additional measure of safety the programming script could be extended to only program the OTP if it is still unpro...

Page 75: ...urring problem is that the file to be programmed to FLASH contains address ranges outside the addresses of the FLASH sectors e g SRAM or unimplemented memory space This can interrupt the flash algorit...

Page 76: ...command an address range ECC Errors in FLASH The FLASH programming commands FLASH ReProgram and FLASH AUTO will read from FLASH sectors that are going to be modified Although the debugger tries to rec...

Page 77: ...JTAG frequency for all cores Format SYStem BdmClock rate rate 1kHz 50MHz NOTE The recommended maximum JTAG frequency is 1 4th of the core frequency with default PLL configuration after reset The JTAG...

Page 78: ...ands Note that the command line provides additional SYStem CONFIG commands for settings that are not included in the SYStem CONFIG state window Format SYStem CONFIG state tab tab DebugPort Jtag XCP ta...

Page 79: ...ted to the common JTAG port at the same time TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate mode Format SYStem CONFIG parameter numbe...

Page 80: ...COMP and nRESET TriState default OFF If more than one debugger share the same JTAG port this option is required The debugger switches to tristate mode after each JTAG access Then other debuggers can a...

Page 81: ...le TCKLevel default 0 Level of TCK signal when all debuggers are tristated CJTAGFLAGS flags Activates bug fixes for cJTAG implementations Bit 0 Disable scanning of cJTAG ID Bit 1 Target has no keeper...

Page 82: ...E There is only one TAP So type just the IR bits of TAP4 i e 6 SYStem CONFIG IRPOST 12 IRPOST Add up the IR bits of TAP1 TAP2 and TAP3 i e 4 3 5 12 SYStem CONFIG DRPRE 1 DRPRE There is only one TAP wh...

Page 83: ...1989 2021 Lauterbach GmbH TapStates 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Id...

Page 84: ...g cable or Nexus adapter supports cJTAG operation depends on the production date The production date is encoded in the serial number CYYMMxxxxxxx YY year MM month LA 7753 14 pin JTAG OnCE header Must...

Page 85: ...Cable Automotive PRO Debug Cable XCP and Nexus AutoFocus adapters Format SYStem CONFIG EXTWDTDIS option option OFF High Low HighwhenStopped LowwhenStopped Trigger OFF The WDTDIS pin is not driven onl...

Page 86: ...e http www lauterbach com 3232 or contact technical support Format SYStem CONFIG PortSHaRing ON OFF Mode mode SYStem Option ETK ON OFF deprecated SYStem Option GSI 1 2 OFF deprecated mode ETK GSI1 GSI...

Page 87: ...s also possible to activate this non intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting SYStem Option DUALPORT ON Format SYStem LOCK ON OFF Format SYStem MemAcces...

Page 88: ...med XCP Only available for software only debugging HostMCI Memory access is done via a built in memory access feature of the 3rd party XCP slave This memory access method is faster than performing the...

Page 89: ...et with debug mode enabled and prepares the CPU for debug mode entry Now the processor can be stopped with the break command or any break condition Attach Connect to the processor without resetting ta...

Page 90: ...code right after reset The other cores remain in reset or disabled state In this state it is not possible to set breakpoints or configure the core for tracing This option works around this limitation...

Page 91: ...n optimal data throughput while maintaining cache coherency while core is halted Do not to set DCFREEZE to OFF unless advised by Lauterbach SYStem Option DCREAD Read from data cache Default ON If enab...

Page 92: ...cause the application to crash e g by accessing uninitialized SRAM The ideal solution is to modify the boot loader so that it evaluates RGM_FESS when deciding if the short sequence is enabled or not...

Page 93: ...Please note that while the CPU is running MMU address translation can not be accesses by the debugger Only physical addresses accesses are possible Use the access class modifier A to declare the acces...

Page 94: ...ead and Write access class DBG This feature is not available for all processors SYStem Option FREEZE Freeze system timers on debug events Enabling this option will lead the debugger to set the FT bit...

Page 95: ...ache of e200z6 cores Default ON Invalidates the instruction cache before starting the target program Step or Go If this option is disabled the debugger will update Memory and instruction cache for pro...

Page 96: ...tep the interrupt mask bits are restored to the value before the step SYStem Option KEYCODE Inhibit censorship protection Use this command to inhibit the censorship protection The processor will then...

Page 97: ...bit values matched the address order in FLASH NOTE MPC55XX processors do not support censorship inhibit via JTAG MPC57XX SPC57X SPC58X processors do not support the censorship unlock while reset is a...

Page 98: ...changes to running lpm stop lpm sleep At LPM exit the communication between the debugger and the processor is re established attach The breakpoints and the NEXUS settings are lost ACTIVE TRACE32 tries...

Page 99: ...real time behavior Please check the processor s reference manual about how the LPM debug handshake works for your specific device If the processor tristates TDO during LPM TDO must be pulled HIGH on t...

Page 100: ...o update SRAM while maintaining cache coherency It is essential to set this option to ON only if the data cache is configured to write through mode L1CSR0 DCWM 1 If the cache is operated in copy back...

Page 101: ...debugger when memory accesses done via the NEXUS block are finished Memory accesses via the NEXUS block are possible with the NEXUS debugger and trace but also with the JTAG only debugger The existenc...

Page 102: ...default OFF TRAP is enabled as debug event in the E DBCR0 register Format SYStem Option NOTRAP ON OFF e200z0 e200z0H e200z0Hn2P e200z1 e200z3 e200z335 e200z336 e200z6 e200z750 If ON the BRKPT instruc...

Page 103: ...RAM Format SYStem Option OVERLAY ON OFF WithOVS ON Activates the overlay extension and extends the address scheme of the debugger with a 16 bit virtual overlay ID Addresses therefore have the format o...

Page 104: ...etected Information about the reset will be printed to the message AREA AsyncHalt Halt core as soon as possible after reset was detected The core will halt shortly after the reset event AsyncStart Hal...

Page 105: ...or and halt the core The longer the defined WaitReset time the more program code is executed until the core can be halted If the WaitReset time is too short SYStem Up will fail SYStem Option ResetDete...

Page 106: ...2708 LA 3736 JTAG Debugger for MPC5xxx Automotive LA 7630 NEXUS Debug Trace for Qorivva MPC5xxx SPC5xxx LA 7610 NEXUS Debugger and Trace for MPC5500 Format SYStem Option ResetMode mode mode PIN DESTru...

Page 107: ...ich core s TDO signal is routed to the TDO pin of the processor Can be useful for debugging lock step related application issues Not available for cores in delayed lock step This setting should only b...

Page 108: ...ORS 0x40002000 0x40002100 address range 2 methods SYStem Option VECTORS 0x40002000 0x40002FFF SYStem Option VECTORS 0x40002000 0x00002FFF use IVPR IVOR registers startaddr R IVPR range DATA LONG SPR 4...

Page 109: ...he debugger detects that reset is released on the corresponding pin Use this command when SYStem Up fails and the message AREA shows the message Target reset detected during system up sequence A wait...

Page 110: ...bled later by the application For MPC563X and SPC563 the debugger will only clear WEN If the debugger is connected using SYStem Mode Go or SYStem Mode Attach the debugger will try to disable and the w...

Page 111: ...og If the debugger is servicing the watchdog conditions might occur where the watchdog times out before the debugger is able to service it Unintended resets or interrupts can occur Further SWT window...

Page 112: ...elPageTable TaskPageTable task_magic task_id task_name space_id 0x0 cpu_specific_tables root The root argument can be used to specify a page table base address deviating from the default page table ba...

Page 113: ...agic task_id task_name space_id 0x0 Displays the MMU translation table entries of the given process Specify one of the TaskPageTable arguments to choose the process you want In MMU based operating sys...

Page 114: ...of TLB2 MPU Format MMU List table range address range root address root MMU table List deprecated table PageTable KernelPageTable TaskPageTable task_magic task_id task_name space_id 0x0 root The root...

Page 115: ...task_magic task_id task_name space_id 0x0 Lists the MMU translation of the given process Specify one of the TaskPageTable arguments to choose the process you want In MMU based operating systems each...

Page 116: ...ss translation into the debugger internal static translation table if range or address have a space ID loads the translation table of the specified process else this command loads the table the CPU cu...

Page 117: ...n the CPU The parameter tlb is not available for CPUs with only one TLB table TLB1 Loads the TLB1 from the CPU to the debugger internal translation table TLB2 Loads the TLB2 MPU from the CPU to the de...

Page 118: ...nt triggered counter start stop The events are defines using ALPHA and BETA breakpoints set with Break Set Every time the Alpha breakpoint condition triggers the counter is started The counter stops w...

Page 119: ...execute unction sieve BMC RESet Break Delete set up counter start stop events Break Set sYmbol BEGIN sieve Program Onchip Alpha Break Set sYmbol EXIT sieve Program Onchip Beta set up CNT0 to count pr...

Page 120: ...e set up counter start stop events Var Break Set sieve Program Onchip Alpha Var Break Set sieve Program Onchip Beta EXCLUDE set up additional BMC event to count function entries Break Set sYmbol BEGIN...

Page 121: ...counter start stop events magic TASK MAGIC my_task get magic value for the task of interest Break Set task config magic ReadWrite Onchip Data magic Alpha Break Set task config magic ReadWrite Onchip...

Page 122: ...mbH BMC FREEZE Freeze counters while core halted On MPC5XXX the core performance counters automatically stop when a core enters debug mode Therefore this command has no effect MASKSET Counter frozen i...

Page 123: ...kpoints are spent As soon as a new data address breakpoint is set the data address breakpoint to the address range is converted to a single data address breakpoint Please be aware that the breakpoint...

Page 124: ...n MPC57XX SPC57XX the functionality was moved to EDBRAC0 See core reference manual for the EDBRAC0 DBERC0 bit definitions Format TrOnchip EDBRAC0 edbrac0 dirconfig TrOnchip DBERC0 edbrac0 edbrac0 Valu...

Page 125: ...r It is not avail able on all processor Please check the processor reference manual for availability On MPC551X set this option to OFF when the EVTx pins are used for the EBI External Bus Interface If...

Page 126: ...elow events Default is OFF unless specified otherwise Format TrOnchip RESet Format TrOnchip Set event ON OFF event BRT IRPT RET CIRPT CRET BKPT event Break events see below BRT Branch taken IRPT RET I...

Page 127: ...rogram execution stops also on any unintentional accesses to the variable s address space Requires two onchip breakpoints since a range breakpoint is used ON If a breakpoint is set to a scalar variabl...

Page 128: ...ger setup window Displays the TrOnchip state window for on chip trigger setup Different commands are available in the TrOnchip state window depending on the Lauterbach hardware used Format TrOnchip st...

Page 129: ...processor Format Onchip TBARange access range access A EEC A Default address space e g production device EEC Address space of emulation device trace buffer range Address range of trace buffer e g 0xD...

Page 130: ...CLIENT x MODE Set data trace mode of nexus client Sets the data trace mode of the selected trace client Select the trace client using NEXUS CLIENT x SELECT before setting the trace mode Format NEXUS...

Page 131: ...accesses If set to a specific master ID only the ID of this master is traced NEXUS CoreENable Enable core tracing for dedicated cores in SMP Core tracing is enabled for all core of an SMP system by d...

Page 132: ...supported by NEXUS AutoFocus adapter LA 7630 Check processor reference manual if the processor supports DDR Usually DDR mode is not allowed with NEXUS PortMode 1 1 and 1 3 On many processors esp MPC5...

Page 133: ...ace messaging disabled default Read Write ReadWrite Data trace messages for read accesses load instructions Data trace messages for write accesses store instructions Data trace messages for read and w...

Page 134: ...cesses while the core is halted Please note that memory accesses through the NEXUS block SYStem MemAccess NEXUS do not generate data trace messages NEXUS DQM Enable data acquisition messaging Default...

Page 135: ...onfiguration is exclusively done by calibration tool Format NEXUS HTM ON OFF SYStem Option HTM ON OFF deprecated OFF default The core generates a program trace message for every taken direct or indire...

Page 136: ...2021 Lauterbach GmbH NEXUS ON Switch the NEXUS trace port on The NEXUS trace port is switched on All trace registers are configured by debugger Do not use if calibration tool makes use of data trace...

Page 137: ...nerated if the application writes to the PID0 register NPIDR Enable ownership trace messaging An OTM is generated if the application writes to the NPIDR register ON Deprecated use PID0 NOTE Enable own...

Page 138: ...t of the system frequency Format NEXUS PINCR NEXUS PINCR value SYStem CPU SC570S50 select CPU NEXUS PortSize MDO4 NEXUS PINCR 0x01492492 set trace port size to 4 MDOs map all trace pins to port B SYSt...

Page 139: ...t a write access to the PID register Enable this option when the OTM is used to generate trace information about task switches OTMs are usually used for task switch tracing on processors with NEXUS 2...

Page 140: ...ailable on processors which implement IEEE ISTO 5001 2008 or later Format NEXUS PTCM event ON OFF event PID_MSR BL_HTM TLBNEW TLBINV PID_MSR Core generates PTCM when PID or MSR IS changes EVCODE 0x5 B...

Page 141: ...ens a window which shows the NEXUS configuration and status registers of NPC core and other trace clients NEXUS RESet Reset NEXUS trace port settings Resets NEXUS trace port settings to default settin...

Page 142: ...controller will stop the core s execution pipeline until all messaged in the on chip NEXUS FIFO are sent Enabling this command will affect delay the instruction execution timing of the CPU This syste...

Page 143: ...the NEXUS messages If the chip external trace is used tracing to PowerTrace unit on chip timestamps are usually not needed because the PowerTrace unit will add it s own timestamp When using the on ch...

Page 144: ...M Enable watchpoint messaging Format NEXUS WTM ON OFF SYStem Option WTM ON OFF deprecated ON NEXUS outputs watchpoint messages OFF No watchpoint messages are output by NEXUS NOTE When a watchpoint is...

Page 145: ...riggering with Debug Events and Tracing Peripheral Modules Bus Masters TrOnchip Beta Set special breakpoint function See TrOnchip Alpha Format TrOnchip Alpha function function OFF ProgramTraceON Progr...

Page 146: ...By executing this command the debugger will not write or modify any registers of the NEXUS block This option can be used to manually set up the NEXUS trace registers The NEXUS memory access is not aff...

Page 147: ...n it is recommended to enable this option to achieve a shorter delay If this option is disabled the debugger will drive EVTI permanently high NOTES Only enable this option if the EVTI pin of the proce...

Page 148: ...he Complex Trigger Unit CTU supports the input channel level as condition IN TrOnchip Out0 Select OUT0 pin signal source Selects the signal source for the OUT0 pin of the NEXUS connector On LA 7630 ad...

Page 149: ...of the Nexus probe OUT0 pin can control a WDTC before a SYStem Up command TD WDTE pin cannot offer that OUT0 can not be tristated and is always driving HIGH or LOW OUT0 is not 5V tolerant it can drive...

Page 150: ...or so changing this setting will also change OUT1 Refer also to TrOnchip Out0 command as a second way to control an output pin with slightly different features Format TrOnchip TOOLIO2 source source OF...

Page 151: ...disable the program trace for interrupts On account of the on chip implementation the program trace will start after the first interrupt return RFI instruction is executed Format TrOnchip TRaceControl...

Page 152: ...eescale and STM evaluation boards AUTO26 Connector JTAG Signal Pin Pin Signal TDI 1 2 GND TDO 3 4 GND TCK 5 6 GND EVTI 7 8 N C RESET 9 10 TMS JTAG VTREF 11 12 GND RDY 13 14 JCOMP Signal Pin Pin Signal...

Page 153: ...4 TDO DAP2 TMS DAP1 5 6 TDI DAPEN USERIO 7 8 VTREF RESETOUT 9 10 RESET Signal Pin Pin Signal MDO12 1 2 MDO13 MDO14 3 4 MDO15 MDO09 5 6 CLKOUT N C 7 8 MDO08 RSTIN 9 10 EVTI TDO 11 12 VTREF MDO10 13 14...

Page 154: ...6 TMS MDO00 7 8 TDI MDO01 9 10 TDO GND 11 12 TRST JCOMP MDO02 13 14 DBGACK RDY MDO03 15 16 EVTI GND 17 18 EVTO MCKO 19 20 RSTIN MDO04 21 22 RSTOUT GND 23 24 GND MDO05 25 26 CLKOUT MDO06 27 28 TD WDTE...

Page 155: ...TDO 6 RDY 7 RSTIN 8 VREF 9 EVTI 10 GND 11 TRST 12 GND 13 TMS 14 GND 15 TDI 16 GND 17 TCK 18 GND 19 MDO0 20 GND 21 MCKO 22 GND 23 EVTO 24 GND 25 MSEO0 26 MDO9 27 MDO1 28 GND 29 MDO2 30 GND 31 MDO3 32 G...

Page 156: ...nnector Aurora NEXUS Signal Pin Pin Signal TXP0 1 2 JTAG VTREF TXN0 3 4 TCK GND 5 6 TMS TXP1 7 8 TDI TXN1 9 10 TDO GND 11 12 JCOMP TXP2 13 14 N C TXN2 15 16 EVTI GND 17 18 EVTO TXP3 19 20 RSTOUT TXN3...

Page 157: ...S MPC5500 3500 275 137 SIDE VIEW TOP VIEW ALL DIMENSIONS IN 1 1000 INCH CABLE 500 1462 1975 2475 1 675 275 REGULAR M2 5 screw 2 X dia 100 for CONVERTER MICTOR TO GLENAIR 51 400 1775 100 850 850 325 13...

Page 158: ...12 NEXUS MPC551X Dimension CONVERTER MICTOR TO GLENAIR 51 400 1775 100 850 850 325 1375 PIN1 PIN1 OUTSIDE INSIDE TOP VIEW TWO ROTATE VERSIONS OF THE GLENAIR 51 PLUG AVAILABLE STANDARD ORIENTATION IS O...

Page 159: ...LA 7630 NEXUS MPC5500 AF LA 7631 CONV MIC38 GENERIC Dimension PIN1 TOP VIEW SIDE VIEW ALL DIMENSIONS IN 1 1000 INCH 275 475 675 3950 1400 400 1525 2475 CABLE LAUTERBACH NEXUS ADAPTER 125 713 975 1500...

Page 160: ...C5500R Dimension TOP VIEW 2X R50 1500 1215 188 1050 ALL DIMENSIONS IN 1 1000 INCH GND IXO OXO GND GND GND GND GND PIN1 LAUTERBACH 2x dia 100 for screws 100 ADAPTER MPC55xx 838 213 75 125 1088 1600 172...

Page 161: ...00 S Dimension TOP VIEW ALL DIMENSIONS IN 1 1000 INCH 675 238 363 1500 Adapter SAMTEC ERx8 50 PIN LAUTERBACH GND DAI2 IX0 N C TD WDT OX0 DAI1 GND J101 J100 1 PIN1 NEXUS AutoFocus TOP VIEW ALL DIMENSIO...

Page 162: ...L LA 7639 CONV MIC38 MPC5500 S Dimension ALL DIMENSIONS IN 1 1000 INCH TOP VIEW LAUTERBACH 150 238 200 513 1575 1775 2 X DIA 100 for screws converter SAMTEC ERx8 50 pin PIN1 850 TOP VIEW ALL DIMENSIO...

Page 163: ...C76 JTAG14 LA 7641 CONV SAM50 MPC5500 L Dimension TOP VIEW SIDE VIEW ALL DIMENSIONS IN 1 1000 INCH CABLE FLEX 3550 488 306 1500 975 375 525 825 1675 PIN 1 MICTOR PIN 1 SAMTEC 700 SIDE VIEW ALL DIMENSI...

Page 164: ...terbach GmbH LA 7645 NEXUS AVR32 AF LA 3725 CONV MIC38 J14 5500 Dimension PIN1 TOP VIEW SIDE VIEW ALL DIMENSIONS IN 1 1000 INCH 275 475 675 3950 1400 400 1525 2475 CABLE LAUTERBACH NEXUS ADAPTER MICTO...

Page 165: ...5 ET176 MPC5607BC Dimension SIDE VIEW TOP VIEW ALL DIMENSIONS IN mm NEXUS connector TARGET TET ADAPTER SOCKET 80 0mm 80 0mm NEXUS CONNECTOR 12 1mm 12 1mm 10 2mm TO 1325 TO 1388 BGA 3150 475 475 PIN1 3...

Page 166: ...PRO LA 2713 1 6 5 5 V JTAG Debugger for MPC5xxx Automotive LA 3736 1 6 5 5 V Debugger Bundle MPC5xxx TriCore Automotive LA 3738 1 6 5 5 V JTAG Debugger Qorivva MPC5xxx SPC5xxx ICD LA 7753 1 6 5 5 V A...

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