Qorivva MPC5 Series, Manual

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Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 110
©1989-2021 Lauterbach GmbH
SYStem.Option WATCHDOG Debug with software watchdog timer
Defined how the debugger is handling the on-chip software watchdog timer. Default: OFF.
The table below describes how the debugger is configuring the SWT when SYStem.Option WATCHDOG
ON is used. The configuration takes place any time the CPU stops for the debugger according to the tables
below:
MPC56XX, SPC56X, MPC57XX, SPC57X:
Format: SYStem.Option WATCHDOG <method >
<method> : [ ON | OFF | PASSIVE ]
OFF Default setting. The watchdog timer of the processor will be disabled during
SYStem.Up and SYStem.Mode.StandBy . For MPC551x, the debugger will
also set the SWCTR_RO (read_only) bit in order to prevent that the
watchdog timer is enabled later by the application. For MPC563X and
SPC563, the debugger will only clear WEN.
If the debugger is connected using
SYStem.Mode.Go or
SYStem.Mode.Attach , the debugger will try to disable and the watchdog
timer as soon as the processor is stopped. If the watchdog is enabled and
SWCTR_RO bit is set after
SYStem.Mode.Go or SYStem.Mode.Attach ,
SYStem.Option WATCHDOG OFF cannot be used.
ON The state of the SWT (enabled or disabled) is not changed by the
debugger. If possible the debugger will try to configure the SWT so that it
does not time out while the processor is halted. See tables below for
details.
PASSIVE The debugger does not access (read or write) the SWT registers. The
target application must ensure that the SWT does not time out while the
core is halted for debugging.
CR[WEN] CR[FRZ] CR[HLK]
CR[SLK] Debugger Action
off don’t care don’t care none
on on don’t care none
on off SLK on
HLK off set FRZ
on off HLK on service watchdog (see note)