Qorivva MPC5 Series, Manual

Page: 39 / 166

Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 39
©1989-2021 Lauterbach GmbH
Multicore Debugging
One or more cores can be assigned to a TRACE32 PowerView instance. The cores are referred to by a
core-index which is hard coded in the debugger software.
TRACE32 supports either controlling each core with a separate PowerView instance ( AMP debugging ) or
controlling multiple cores with a single PowerView instance ( SMP debugging ). SMP debugging is only
possible for cores of the same architecture (e.g. e200 core_0 and e200 core_1).
TRACE32 also supports mixed AMP/SMP operation. E.g. MPC5746M can be controlled with two
PowerView instances, one for core_2 (IOP) and one controlling core_0 and core_1 in SMP mode.
core-index MPC55xx
MPC563xM
MPC564xA
MPC5674F
SPC563M
SPC564A MPC5510
MPC5643L
MPC5668G
MPC567xK
SPC56EL
SPC56HL
SPC56AP MPC5676R
MPC574xR
MPC5777C MPC5747C
MPC5748C
MPC5746G
MPC5747G
MPC5748G MPC5744B
MPC5745B
MCP5746B
MPC5744C
MPC5745C
MPC5746C
core_0 1 1 1 1 (z4_a) 1 (z4)
core_1 - 2 2 2 (z4_b) 2 (z2)
core_2 - - - 3 (z2) -
HSM - - - 4 3
eTPU A/B/C 2/3/4 - 3/4/5 - -
GTM - - - - -
SPT - - - - -
core-index MPC5746M
MPC5777M
SPC57xM
SPC58xG
SPC58xE
SPC58xN
SPC58xH MPC574xK
SPC574K MPC577xK
S32R264
S32R274
S32R294
S32R372
core_0 1 1 3 (z4)
core_1 2 - 1 (z7_a)
core_2 3 (IOP) 3 (IOP) 2 (z7_b)
HSM 4 4 -
eTPU A/B/C - - -
GTM 5 5 -
SPT - - 4