Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
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4.
Load debug symbols on both instances.
5.
Start debug session: SYStem.Up for the core that runs right from reset. SYStem.Mode.Attach for
all cores that are started later.
6.
Core_0 is halted at the reset address and core_1 remains in reset, In order to halt core_1 as
soon as it is released from reset, issue the Break command.
7.
Start core_0. Core_1 will halt at its reset address after being released by core_0.
Example scripts for AMP debugging can be found in the demo folder, e.g.
•
~~/demo/powerpc/hardware/mpc56xx/mpc564xc-dualcore/
•
~~/demo/powerpc/hardware/spc56xx/spc56el-dualcore/
Further demo scripts are available for download and upon request.
Watchdog Timer Support
e200 Core Watchdog (TCR/TSR)
The e200 core watchdog is configured and controlled through the TCR and TSR special purpose registers.
There is no dedicated command to control this watchdog, but it is indirectly controlled with
, which halts the time base (TBU/TBL/DEC) while the core is halted in debug
mode.
On-chip Watchdog (SWT)
The on-chip SWT modules can be controlled via
. By default setting,
TRACE32 will disable the SWT every time the core halts in debug mode. Each TRACE32 PowerView
instance will control only the SWT module(s) that is/are assigned to the core(s) it controls.
If it is intended to debug with SWT enabled, please ensure that the application sets the SWT_CR[FRZ] bit
when it sets up the SWT. The FRZ bit configures the SWT to automatically halt when the core halts for the
debugger.
Data.LOAD appl.x /NoCODE
Data.LOAD appl.x /NoCODE
SYStem.Up
SYStem.Mode.Attach
Break
Go
WAIT !RUN()
; wait until cpu stops
