User Manual
E727T0005, valid for E-727
BRO, 2019-06-28
Physik Instrumente (PI) GmbH & Co. KG, Auf der Roemerstrasse 1, 76228 Karlsruhe, Germany
Page 154 / 240
Phone +49 721 4846-0, Fax +49 721 4846-1019, Email
Note 4: Before writing the received data bytes to FIFO the receiver should check if the FIFO is not
full. This is not shown by the flow chart because the implementation might be different, depending
on the PI-controller type or host implementation. However, the following procedure is
recommended
Save the received DataSegmen2.Byte1, DataSegmen2.Byte2 and CTR2 bits
temporarily to a buffer.
Set the ST.ACK bit zero as long as the receiver FIFO is full. This tells the sender that
the receiver is not ready to receive any more DataSegmen2 data bytes.
When the FIFO is not full any more save the received data bytes from buffer to the
FIFO.
After saving the data bytes to FIFO the ST.ACK bit should be set to one and the
received toggle bit should be returned to the sender (shown at the end of the flow