Philips DVDR880/001, Service Manual

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EN 122 DVDR880-890 /0X1 7. Circuit Diagrams and PWB Layouts
DVIO Board: DVCODEC
1Mx16 devices are used as 256kx16
DVCODEC
I II
H H
I
H H
G G
F F
E E
D D
F F
E E
D D
C C C C
B B
A A
8 8
B B
A A
15 15 14 14 13 13
G G
6 5 5 4 4 3 3 2 12 12 11 11 10 10 9 9
8 8 7 7
2 1 1
15 15 14 14 13 13
7 7 6
5 5 4 4 3 3 2 2 12 12 11 11 10 10 9 9 1 1 6 6
DRAM DATA [ 0...31] BUS
GENERAL
PURPOSE I/O
HOST AD BUS [ 0....15 ]
AUDIO
INTERFACE
VIDEO BUS
VIDEO BUS CLOCK INPUTS
SYNCHRONOUS
VIDEO INTERFACE
DRAM CTRL
DRAM ADDRESS BUS
DV Decoder
DRAM DATA [ 0...31] BUS
GENERAL
PURPOSE I/O
HOST AD BUS [ 0....15 ]
AUDIO
INTERFACE
VIDEO BUS
VIDEO BUS CLOCK INPUTS
SYNCHRONOUS
VIDEO INTERFACE
DRAM CTRL
DRAM ADDRESS BUS
DV Decoder
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
WE
HCAS
LCAS
9
8
7
6
5
4
3
NC
NC
2
1
RAS
0
DATA
ADR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
WE
HCAS
LCAS
9
8
7
6
5
4
3
NC
NC
2
1
RAS
0
DATA
ADR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
WE
HCAS
LCAS
9
8
7
6
5
4
3
NC
NC
2
1
RAS
0
DATA
ADR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
WE
HCAS
LCAS
9
8
7
6
5
4
3
NC
NC
2
1
RAS
0
DATA
ADR
15
14
13
1Mx16 devices are used as 256kx16
DVCODEC
OPTION
OPTION
H
G
F
E
D
I
7
1
15 14 13 12
7 6 5 4 3 2 12 11 10 9 8
B
A
15 14 13
G
F
E
D
C C
B
A
I
H
HAD(3)
HAD(4)
HAD(5)
HAD(6)
HAD(0)
HAD(1)
HAD(2)
IO(31)
LCASn
RASn
UCASn
WEn
+3V3_DV
+3V3_DV +3V3_DV
A(0)
+3V3_DV +3V3_DV +3V3_DV
+3V3_DV
1
CLK27M_DV
6 5 4 3 2 11 10 9 8
CRTL{RASn,LCASn,UCASn,WEn}
IO(31:0)
A(6)
A(7)
A(8)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(0)
A(1)
A(2)
A(3)
A(4)
A(5)
A(0)
A(1)
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
HAD(7)
IO(30)
A(3)
A(4)
A(5)
A(6)
+35V_DV_EDO
+35V_DV_EDO +35V_DV_EDO
A(1)
A(2)
IO(10)
+35V_DV_EDO
+35V_DV_EDO
+35V_DV_EDO
IO(28)
IO(29)
IO(30)
IO(31)
IO(9)
IO(24)
IO(25)
IO(26)
IO(27)
IO(19)
IO(20)
IO(21)
IO(22)
IO(23)
IO(16)
IO(17)
IO(18)
+VCC_DV_RAM
IO(4)
IO(3)
IO(2)
IO(1)
IO(11)
IO(8)
IO(7)
IO(6)
IO(5)
IO(15) IO(14) IO(13) IO(12) IO(20) IO(19) IO(18) IO(17) IO(16) IO(24) IO(23) IO(22) IO(21) IO(29) IO(28) IO(27) IO(26) IO(25)
A(7)
A(8)
+3V3_DV +3V3_DV
DV
RSTn
DV
RWn
DV DTACKn
DV_DRQn
HAD(7:0)
YUV(7:0)
+5V
A(0:8)
UCASn
LCASn
UCASn
+3V3
+5V
RASn
WEn
+3V3
LCASn
+3V3
RASn
WEn
+VCC_DV_RAM +35V_DV_EDO +3V3_DV
+VCC_DV_RAM
IO(0)
YUV(7) YUV(6) YUV(4) YUV(5) YUV(2)
AUD BCLK
YUV(0) YUV(1)
DV
DSUn
DV
DSLn
DV_PDn
DV
ASn
DV ERRn
DV LCn
IO(5)
IO(6)
IO(7)
IO(8)
IO(9)
IO(15)
IO(2)
IO(3)
IO(4)
IO(10)
IO(11)
IO(12)
IO(13)
IO(14)
IO(0)
IO(1)
AUD_WS_701
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
AUD SDI
DV_HS_IN
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
DV
VS
YUV(3)
44
VSS6
38
VSS5
32
VSS4
26
VSS3
20
VSS26
160
VSS16
98
VSS15
92
VSS14
86
VSS13
80
VSS12
74
VSS11
7404
NW700LQ
VSS9
56
VSS8
50
VSS7
VID DTACK
82
VID-D7
65
VID-D6
64
VID-D5
63
VID-D4
61
VID-D3
59
VSS25
152
VSS24
146
VSS23
140
VSS22
134
VSS21
128
VSS20
122
VSS2
14
VSS19
116
VSS18
110
VSS17
104
VCC3 3 6
36
VCC3 3 5
30
VCC3 3 4
24
VCC3 3 3
18
150
VCC3.3-25 VCC3.3-24
144
VCC3.3-23
138
VCC3.3-22
68
VSS10
62
VSS1
7
VID-VS
73
VID RDY
83
VID OE
81
VID-HS
75
VID-FLD
76
VCC3 3 14
84
VCC3.3-13
78
VCC3.3-12
72
VCC3.3-11
66
VCC3.3-10
60
VCC3 3 1
1
TEST
67
VID-D2
58
VID-D1
57
VID-D0
55
VID-CLK1
69
VID-CLK0
70
VCC3.3-9
54
VCC3.3-8
48
VCC3.3-7
41
RES9
71
RES8
53
RES7
52
RES6
51
RES5
49
132
VCC3.3-21
126
VCC3 3 20
120
VCC3 3 2
12
VCC3 3 19
114
VCC3 3 18
108
VCC3 3 17
102
VCC3 3 16
96
VCC3 3 15
90
HOST DTAC
8
HOST-DSU_
156
HOST-DSL_
155
HOST DRQ
9
HOST-CS_
158
HOST-AS_
153
HOST AD9
27
RES4
47
RES3
46
RES2
45
RES11
79
RES10
77
RES1
25
HOST AD7
23
HOST AD6
22
HOST AD5
21
HOST AD4
19
HOST AD3
17
HOST AD2
16
HOST AD15
35
HOST AD14
34
HOST AD13
43
HOST-R
W_
157
HOST-RST_
159
HOST-PD_
154
HOST LC
11
HOST ERR
10
DRAM RAS
85
DRAM LCAS
88
DRAM D9
118
DRAM D8
117
DRAM D7
115
DRAM D6
33
HOST AD12
31
HOST AD11
29
HOST AD10
28
HOST AD1
15
HOST AD0
13
HOST 16 8
2
GPIO3
6
HOST AD8
148
DRAM-D28
147
DRAM-D27
145
DRAM-D26
143
DRAM-D25
142
DRAM-D24
141
DRAM-D23
139
DRAM-D22
137
DRAM-D21
136
DRAM-D20
135
DRAM D2
GPIO2
5
GPIO1
4
GPIO0
3
DRAM WE
89
DRAM UCAS
87
125
DRAM-D13
124
DRAM-D12
123
DRAM-D11
121
DRAM D10
119
DRAM D1
106
DRAM D0
105
DRAM A8
103
DRAM A7
101
DRAM A6
100
113
DRAM D5
112
DRAM D4
111
DRAM-D31
151
DRAM-D30
149
DRAM D3
109
DRAM-D29
93
DRAM A0
91
AUD WS
37
AUD SDO
40
AUD-SDI
42
AUD BCLK
39
107
DRAM-D19
133
DRAM-D18
131
DRAM-D17
130
DRAM-D16
129
DRAM-D15
127
DRAM-D14
DRAM A5
99
DRAM A4
97
DRAM A3
95
DRAM A2
94
DRAM A1
100n 2400 100n 2403 2401 100n 2404 100n 2402 100n 100n 2405 100n 2406 2407 100n 100n 2408 100n 2411 2409 100n 2412 100n 2410 100n 100n 2413 100n 2414 2415 100n 100n 2416 2417 100n 100n 2420 100n 2418 2421 100n 2419 100n
5404
100MHZ
5402
100MHZ
3400
10K
F405
F417
F406
F404
F407 F408
F409
F410
F414 F412 F413
F401
F411
F403
F416
13
42 37
F402
29
16
15
EDO RAM
1Mx16
Φ
MT4LC1M16E5
7402
31
30
34
33
10
22
21 6 1
14
5
4
41
40
39
38
36
32
12
11
27
26
25
24
23
20
19
9
8
7
EDO RAM
1Mx16
Φ
18
17
35
3
2
28
MT4LC1M16E5
7403
13
42 37 22
21
10
9
8
6 1
14
29
16
15
32
36
35
3
2
12
11
31
30
34
33
20
19
18
17
7
5
4
41
40
39
38
28
27
26
25
24
23
100MHZ
5400
100MHZ
5401
5403
100MHZ
F425
F418
F400
3401-D
47R
47R
3401-A
47R
3401-C
3402-D
47R
3401-B
47R
47R
3402-C
3402-B 47R
47R
3402-A
F419
3404 47R
F420
F421
47R
3403
F422
47R
3405
F426
CL 16532145_017.eps
221101
2400 I6
2401 I6
2402 I6
2403 I7
2404 I7
2405 I7
2406 I8
2407 I8
2408 I8
2409 I8
2410 I10
2411 I10
2412 I11
2413 I11
2414 I11
2415 I12
2416 I13
2417 I13
2418 I14
2419 I14
2420 I14
2421 I15
3400 B4
3401-A H5
3401-B G5
3401-C H5
3401-D G5
3402-A H6
3402-B G6
3402-C H6
3402-D G6
3403
G6
3404 G7
3405 F3
5400 H10
5401 H13
5402 I5
5403 I10
5404 I13
7402 C9
7403 C11
7404 C4
F400 B4
F401 F3
F402 F4
F403 F3
F404 G6
F405 G7
F406 F5
F407 F5
F408 F5
F409 H6
F410 G6
F411 F6
F412 F6
F413 F6
F414 F6
F416 I9
F417 I15
F418 G7
F419 F6
F420 H6
F421 H6
F422 H7
F425 I12
F426 F4