Peritek VCD-V, User Manual

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Peritek
4-4 Theory of Operation
refreshed every 8 ms. They are refreshed using the CAS before RAS
refresh mode, which is controlled by the 34020's DRAM refresh logic.
This mode utilizes a refresh counter internal to the memory chip. When
CAS is asserted before RAS (the opposite of the normal order), the
memory chip executes a self-refresh cycle.
In general though, devices themselves (e.g. DUART, color maps) are only
eight bits wide, so the device registers, while located on 32-bit boundaries,
have at most 8 valid bits.
4.3 Graphics Board Clock Sources
There are several clock sources on the graphics board: a 40 MHz clock for
the 34020 and VMEbus/34020 arbitrator, a programmable phase locked
loop (PLL) pixel clock, a 14.7456 MHz reference oscillator for the pixel
clock PLL with a divide-by-4 to provide a 3.6864 MHz clock for the
DUARTs, and for the VCD-V (only) one or two fixed frequency pixel
clock oscillators (24.576 to 110 MHz).
Phase Locked Loop (PLL) Clock
The VCT-V, VCU-V, and some versions of the VCD-V incorporate a
programmable pixel clock oscillator (ICS1562-201AM) which allows the
user to program virtually any frequency pixel clock up to more than 200
MHz. In fact, only the VCU-V is capable of operating at such lofty
frequencies, and even then requires a special order BT468. The 1562 uses
the 14.7456 oscillator as its reference clock to drive an internal phase-
locked loop (PLL).
While a PLL clock is being phased into the VCD-V at the time of this
writing, most VCD-V configurations use a fixed frequency oscillator. The
video clock is connected to a GAL16V8-7 high speed PAL which is used
as a programmable synchronous divider controlled by the MACH110-
based horizontal control register. The function of the register changes
somewhat, depending on configuration. See Sections V.7 and V.8 for
detailed information. The divider output drives a counter in the MACH110
to provide shift and load clocks for the Video RAMs and blanking circuits.