Peritek VCD-V, User Manual

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Peritek
Theory of Operation 4-9
34020 Host Interface Arbitrator
When the arbitrator receives the request from the VMEbus, it asserts the
34020 control lines (HCS, HWR, HRD) and waits until the 34020
responds, typically within 100 ns. If data is being read from the 34020
side, then that data is loaded into the VMEbus/34020 32-bit bus
transceivers when the 34020 responds. If data is being written to the 34020
side, the bus transceivers are latched into the 34020-side 32-bit
address/bus, where it is loaded directly into memory or a device.
Once the reply phase is entered, the arbitrator sets VMEbus DTACK.
When VMEbus signals DS0 and DS1 go false, (which indicates that read
or write has become false), DTACK is negated.
VMEbus Block Mode
The VMEbus supports a high-speed data transfer method known as block
mode. According to the specification, up to 64 contiguous long words may
be transferred using the technique of implied addressing.
However, the
graphics board can support as many transfers as you wish.
Using the Address Modifier control lines, the bus master signals its intent
to initiate block transfers. It supplies a memory starting address and the
bus slave (i.e. the graphics board), using the 34020's block transfer
function, supplies its own addresses, which increments after each memory
cycle. This allows the bus master to skip the address output cycle, which
can result in significantly higher data transfer rates.
4.7 Display Memory
The memory devices used in the display memories are expressly designed
for high speed graphics applications. These devices are called video RAMs
(VRAMs). They are like ordinary DRAMs, but they also contain an
internal 512 x 8 line buffer. During a special data transfer cycle, an entire
row address worth of data is loaded into this line buffer. The VRAMs have
a mode control input (DT/OE), which is used to trigger a data transfer.
When DT/OE is active when RAS is asserted, a data transfer cycle occurs.
The row address selects a line of data, and the column address selects the
starting position within that line. The data are then shifted out by a serial
clock, 8 bits/clock appearing at the outputs.