Peritek VCD-V, User Manual

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Peritek
5-6 Programming On-board Devices and Memories
5.2.2 Line Address Register (LAR)
The LAR selects a memory or device register group on the board and
permits a 1K Byte segment to be accessed through the DBR. Fully
configured, the board contains a number of programmable devices, each of
which has between 2 and 16 control registers. The board uses spare LAR
values (0 and 400) to permit access to all of these devices through the
DBR line buffer.
See Section 5.2.3 for A32 addressing information.
Note
The 34020 must be initialized prior to accessing memories or devices.
Table 5-3 LAR Bit Definitions
LAR Memory Selected
0 34020 internal device registers. See Section 5.3 and 5.4 for
more information.
400 Device Buffer - Color map chip(s), DUARTs, PC Keyboard
controller, zoom register, cursors, and SCSI (
VCT/VCU ).
800 High Speed Data input port (HSP) - special order only
C00-CFF Digital Lookup Table ( VCD-V only)
2000-2FFF Up to 2 MB of Flash EEPROM, using four 512 KB devices.
Video RAM
VCD-V and VCU-V
4000-5FFF Primary (8-bit) graphics RAM - 1024 pixels for each LAR
value. 1K x 1K pixels is 1 MB or 1024 LARs. Memory is byte
addressable and writemask applies.
6000-7FFF Overlay (4-bit) graphics RAM - 1024 pixels for each LAR
value. The data is valid in each byte, but only the 4 low bits
are used. Memory is byte addressable and writemask applies.