Peritek VCD-V, User Manual

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Peritek
4-2 Theory of Operation
4.2 System Architecture
As noted before, this manual deals with all three of Peritek's 34020-based
graphics boards. The awkward places which result are in having to
delineate differences between boards, while maintaining a coherent flow in
the material. In this chapter, the overall board architecture and feature set
is the same. The most significant differences arise out of the variety of
display output options: 24 bit true color for the VCT-V, 8 bit color for the
VCU-V and VCD-V, and digital output for the VCD-V. Referring to the
block diagram appended to this chapter, it is evident that the VCD-V,
VCT-V, and VCU-V graphics boards are divided into two main sections:
the VMEbus interface section and the TMS34020 section.
VMEbus Interface
Rather than use a commercial VMEbus interface controller such as the
VIC064 or the SCV64, Peritek uses a proprietary chip set which is tailored
to the interface requirements of the 34020. Implemented in 3 high density
AMD MACH FPGA devices, the chip set includes control signals for the
VMEbus bus drivers, address decoders for the VMEbus, Control/Status
Register (CSR), Line Address Register (LAR), Line Buffer Address
Register (DBRADR), Extended Address Register (XAR), Interrupt Vector
Address Register (IVAR), an interrupt controller, VMEbus/34020
arbitrator and a byte swapper (see Section 5.3).
Control Registers
The 4 word CSR/LAR group and a 1 KB line buffer are all in the A16
space. A control bit can be used to enable A24 operation for the line buffer
when the VMEbus host doesn't support A16/D32 transfers. D32 capability
is important because long word data transfers will go twice as fast.
The CSR provides basic control over the board, including 34020 reset, line
buffer response enable, A24 enable, A32 enable, hardware byte swapper
enable, and interrupt enable. The LAR selects which 1 KB section of
memory or block of device registers is accessed through the line buffer.
The line buffer mechanism is used instead of direct addressing because the
internal memory capacity of the graphics board is in excess of 48 MB,
which is a substantial amount of address space, one that is outside the
reach of both A16 and A24 bus masters. Alternatively, the graphics board
can respond to a 64 MB section of A32 VMEbus address space, which
might be convenient for a disk controller. Note that Peritek software