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Peritek VCD-V, User Manual

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34020/VMEbus Host Interface ......................................................................................4-3

34020 Functional Unit ...................................................................................................4-3

34020 Data and Address Buses......................................................................................4-3

4.3 Graphics Board Clock Sources..............................................................................................4-4

Phase Locked Loop (PLL) Clock...................................................................................4-4

34020 Video and Processor Clock Synchronization ......................................................4-5

4.4 VMEbus Interface .................................................................................................................4-5

Address Decoding ..........................................................................................................4-5

Data Bus Transceivers and the Byte Swapper................................................................4-6

4.5 VMEbus Interrupt Controller ................................................................................................4-7

4.6 System Arbitration ................................................................................................................4-7

Control Register Decoding (CSRREQ)..........................................................................4-8

Line Buffer Decoding (IOREQ).....................................................................................4-8

34020 Host Interface Arbitrator.....................................................................................4-9

VMEbus Block Mode ....................................................................................................4-9

4.7 Display Memory....................................................................................................................4-9

VCD-V and VCU-V Pixel Size......................................................................................4-10

VCT-V Pixel Size ..........................................................................................................4-10

VCD-V Display Memory Size .......................................................................................4-10

VCU-V Display Memory Size .......................................................................................4-10

VCT-V Display Memory Size........................................................................................4-11

4.8 System Memory.....................................................................................................................4-11

SIMM Sockets ...............................................................................................................4-11

Flash EEPROM..............................................................................................................4-11

4.9 Programmed Logic Devices ..................................................................................................4-12

AMD MACH Field Programmable Gate Arrays (FPGA) ..............................................4-12

PAL22V10 Field Programmable Gate Array (FPGA) ...................................................4-12

Chapter 5 Programming On-board Devices and Memories ............................................5-1

5.1 Introduction ...........................................................................................................................5-1

5.2 VMEbus and Control Registers.............................................................................................5-3

5.2.1 Control/Status Register (CSR) .............................................................................5-4

5.2.2 Line Address Register (LAR) ..............................................................................5-6

5.2.3 A32 Address Map and the XARADR Address Match Register ...........................5-8

5.2.4 A16/A24 Address Map and DBRADR Address Match Register .........................5-9

5.2.5 VECADR Interrupt Vector Address Register ......................................................5-10

5.2.7 VMEbus Block Transfers (BLT) .........................................................................5-11

5.2.8 Device Register Access........................................................................................5-11

5.3 TMS 34020 Graphics Systems Processor..............................................................................5-14

5.3.1 34082 Floating Point Coprocessor.......................................................................5-15

5.3.2 Writemask Register..............................................................................................5-15

5.3.3 VRAM Color Register and Block Fill Special Function ......................................5-16

5.3.4 Memory Types and Sizes .....................................................................................5-17

5.3.5 Byte Ordering and the Hardware Byte Swapper ..................................................5-17

5.3.5a VMEbus and 34020 Byte Order Mapping .........................................................5-18

5.3.5b Example Code for Software Byte Swapping ......................................................5-19

Summary of Contents for VCD-V

Page 1: ...MANUAL Copyright c 1995 by Peritek Corporation 5550 Redwood Road Oakland CA 94619 510 531 6500 FAX 510 530 8563 email support peritek com Release 2 3 April 19 1995 Applies to VCT V FAB REV 4 and up VCU V FAB REV 4 and up VCD V FAB REV 2 and up ...

Page 2: ...Peritek ...

Page 3: ...Peritek ...

Page 4: ...References 1 8 1 4 General Specifications 1 9 1 5 Monitor Requirements 1 16 1 6 Configuration Information 1 16 Chapter 2 Installing Your Peritek Graphics Board 2 1 2 1 Introduction 2 1 2 2 Unpacking Your Board 2 2 2 3 VMEbus Installation 2 3 2 3 1 Default Interrupt Settings on Peritek Video Boards 2 3 2 3 2 Checking Board Addresses 2 4 2 3 3 Installing the Graphics Board 2 5 Figure 2 1 Example VME...

Page 5: ...Peritek ...

Page 6: ...Peritek ...

Page 7: ...3 High Speed Data Port HSP 2 28 2 5 4 8 bit SCSI Port VCT V and VCU V 2 29 2 5 5 Digital Video Connector VCD V only 2 30 Chapter 3 Software Summary 3 1 3 1 Introduction 3 1 3 2 Software Availability by Platform and OS 3 2 3 3 Write Posting 3 3 3 4 PX Windows Server 3 4 3 5 Graphics Subroutine Package 3 5 3 6 PTERM Terminal Emulator 3 8 3 7 Software Development Package 3 9 Features of the 34020 Dev...

Page 8: ...ogrammed Logic Devices 4 12 AMD MACH Field Programmable Gate Arrays FPGA 4 12 PAL22V10 Field Programmable Gate Array FPGA 4 12 Chapter 5 Programming On board Devices and Memories 5 1 5 1 Introduction 5 1 5 2 VMEbus and Control Registers 5 3 5 2 1 Control Status Register CSR 5 4 5 2 2 Line Address Register LAR 5 6 5 2 3 A32 Address Map and the XARADR Address Match Register 5 8 5 2 4 A16 A24 Address...

Page 9: ...trol Register Non ICS1562 VCD V s 5 39 5 6 BT463 Color Map Controller for the VCT V 5 43 5 7 BT468 Color Map Controller for the VCU V 5 47 5 8 BT459 Color Map Controller for the VCD V 5 50 5 9 BT482 Color Map Controller for the VCD V 5 53 5 10 VCD V Digital Lookup Table DLUT 5 57 5 11 Hardware Cursors 5 61 5 12 Serial I O Ports DUART 5 64 5 13 SCSI Port 5 66 5 14 PC Keyboard Controller 8242PC 5 69...

Page 10: ...Peritek ...

Page 11: ... in one manual because their feature set is largely the same and the software is identical This manual is broken down into six chapters Chapter 1 Overview of the Peritek graphics boards Chapter 2 Installing Peritek graphics boards Chapter 3 Summary of Peritek s Software Products Chapter 4 Theory of Operation Chapter 5 Programming On board Devices and Memories Chapter 6 Troubleshooting Chapter 1 pr...

Page 12: ...ur problems do one of the following 1 call Peritek technical support at 510 531 6500 2 fax your questions to 510 530 8563 3 or send E mail to support peritek com If your problem is monitor related Peritek technical support will need detailed information about your monitor Manual Revisions Revision 2 0 January 11 1995 First Word for Windows 2 0 Master Revision 2 1 March 27 1995 Compensate for WFW b...

Page 13: ...ponents described in this manual are subject to change without notice Although it regrets them Peritek Corporation assumes no responsibility for any errors or omissions that may occur in this manual Peritek Corporation assumes no responsibility for the use or reliability of software or hardware that is not supplied by Peritek or which has not been installed in accordance with this manual PX Window...

Page 14: ...in code fragments are preceded by the system prompt a percentage sign the standard prompt in UNIX s C shell a dollar sign the OS 9 prompt or the hash mark the standard UNIX prompt for the Super User Note Note boxes contain information either specific to one or more platforms or interesting background information that is not essential to the installation Caution Caution boxes warn you about actions...

Page 15: ...ew of the VCT V VCD V and VCU V graphics controllers Additional sections contain a bibliography specifications monitor requirements and common configurations This is summary information and is not critical to the one who wishes to press on to the installation procedures which are contained in Chapter 2 ...

Page 16: ...V offers both analog and digital The common feature set of the VCU V VCT V and VCD V includes 40 MHz 34020 Optional 34082 Floating Point Unit FPU 4 RS 232 serial I O ports PC Keyboard 4 Kb serial EEPROM up to 2 MB autoboot Flash PROM up to 32 MB 34020 memory Optional multiple display pages Hardware pan zoom and scroll Hardware bitmapped cursors 4 bit overlay SIMMs for display and 34020 memory PLL ...

Page 17: ...gital flat panel outputs digital is limitied to 1024 x 768 simultaneous analog and dital operation with VGA timing compatible panels and up to two pages of 1280 x 1024 display Programmable screen resolution ranges from 640 x 480 pixels up to 1280 x 1024 with refresh rates between 30 and 72 Hz vertical and 15 7 to 73 KHz horizontal refresh rates non interlaced or non interlaced including NTSC sync ...

Page 18: ...t conforms to the IEEE floating point standard 754 1985 for binary floating point single or double precision addition subtraction multiplication division square root and comparison In addition it offers 32 bit integer arithmetic logical comparisons and shifts Complex operations for graphics support include matrix operations 1 x 3 3 x 3 1 x 4 and 4 x 4 backface testing polygon elimination and clipp...

Page 19: ...simple console terminal emulator combined with the graphics subroutine package or X11R6 X Windows server Display Features All boards support binary vertical zoom 1 2 4 8 16 32 horizontal zoom except some VCD Vs multi pixel horizontal pan and vertical smooth scroll For the VCD V and VCU V the display memory data is directed to the analog monitor via a Brooktree RAMDAC color map control chip which p...

Page 20: ...e CSR contains device interrupt enables line buffer response enable and 34020 hardware reset The LAR is a 16 bit register which maps a portion of the address space of the graphics board into a 1 KB line buffer Two additional registers include programmable line buffer address interrupt vector address and programmable extended address A32 decoder Access to the board through the A16 space provides a ...

Page 21: ...to minimize the possibility of data overrun Each channel has an internal loopback mode for testing An 8242PC keyboard controller gives a PC compatible keyboard port and a PS 2 mini DIN connector is used The VCU V and VCT V also have an optional 8 bit Small Computer Systems Interface SCSI peripheral port All three designs can be supplied with a 32 bit High Speed Port HSP which allows 32 bit data to...

Page 22: ...neration Tools Order SPVU020B SCN2681 Dual Asynchronous Receiver Philips Semiconductors Transmitter DUART Data Sheet 811 E Arques Avenue Signetics Microprocessor Data Manual Sunnyvale CA 94088 3409 1986 pages 2 189 to 2 208 800 234 7381 BTxxx Product Descriptions Brooktree Corporation 9950 Barnes Canyon Road Product Data Book 4th Edition San Diego CA 92121 619 452 7580 NCR5380 SCSI Processor NCR M...

Page 23: ... display data It is expandable in steps of 4 8 16 and 32 MB A minimum of 4 MB is required for PX Windows PROM Memory Four 8 bit Flash PROMs support no wait state firmware storage of up to 2 MB total of 32 bit wide permanent storage A user jumper allows the board to auto start from EPROM Peritek can supply dumb terminal emulation PTERM Graphics Subroutine Package CnP and Peritek s PX Windows X11R6 ...

Page 24: ...he display memory is expandable to 8 MB The 2M option can give either 1280 x 1024 displayable or two pages of 1024 x 1024 pixels The 4M option can give two pages of 1280 x 1024 displayable or four pages of 1024 x 1024 pixels The basic display memory size for the VCU V is 2 MB which provides 2048 x 1024 addressable pixels 8 bit pixel primary 4 bit pixel overlay The memory is expandable to 16 MB The...

Page 25: ...works correctly with interlaced displays The VCD V uses a Brooktree BT459 RAMDAC for high frequency above 1024 x 768 analog displays The BT459 contains a 64 x 64 x 2 bitmapped cursor which does not work correctly with interlaced displays The VCD V digital output consists of a 32K x 8 lookup table LUT and a 32 x 32 x 2 bitmapped cursor controller 8 bit primary 4 bit overlay and 2 bit cursor data ar...

Page 26: ...al Small Computer Systems Interface SCSI peripheral port using an NCR 5380 controller supports up to 7 high speed 1 MB second 8 bit parallel intelligent devices It allows any compatible device such as a SCSI disk to be used For improved performance an alternate port address mode allows the 34020 to utilize the 5380 pseudo DMA mode which automatically operates the SCSI handshake lines during data t...

Page 27: ... register block in the A16 space which contains the Control Status Register CSR Line Address Register LAR Line Buffer Address Register Extended Address Register and Interrupt Vector Address Register VMEbus Interrupts VMEbus interrupt controller supports a vectored interrupt from the 34020 Bus Loading Two bus loads Data Strobe to DTACK Times were measured using an HP1650A logic analyzer at the VME ...

Page 28: ...nochrome and color panels have been tested and qualified In the case of color panels 9 bit panels such as the LQ10DH011 are connected 3 bits red 3 bits green and 2 bits blue Contact Peritek about information regarding panel compatibility Serial Connector DB 9 connectors are provided for the console and mouse connectors A 4 pin modular phone RJ 11 connector is provided for the LK401 type keyboard W...

Page 29: ...024 x 768 70 Hz 60 KHz 55 MHz 1024 x 1024 57 Hz 60 KHz 80 MHz 1024 x 1024 60 Hz 64 KHz 100 MHz 1280 x 1024 67 Hz 64 KHz 110 Mhz 1280 x 1024 72 Hz 72 KHz 125 MHz 1600 x 1280 60 Hz 79 KHz 170 MHz See Table 5 14 for more initialization table information Composite Video Signal 1 Volt peak to peak consisting of 660 mV Reference White 54 mV Reference Black 286 mV Sync Level ...

Page 30: ...CU V Horizontal refresh rate 55 KHz VCD V 70 KHz VCT V 90 KHz VCU V 1 6 Configuration Information The basic graphics board includes 40 MHz TMS 34020 Graphics Systems Processor 1 page 1024 x 1024 of display memory 1 MB 34020 memory hardware cursors hardware pan scroll and zoom hardware byte swapper VMEbus interrupts Everything else is controlled by the options Please contact Peritek and or refer to...

Page 31: ...able X12 1280 x 1024 display 2048 x 1024 addressable X16 1600 x 1280 display 2048 x 2048 addressable nSM 34020 system memory in megabytes where n 4 8 16 or 32 2M 2 pages of 1024 x 1024 2048 x 1024 addressable pixels primary and overlay 4M 4 pages of 1024 x 1024 2048 x 2048 addressable pixels primary and overlay 8M 8 pages of 1024 x 1024 2048 x 4096 addressable pixels primary and overlay SC SCSI po...

Page 32: ...lved in getting your Peritek Graphics board to work in your system Unpack and install the Peritek graphics board Install the software This chapter shows you how to install the Peritek graphics board in your computer The PX Windows Manual and the Graphics Subroutine Package Manual provide instructions on how to install the software ...

Page 33: ...tall it It is preferable to wear a grounded wrist strap whenever handling computer boards Some operating systems require that you reboot your system after installing a device driver because only after the reboot will your system utilize the driver and recognize the board If yours is such an operating system you might like to install PX Windows or the Subroutine Package before installing the board ...

Page 34: ... for interrupt level 3 IRQ3 If you change this setting the device driver needs to be changed accordingly Peritek boards have a programmable interrupt vector address which is usually set by the software to default to E0 hex However some platforms such as Sun permit the vector to be chosen transparently by the operating system In these cases you do not need to specify an interrupt vector address Mak...

Page 35: ...ble 2 1 VMEbus graphics board addresses Standard Address Address Type Data Type Control Registers xxxxC000 xxxxC00F A16 D16 D32 Line Buffer xxxxy000 xxxxy3FF A16 D8 D16 D32 Full Memory A0000000 A3FFFFFF A32 D8 D16 D32 Interrupt Vector E0 D8 interrupter The xxxx is a place holder for digits that are processor specific Some common values are shown in Table 2 2 Full memory settings are only used in m...

Page 36: ...pt Vector are software configurable 2 3 3 Installing the Graphics Board Use the following procedure to install the Peritek graphics board into the VMEbus backplane 1 Shut down the operating system and turn off the power Warning Never open the computer without turning off the power supply Unless internal AC wiring is exposed leave the power cord plugged in so as to ground the computer chassis You c...

Page 37: ...pare 5 Spare 6 Spare 7 Spare Spare Spare v Spare 21 Spare Note Note There must not be any open slots between the first and last boards which use either DMA or interrupts this includes the Peritek graphics board which uses interrupts The shorting jumper for Slot 2 IAKIN OUT should be removed assuming the graphics board is installed in that slot Shorting jumpers should be installed for all unused sl...

Page 38: ...ound It is preferable to wear a grounded wrist strap whenever handling computer boards Handle the graphics board only by its edges Oils from your hand can break down the metal used in the circuit board 5 After making sure the board is seated correctly tighten the screwlock on each end of the board 6 Close the computer and plug the video cable into the monitor and the graphics board Make sure to pl...

Page 39: ...ectors labeled M K C and S These letters stand for mouse keyboard console and special The S plug is not used Plug the other three connectors in to the mouse keyboard and the console ports on your computer Plug the mouse cable into the 9 pin male connector labelled MOUSE Plug an LK201 or LK401 keyboard into the RJ 11 socket labelled LK401 or plug a PC keyboard with a PS 2 style connector or adapter...

Page 40: ... messages on the screen If none appear make sure the console connector is correctly plugged in and the console terminal parity and data bits are set correctly see Jumper Settings Once you have a picture on the screen you may need to adjust the width height brightness contrast and hold controls on your monitor to get a good centered image If these controls don t adjust the image properly the parame...

Page 41: ...Peritek 2 10 Installing Your Peritek Graphics Board Figure 2 2 Jumper Locations for the VCT V and VCU V ...

Page 42: ...Peritek Installing Your Peritek Graphics Board 2 11 Figure 2 3 Jumper Locations for the VCD V ...

Page 43: ...V and VCT V FAB REV 4 and on to a non standard configuration Refer to Figure 2 3 Jumper Option Locations for VCD and VCT VCU previous two pages for jumper locations For wire wrap changes only KYNAR or TEFLON not enamel or plastic coated insulated wire should be used 2 4 1 CSR Addresses The address range for the CSR block is jumper selectable to certain addresses in A16 space As configured at the f...

Page 44: ...C03F Alternate 4 7 xxxx80n0 xxxx80nF A14 A5 A4 Alternate 8 11 xxxx40n0 xxxx40nF A15 A5 A4 Alternate 12 15 xxxx00n0 xxxx00nF A14 A15 A5 A4 Note xxxx depends on host processor s A16 VMEbus address space 2 4 2 Interrupt Grant Receive Acknowledge The VMEbus has a seven level interrupt grant receive acknowledge protocol which requires each board to acknowledge that it is responding to the interrupt gra...

Page 45: ...uest priority is jumper programmable for the seven levels 1 7 The lower the priority number the less likely the board will be serviced The Interrupt Request Priority jumper is located to the left side of J1 VME P1 connector and is labeled JP1 The pin layout is as follows Figure 2 5 Interrupt Priority Jumpers IRQ7 IRQ3 IRQ6 IRQ2 IRQ5 IRQ1 J1 IRQ4 IRQ Caution The Vector Priority setting must match t...

Page 46: ... Peritek VCD V Program Voltage Enable As shown in Figure 2 2 install a jumper between pins 2 and 3 of JP6 VCT V and VCU V Program Voltage Enable As shown in Figure 2 3 install a jumper between pins 2 and 3 of JP6 Caution Remove the jumper once you are done programming 2 4 5 Autoboot Enable The graphics boards can run automatically from on board EEPROM on powerup or anytime SYSRESET is asserted Per...

Page 47: ...here one page 1024 x 1024 pixels On the VCD V the jumpers are part of jumper strip JP5 Figure 2 6 VCD V DRAM and VRAM Size and Autoboot Enable GRD GRD GRD GRD GRD GRD GRD D0 D1 V0 V1 resv resv BEN RP4 On the VCT V and VCU V the jumpers are part of jumper strip JP19 Figure 2 7 VCT VCU DRAM and VRAM Size Lower edge of U27 MACH230 GRD D1 GRD D0 GRD V1 GRD V0 GRD resv The tables on the next page shows...

Page 48: ...requency pixel clock to be chosen Peritek distributes an number of standard initialization tables and can provide custom versions upon request See Section 5 4 for more information The VCU V uses the ICS1562 clock chip which actually gives a maximum pixel clock in excess of 200 MHz Note that the BT468 color map chip must be upgraded from its standard 170 MHz to take advantage of this The VCT V uses...

Page 49: ...nd VCD V X12 type boards will operate in interlaced mode but the cursor appearance and positioning will not be correct This is because the cursor built into the color map does not know about interlaced operation In order to run the VCU V in 640x480 interlaced mode or any mode with a pixel clock of less than 18 25 MHz the blanking jumper must be changed to the slow mode This jumper is labeled JP7 a...

Page 50: ...TERM Keyboard data send from PTERM to the host is not flow controlled with XON XOFF PTERM has a 8KB input buffer so that it can handle bursts of up to 8KB without requiring XON XOFF flow control The RTS CTS flow control is done by programming the UART to enable UART control of the RTS CTS lines THIS OPTION HAS NOT BEEN COMPLETELY TESTED It is unlikely that the CTS signal will be asserted because t...

Page 51: ... 12 volt outputs should not exceed 5 A There is a 470 ohm current limiting resistor in the 12 volt line There is a 1K ohm current limiting resistor power source to the Mouse Connector pins 4 and 7 Table 2 7 Mouse Port or CnP Port 0 DUART 0 channel A Jumper Mouse Connector Pin Option Default JP8 1 2 pin 3 to 12V yes JP8 2 3 pin 3 to Port 0 TX no JP20 1 2 pin 6 to Port 1 RX no JP21 1 2 pin 8 to Port...

Page 52: ...P13 1 2 pin 7 to CTS yes JP13 2 3 pin 7 to Port 3 RX no JP12 1 2 pin 8 to RTS yes JP12 1 3 pin 8 to Port 3 TX no JP11 1 2 only pin 9 to fused 5A 12 volts no JP11 2 3 only pin 9 to fused 5A 5 volts no The console port is a DB9 female connector At the connector CTS is an input and RTS is an output Not all installations require these signals Table 2 10 Extra Port or CnP Port 3 DUART 1 channel B No co...

Page 53: ...anged from earlier revisions The 34020 emulator connector while still included in the PCB artwork has been deleted as an orderable option It is for factory use only Contact Peritek if you need emulator connections There are five unique connectors installed on the VCU V VCT V and VCD V An additional 26 pin header is installed on the VCD V for digital output The connectors include Section 2 5 1a a c...

Page 54: ...lly when an overload is removed The Peritek Graphics Subroutine Package CnP includes general purpose serial I O routines but has no knowledge of the device connected to the port Sample programs exist which process keyboard and mouse inputs but no intelligent keyboard or mouse software is available That is why we have PX Windows Peritek can supply cables and devices please contact the factory for o...

Page 55: ...If no keyboard is installed the default is the LK401 The PX Windows mouse or trackball should be a 3 button Mouse Systems protocol 5 byte device although the 2 button Microsoft Mouse protocol is now supported The Peritek Optical Mouse is a Mouse Systems Serial PC Mouse It uses optical technology for postioning thus requiring a small pad which is included Peritek can also supply the low cost Perite...

Page 56: ...le D Sub connector to pass data and power to the mouse which requires 12 and 12 Note If you experience difficulty getting a device to work especially a Mouse or Trackball you may be drawing too much current from pins 3 4 or 7 There are current limiting resistors in series with the power sources for these lines Table 2 12 Mouse Connector Pinout 9 pin D Sub Pin Number Description 1 not used 2 Data f...

Page 57: ...m Serial Keyboard 2 Fused 12 Volts 3 Ground 4 Data to Serial Keyboard Peritek PC Keyboard The Peritek PC Keyboard is suitable for applications which do not require long cables because it uses a TTL level electrical protocol which cannot support cable lengths in excess of about 10 feet 3rd party cable extender amplifiers are available to overcome this limitation Peritek uses the mini DIN PS 2 keybo...

Page 58: ... so equipped The direction of the TTL Dot Clock Vertical Composite Sync and Horizontal Sync and the polarity of the Sync signals are controlled by a combination of jumpers and the Zoom Control Register see Section 5 5 Table 2 15 Video Connector Pinout Pin Description Pin Description 1 RED 8 GND 2 GREEN 9 GND 3 BLUE 10 GND 4 NC 11 HSYNCIN for genlock option 5 GND 12 VSYNCIN for genlock option 6 GND...

Page 59: ..._12 A7 active high VCD input 74ACT374 74ACT652 DATA_13 C7 active high VCD input 74ACT374 74ACT652 DATA_14 A8 active high VCD input 74ACT374 74ACT652 DATA_15 C8 active high VCD input 74ACT374 74ACT652 DATA_16 A9 active high VCD input 74ACT374 74ACT652 DATA_17 C9 active high VCD input 74ACT374 74ACT652 DATA_18 A10 active high VCD input 74ACT374 74ACT652 DATA_19 C10 active high VCD input 74ACT374 74A...

Page 60: ...ctive A2 Data Bit 1 Low Active 4 Data Bit 1 Low Active A3 Data Bit 2 Low Active 6 Data Bit 2 Low Active A4 Data Bit 3 Low Active 8 Data Bit 3 Low Active A5 Data Bit 4 Low Active 10 Data Bit 4 Low Active A6 Data Bit 5 Low Active 12 Data Bit 5 Low Active A7 Data Bit 6 Low Active 14 Data Bit 6 Low Active A8 Data Bit 7 Low Active 16 Data Bit 7 Low Active A9 Data Bit Parity Low Active 18 Data Bit Parit...

Page 61: ...itek s experience that if the panel and the graphics board are powered on and off simultaneously that additional sequence control is not required Nevertheless some users feel more strongly The VCD V as it exists today does not include sequenced power An ECO procedure does exist and can be supplied if necessary The next circuit revision available 4 95 will include sequenced 5 and 12 sources on the ...

Page 62: ...0 0 0 0 0 0 1 1 Green 0 0 0 1 1 1 0 0 Light Blue 0 0 0 1 1 1 1 1 Red 1 1 1 0 0 0 0 0 Purple 1 1 1 0 0 0 1 1 Yellow 1 1 1 1 1 1 0 0 White 1 1 1 1 1 1 1 1 Red Scale 0 0 0 0 0 0 0 0 darker 1 0 0 0 0 0 0 0 brightest 1 1 1 0 0 0 0 0 Green Scale 0 0 0 0 0 0 0 0 darker 0 0 0 1 0 0 0 0 brightest 0 0 0 1 1 1 0 0 Blue Scale 0 0 0 0 0 0 0 0 darker 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 brightest 0 0 0 0 0 0 1 1 ...

Page 63: ...4 23 Pixel Clock n a 1 2 2 CN1 1 25 26 5 Volts use direct power supply connection 2 Ground n a 2 1 1 2 4 Ground n a 5 5 6 Ground n a 6 8 Ground n a 9 9 8 10 Ground n a 10 12 Ground n a 13 13 12 14 Ground n a 14 15 15 16 Ground n a 16 18 24 Ground n a Computer power supply 5 18 17 17 CN2 1 2 12 20 19 19 Ground 19 20 20 CN2 3 4 Lighting n a Backlit Backlit Backlit Edgelit Power Sequencing n a yes ye...

Page 64: ... bit 3 21 A3 D13 9 Pixel 0 Data bit 0 20 B4 D00 11 Pixel 0 Data bit 1 19 A4 D01 13 Pixel 0 Data bit 2 18 B5 D02 15 Pixel 0 Data bit 3 17 A5 D03 17 no connect 19 Horizontal Sync 11 A8 HSYNC 21 Vertical Sync 9 A9 VSYNC 23 Pixel Clock 2 13 A7 2CLK 25 26 5 Volts use direct power supply connection 2 4 6 8 Ground 10 Ground 10 B9 GND 12 Ground 12 B8 GND 14 Ground 14 B7 GND 16 18 20 22 24 Ground Power Sup...

Page 65: ...al sets for the PX Windows and Graphics Subroutine Package products Peritek provides software for the VCU V VCT V and VCD V including Peritek PX Windows X11R6 X Windows Server 34020 Compiler Tools Peritek simple console Terminal emulator PTERM and a comprehensive Graphics Subroutine Package generically CnP The following table summarizes the current availability Contact Peritek if your choice is no...

Page 66: ...es yes SGI 5 R3000 yes yes Solaris 2 3 SPARC yes no SunOS 4 1 3 SPARC yes yes Unix V68 SVR3 68K yes yes Unix V88 SVR4 88K yes yes VMEexec 68K 3 0 68K yes no VMEexec 88K 3 0 88K yes no VxWorks 5 1 68K yes yes VxWorks alpha 5 1 Alpha yes no VxWorks sparc 5 1 SPARC yes no In addition to being available on tape media the board side of PX Windows PTERM and CnP Subroutine Package can be provided in PROM...

Page 67: ...accesses to the VMEbus which the Peritek baords use it can happen that the a write of the Peritek graphics board Line Buffer can occur before a write to the Line Address Register LAR has been completed If you had wanted to change the LAR and then write you are not guaranteed that this has happened This results in incorrect operation The way to get around this is to immediately read back the data w...

Page 68: ...3 button compatible pointing devices i e mouse or trackball X Windows is a machine independent network based windowing system It divides graphics functions into two parts 1 The server which controls the hardware dependent functions such as the mouse keyboard or trackball and graphics display and 2 The client s which is are the actual programs which the user wants to interact with This might includ...

Page 69: ...nder a shell on the graphics board and provide functions for the board All characters are software defined patterns which are drawn in the graphics memory The subroutine package supplies a variety of bit mapped fonts including contemporary and typewriter styles in different weights and pitches Two versions of CnP are included a A hybrid version wherein a front end process running in the host compu...

Page 70: ...get_last_ch get_leading get_width Font Management Functions get_font_max install_font select_font Graphics Output Functions bound_fill bound_patnfill draw_line draw_oval draw_ovalarc draw_point draw_polyline draw_rect fill_convex fill_oval fill_piearc fill_polygon fill_rect frame_oval frame_rect patnfill_oval patnfill_polygon patnfill_rect patnfill_convex patnfill_piearc patnframe_oval patnframe_r...

Page 71: ...lswrt Viewport Functions close_vuport copy_vuport cpw get_vuport_max move_vuport open_vuport select_vuport set_cliprect set_origin size_vuport Miscellaneous Functions delay lib_id lmo rmo peek_breg poke_breg rep_pixel wait_scan xytoaddr pan panrl zoom_vert zoom_horiz Double Precision Functions acos asin atan atan2 ceil cos cosh cotan exp fabs floor fmod frexp ldexp log log10 modf pow sin sinh sqrt...

Page 72: ...ows can be started whereupon PTERM ceases to function Console terminal output can be redirected to an xterm window By running a special program PX Windows can be killed and PTERM restarted There is at this time no hot key function to permit dynamic switching A cable is connected between the host computer s console port and the graphics board Console Port In addition a Peritek keyboard must be conn...

Page 73: ... applications is available from Peritek Its general characteristics are described below Contact Peritek for availability Figure 3 1 Software Development Flow C source files C compiler object files assembler source archiver assembler object libraries COFF object files V V graphics subroutinel ibrary linker LD DMP GO HLT OFF WT and TIDTSK ...

Page 74: ... functions and returning structures from functions Assembly Language output is generated by the compiler from the C source An interlist utility associates each C source line with its corresponding assembly code output The Assembler translates the assembly language source output from the compiler into 34020 machine language object files The Linker combines all object files into a single executable ...

Page 75: ... TIDTSK 3 8 11 Formatted dump of COFF data 5 4 34020 initialization table examples 3 8 1 Initialization Tables Programs which initialize the graphics board are shipped in source and executable form Initialization parameters that are used within some programs are provided as ASCII files A list of tables is provided in Section 5 4 Both PX Windows and CnP are distributed with a host of tables appropr...

Page 76: ...nVINT was designed to run before the Graphics Subroutine Package is loaded into the board VCnVINT has several command line options which supports specification of a non standard CSR address and line buffer addresses Refer to the sample scripts for the different OS s to see how to use this program A number of standard initialization tables are supported and are supplied See Section 5 4 for more inf...

Page 77: ...n In this test a unique value is stored at each address in the memory region under test As each location is written into an immediate readback is performed to rule out RAM and data line failures After every address in the memory region under test has had a unique value written to it readback of the whole memory is performed If a non unique location is found i e an addressed location does not conta...

Page 78: ...VCnVLD does not wait for the 34020 task to complete before exiting You also have the same non standard CSR and line buffer options available in VCnVINT 3 8 6 VCnVWT Purpose Wait for a task started by VCnVLD to complete This program duplicates the second half of VCnVLD If you didn t run VCnVLD with the wait option you can wait later by running this program 3 8 7 VCnVHLT Purpose Halt a program runni...

Page 79: ... program especially if you have boards which share the same line buffer addresses 3 8 10 VCnVDMP Purpose Dumps formatted portions of board memory to the terminal This program is useful for dumping the 34020 register block or video memory Output is similar to the Unix od command Command line options allow on to specify address type and format and data size and format 3 8 11 TIDTSK Purpose Provides ...

Page 80: ...evant information about the devices Otherwise we depend on the manufacturer s data sheet to provide complete information Section 1 2 contains a complete Functional Description Please refer to that section before continuing with this chapter This chapter has the following sections 4 2 System Architecture 4 3 Master Clock 4 4 VMEbus Interface 4 5 VMEbus Interrupt Controller 4 6 System Arbitration 4 ...

Page 81: ...address decoders for the VMEbus Control Status Register CSR Line Address Register LAR Line Buffer Address Register DBRADR Extended Address Register XAR Interrupt Vector Address Register IVAR an interrupt controller VMEbus 34020 arbitrator and a byte swapper see Section 5 3 Control Registers The 4 word CSR LAR group and a 1 KB line buffer are all in the A16 space A control bit can be used to enable...

Page 82: ...nother except for passing data back and forth once loaded with a program and started the 34020 can run independently of the VMEbus host Except for the CSR group the 34020 has complete control over the functions of the board The VMEbus going through the 34020 host interface also has ready access to those functions The 34020 provides a very fast and efficient interface to the host supporting byte op...

Page 83: ...ed frequency pixel clock oscillators 24 576 to 110 MHz Phase Locked Loop PLL Clock The VCT V VCU V and some versions of the VCD V incorporate a programmable pixel clock oscillator ICS1562 201AM which allows the user to program virtually any frequency pixel clock up to more than 200 MHz In fact only the VCU V is capable of operating at such lofty frequencies and even then requires a special order B...

Page 84: ...s two devices connected to the VMEbus a bus address register BAR and 32 bit bidirectional data transceiver The BAR is actually part of a MACH230 which latches the address bits and provides A16 A24 and A32 address decode ranges and block transfer requests as determined by the CSR programmable address decoder registers Address Decoding XMEMON is connected to the A32 main memory address decoder XMEMO...

Page 85: ...ide a 32 bit path for data transfers between the VMEbus processor and the on board devices during programmed I O cycles Since the board as a VMEbus slave must support D32 D16 and D8 bus transfers the byte swapper which sits in the data path is used to pass 32 bit data straight to the 34020 side or to multiplex data from the high data bits to the low data bits for D16 and D8 transfers Note that acc...

Page 86: ...res A01 A03 with the vector priority select jumpers VPSEL0 2 If there is not a match it will drive IAKO as outlined above If there is a match it will cause a read of the 8 bit Interrupt Vector Register IVAR The board will drive the contents of the IVAR into bits 0 7 of the transceivers Bits D08 D31 are not driven by the board They are pulled high by the VMEbus terminators The interrupt cycle then ...

Page 87: ...0 related functions CSR group When the arbitrator receives a valid request it grants access by asserting VSTRB and gating the address and data onto the board s internal busses Once the operation is complete about 100 ns DTACK is set terminating the VMEbus request Line Buffer Decoding IOREQ IOREQ is used to request 34020 related functions A valid LAR see Section 4 2 and an offset into the line buff...

Page 88: ...upport as many transfers as you wish Using the Address Modifier control lines the bus master signals its intent to initiate block transfers It supplies a memory starting address and the bus slave i e the graphics board using the 34020 s block transfer function supplies its own addresses which increments after each memory cycle This allows the bus master to skip the address output cycle which can r...

Page 89: ...are allocated for the primary and overlay memories VCT V Pixel Size On the VCT V pixel memory size is 24 bits for primary and 8 bits for overlay The overlay actually only uses the low 4 bits because that is all the color map will use The primary and overlay share the same address space the primary uses the low 24 bits of each word and the overlay uses the top 8 bits The writemask is very useful on...

Page 90: ...ces for the graphics board are comprehensive and consist of four components SIMM sockets for field upgradability and Flash EEPROM Section 5 3 4 has address ranges and memory maps for the DRAM and EEPROM memories SIMM Sockets The graphics board is built with SIMM sockets because it allows considerable manufacturing flexibility 1 MB 4 MB 8 MB 16 MB and 32 MB units can be fit into the same slot with ...

Page 91: ...exibility All parts are EEPROM technology which permits easy reprogrammability The MACH parts are essentially 26V16 building blocks linked by a partially implemented crossbar switch built into a single package The MACH210 part has two blocks and the 230 has four blocks Registered and asynchronous I O pins abound and I O and buried register per pin capability global clocks and resets are included T...

Page 92: ... as a 32 bit registered bus transceiver with byte word and long data swapping All data passing between VMEbus and 34020 side goes through this device VCDTU11 PALC22V10 Supplies CAS lines for display and system memory Decodes LAD0 3 to support VRAM block fill Different versions are required for VCD VCT and VCU VCDTU234 MACH435 A16 A24 A32 space VMEbus decoder CSR bits 0 15 LAR bits 0 15 A16 A24 DBR...

Page 93: ...our pixels in a VRAM for simultaneous writing from the VRAM color register Table 4 3 VCD Unique PLD Device Summary Part Device Number Type Description VCDV19 MACH230 Used for VCD Zoom control register Provides GAL crystal clock and ICS1562 3 wire control interface Provides programmable polarity for HSYNC and VSYNC Supports external sync genlock function Controls blanking VRAM shift clocks and VCLK...

Page 94: ...Peritek Theory of Operation 4 15 Figure 4 1 VCD V Block Diagram ...

Page 95: ...Peritek 4 16 Theory of Operation Figure 4 2 VCU V Block Diagram ...

Page 96: ...Peritek Theory of Operation 4 17 Figure 4 3 VCT V Block Diagram ...

Page 97: ...he manual have been removed as they are little used They are still available upon request This chapter covers the special programming features of the individual devices used on the graphics board It is intended to supply information unique to the board or to the application of a particular chip Section 1 2 provides a list of appropriate publications which include manufacturer s data sheets and man...

Page 98: ...owing sections 5 1 Introduction 5 2 VMEbus and Control Registers 5 3 34020 5 4 Board Initialization Tables 5 5 Vertical and Horizontal Zoom Register 5 6 BT463 Lookup Table VCT V LUT 5 7 BT468 Lookup Table VCU V LUT 5 8 BT459 Lookup Table VCD V High Resolution Analog LUT 5 9 BT482 Lookup Table VCD V Low Resolution Analog LUT 5 10 Digital Lookup Table VCD V DLUT 5 11 Hardware Cursors 5 12 2681 Seria...

Page 99: ...e might say the lowest common denominator A16 space is the most general and there is a minimal performance impact for using the line buffer Thus Peritek software supports A16 A24 space addressing only The standard addresses are shown in Section 2 4 1 For linear address access to the entire board it can also respond to a 64 MB byte addressable section of the 32 bit VMEbus memory map Contact Peritek...

Page 100: ...ations see Section 2 4 1 Note CSR group registers should be accessed as words not long words because the high word will not read back useful data 5 2 1 Control Status Register CSR Table 5 1 CSR Bit Summary Bit Mnemonic Function R W Reset 15 spare was BIGEND now reads back 0 no no 14 REVFLAG was r w now read back set no no 8 13 spare not used reads back 0 no no 7 A24EN clear A16 DBR access set A24 ...

Page 101: ...es byte swapping in the DBR A16 or A24 address range Note that when this bit is set the DBR address range expands to 4 KB from 1 KB VINTEN allows the 34020 on the board to interrupt the VMEbus When entering the interrupt service routine VINTEN should be cleared To avoid spurious interrupts be sure that the 34020 s interrupt request flag has dropped before reenabling VINTEN Interrupts are level sen...

Page 102: ... devices Table 5 3 LAR Bit Definitions LAR Memory Selected 0 34020 internal device registers See Section 5 3 and 5 4 for more information 400 Device Buffer Color map chip s DUARTs PC Keyboard controller zoom register cursors and SCSI VCT VCU 800 High Speed Data input port HSP special order only C00 CFF Digital Lookup Table VCD V only 2000 2FFF Up to 2 MB of Flash EEPROM using four 512 KB devices V...

Page 103: ...rder 1K bytes for each LAR value Used only on the VCD V for storing off screen images Special routines in the Subroutine Package support its use Memory is not displayable Byte addressable Memory capacity is 8 MB or 16 MB Memory Installed LAR ranges 8 MB 8000 9FFF 16 MB 8000 BFFF System RAM 1K bytes for each LAR value Used for the 34020 program store Memory is not displayable Byte addressable 1 MB ...

Page 104: ...en set up The hardware byte swapping function can be enabled for A32 space You must first set the A32SWAPEN bit in the CSR Note that the A32 space usage increases to 256 MB when A32 byte swapping is enabled The reason for this is revealed in Section 5 3 5 which contains detailed information on the byte swapping The XARADR DBRADR Address Match Registers are programmed through a single register in t...

Page 105: ...Note that the 4 register CSR block can only respond in A16 space To enable A24 response turn off MEMON set the DBRADR to match the upper 14 bits of the A24 address then set both MEMON and A24EN The hardware byte swapping function can be enabled for A16 A24 space You must first set the A1624SWAPEN bit in the CSR Note that the A16 A24 space usage increases to 4 KB when byte swapping is enabled The r...

Page 106: ... 5 2 5 VECADR Interrupt Vector Address Register The interrupt vector address which the board supplies to the VMEbus during an interrupt acknowledge cycle is also programmable Now it should be pointed out that this is not literally the address to which the CPU will vector but a 1 of 256 index which is left shifted 2 bits by the CPU and then used as the vector address Bits 0 7 in this register corre...

Page 107: ...hen non BLT reads will be faster if sequential possibly slower if random If HINC is always on then non BLT writes will be unaffected if HPFW HSTCTLH is clear default possibly slower if it is set Note HINC must not be set on pre Rev 4 VCT VCU or Pre Rev 2 VCDs 5 2 8 Device Register Access The board devices and memory are accessed through the 1 KB line buffer in the A16 A24 space The 34020 registers...

Page 108: ... 8 bit Red Green with Sync and Blue analog video outputs The BT459 and BT468 include on chip 2 bit cursor 400 3 F BT482 VCD V 5 9 The BT482 color map is used instead of the BT459 in cases where a digital output is supplied and medium resolution 640 x 480 analog is also needed Includes 2 bit cursor 400 20 2F 8242PC 5 14 The 8242PC is an Intel 8042 programmed with the Phoenix MultiKey keyboard BIOS ...

Page 109: ...I supports intelligent 8 bit parallel I O devices 400 1C2 ZOOM 5 5 16 bit register access only The zoom control register is used to set the dot clock frequency and in some configurations front and back porch horizontal sync adjust and sync polarity 800 BFF 0 3FC HSP 5 15 32 bit access only High Speed Port optional allows the 34020 to directly copy data into memory via a 32 bit port connected to VM...

Page 110: ...hics memory color register block fill and writemask functions are supported The writemask operation is write enable per bit enable function which allows direct writes instead of read modify writes The 34020 derives its timing from a clock which is independent of the video clock In fact the standard clock is 40 MHz while the typical video clock is 110 MHz The 34020 has internal synchronizers which ...

Page 111: ...tches must be set to use it Since the chip select for the FPU always responds you must run an FPU instruction An uncompleted operation will reveal its absence The Coprocessor ID for the 34082 is 0 The 34082 conforms to the IEEE floating point standard P754 R10 0 for high level math functions In addition it offers transcendental functions trigonometrics hyperbolics exponentials logarithmics etc and...

Page 112: ...ata bus MAD bus The 74BCT16652s hold the writemask data essentially acting as the VRAM writemask holding register and gate it onto the MAD bus at the beginning of every VRAM cycle Writing the 74BCT16652 writemask register is a bit of a trick When a program writes into the 34020 writemask register the 34020 executes a special cycle to update the VRAM writemask holding register A PLD detects this cy...

Page 113: ...2 space When used the hardware byte swapper quadruples these memory sizes The 34020 addresses long 32 bit words so masking must be done to limit the operation to a single byte or less if desired The masking may be done by setting the proper bit field size in the 34020 or if the operation is to be performed on the display memory by using the writemask register see Section 5 3 3 5 3 5 Byte Ordering ...

Page 114: ... are not inadvertently swapped Long word operands are stored by the VMEbus with the high order word bytes 0 and 1 preceding the low order word bytes 2 and 3 in memory the reverse of the 34020 The TI cross assembler compiler tools will supply the object code in big or little endian The Peritek downloader and software are written for little endian The VMEbus must use an odd address for byte access o...

Page 115: ...ple mappings to the same physical memory This permits swap modes to be changed on the fly without changing control bits The only penalty is memory space requirements on the VMEbus which jumps by 4 times A16 A24 Swap Modes If A1624SWAPEN is set then the 1 KB DBR expands to 4 contiguous 1 KB DBRs and the lower 2 bits of the DBRADR are don t care The 4 KB block must start on a 4 KB boundary Each DBR ...

Page 116: ...e that they are in CPU memory If you don t do this you may get a page fault which would force a retry of the instruction Since the color map has already been read when the page fault occurs you will end up reading the color palette too many times 5 3 7 34020 Memory and Device Addresses This section covers the 34020 address equivalents for the board on board memory and devices The 34020 address is ...

Page 117: ...4020 address spaces have the same 1 MB of memory However for larger system memory configurations this is not true Thinking of a memory block starting from the bottom of the address space the top of that memory block will map to the top of the address space Table 5 9 LAR 34020 Starting Address Table TMS34020 address LAR High Low 34020 Registers 0 C000 0000 Device Registers 400 C080 0000 High Speed ...

Page 118: ... out what VMEbus addresses the board appears at All addresses are calculated by adding a host CPU s A16 or A32 VMEbus base address an offset In this example A16 VMEbus is the base address which the host CPU has mapped to the VMEbus A16 space see Section 6 2 and is of the form A16 VMEbus abcd 0000 In many systems A16 space is mapped to high memory so let s assume that A16 VMEbus FFFF0000 A32 VMEbus...

Page 119: ...0 DBRADR 20 The board appears at the 32 bit address A16 VMEbus D offset so we would get FFFF8000 Calculating the A32 Base Address The XARADR is a register containing the high 6 bits of the A32 extended address see Section 5 2 3 The actual VMEbus offset value X offset XAR 400000h Let us assume X offset 8000 0000 XARADR 20 The board appears at the 32 bit address A32 VMEbus X offset so we would get 1...

Page 120: ...FFE0 Flash EEPROM 100 0000 abcd 0000 abcd 03FF 4000 7FFF C800 0000 CFFF FFE0 VCT V 1K x 1K x 32 Display Plane Four Pages 100 0000 abcd 0000 abcd 03FF 4000 4FFF 5FFF C800 0000 C9FF FFE0 CBFF FFE0 1K x 1K x 8 Primary Display Plane Four Pages VCD V Eight Pages VCU V 180 0000 abcd 0000 abcd 03FF 6000 6FFF 7FFF CC00 0000 CDFF FFE0 CFFF FFE0 1K x 1K x 4 Overlay Display Plane Four Pages VCD V Eight Pages...

Page 121: ...ter primary cursor RAM C080 0 3 Data Buffer primary C080 20 7 Primary Palette Mask Register C080 40 B Read Address Register primary cursor RAM C080 60 F Write Address Register overlay cursor color C080 80 3 Data Buffer overlay C080 A0 7 Command Register A C080 C0 B Read Address Register overlay cursor color C080 E0 F 8242PC Keyboard Controller Data Buffer C080 100 23 Control Status Register C080 1...

Page 122: ...r Lower Registers C080 wE0 m 1F Mode Registers 1B and 2B C080 x00 m 23 Status Clock Register B C080 x20 m 27 Command Register B C080 x40 m 2B Receive Transmit B Buffers C080 x60 m 2F Reserved C080 x80 m 33 Not used C080 xA0 m 37 Stop Counter C080 xC0 m 3B Start Counter C080 xE0 m 3F For DUART A m 100 w 8 x 9 For DUART B m 140 w A x B 5380 SCSI VCT V and VCU V option SCSI Data In Out C080 C00 183 I...

Page 123: ... Table 5 13 Graphics Board Option Description Option Type Description X6 Analog only 640 x 480 X Compatible X10 Analog only 1024 x 768 X Compatible X12 Analog only 1280 x 1024 X Compatible A6 A10 A12 Analog only as above but CnP compatible D8 Digital only VCD V only 640 x 480 8 bit pixel X6 D8 X10 D8 X12 D8 Analog and Digital as above VCD V only X Compatible A6 D8 A10 D8 A12 D8 Analog and Digital ...

Page 124: ...VGA 98 Mhz Crystal D90VX108 80 VCD X10 1024x768 80 Mhz Crystal D90VX128 110 VCD X10 1280x1024 110 Mhz Crystal TV1709 ics VCT NTSC 1562 PLL TV1x19 ics VCT 1024x1024 1562 PLL TVVGA9 ics VCT VGA 1562 PLL TVX109 ics VCT 1024x768 1562 PLL TVX129 ics VCT 1280x1024 1562 PLL TVsn39 ics VCT SunMode3 1562 PLL UV1x18 ics VCU 1024x1024 1562 PLL UVVGA8 ics VCU VGA 1562 PLL UVX108 ics VCU 1024x768 1562 PLL UVX1...

Page 125: ...0 intpend external display window violation flags 0x24 0x0000 convsp Source pitch conversion for XY to linear 0x2a 0x0000 convdp Destination pitch conversion for XY to linear 0x2e 0x0000 pmaskl Bit plane write disable low 16 bits 0x2c 0x0000 pmaskh Bit plane write disable high 16 bits 0x32 0x0000 convmp Mask pitch conversion for XY to linear 0x16 0x01ff dpyint display line count interrupt register...

Page 126: ... 0x20b 0x00 P16 23 blinkmask register 0x20c 0x00 P24 27 blinkmask register TI34020 0x12 0xd007 dpyctl turn on display after initializing everything Information region INFO CMMType 0x0002 Bt463 CURSType 0x0002 BT431 Overlay 1 VideoWide 2048 width of video memory VideoHigh 1024 height of video memory DisplayWide 1280 width of displayed part of video memory DisplayHigh 1024 height of displayed part o...

Page 127: ...s Some monitors display no picture when the horizontal frequency is out of its bandwidth The same symptoms can be caused by no sync at all so make sure that the cables are connected correctly and that the monitor is configured correctly The graphics board default output is sync on green The horizontal frequency is controlled by HTOTAL The number of diagonal lines is an indication of how close you ...

Page 128: ...ertical frequency Indications that the vertical frequency needs to be changed are a picture which rolls up or down Sometimes the appearance is of multiple pictures one on top of another with multiple horizontal lines An excessively slow vertical frequency will cause the image to flicker Some monitors display no picture when the vertical frequency is out of it s bandwidth The same symptoms can be c...

Page 129: ...LNK larger VEBLNK must be larger than VESYNC VSBLNK must be less than VTOTAL To change the height of the image There are 2 ways to change the width vertical size of the image 1 Display more lines The aspect ratio remains the same 2 Change the vertical frequency Increasing the vertical frequency will result in a shorter image decreasing it will result in a taller image Declaration Peritek remains d...

Page 130: ...__________________ Horizontal Sync Width____________________ Horizontal Back Porch____________________ Vertical Timing Information Note Vertical timings may be given in line units or time units Vertical Lines Displayed__________ Interlaced Yes No ________ Vertical Lines Total or Frequency Field Rate _________ Vertical Lines Total or Frequency Frame Rate ________ same as Field Rate unless interlace...

Page 131: ...al Zoom The primary and overlay graphics screens are zoomed together vertically through bits 0 4 of 34020 register DINCL This is a binary zoom factors 1 2 4 8 16 32 Due to a bug in the 34020 vertical zoom does not work properly in interlaced displays Horizontal Zoom The zoom control register is used not only for horizontal zoom but also to program the ICS1562 programmable phase locked loop PLL pix...

Page 132: ... V Table 5 17 Zoom Control Register for VCT V and VCU V Bit Mnemonic Function 31 9 spare not used not defined reads 0 or 1 8 ICUR VCT V only Enable interlaced cursors clear non interlaced set interlaced 7 EMODE Enable genlock Contact Peritek before using clear internal sync set external sync genlock 6 VCMODE Vertical Composite Mode for J3 pin 14 clear vertical sync set composite sync 5 VCSYNCPOL V...

Page 133: ...set external sync genlock 10 SM Sync Mode clear composite sync set block sync no serrations during VSYNC 9 SU Setup 7 5 IRE step between blank and sync clear no step set step enabled normal 8 IN Interlaced mode clear non interlaced set interlaced 7 JP Reads jumper 6 V CMODE Vertical Composite Mode for J3 pin 14 clear vertical sync set composite sync 5 V CSYNCPOL Sync Polarity for signal on J3 pins...

Page 134: ...t used not defined reads 0 or 1 7 JP Reads jumper 6 V CMODE Vertical Composite Mode for J3 pin 14 clear vertical sync set composite sync 5 V CSYNCPOL Sync Polarity for J3 pin 14 clear output is active low set output is active high 4 HSYNCPOL Horizontal Sync Polarity for J3 pin 13 clear sync is active low set sync is active high 3 DAMODE Digital Analog mode clear digital display set analog display ...

Page 135: ...image width i e zoom or to prescale the master oscillator for a required pixel clock An example of the prescale function would be to divide an NTSC master oscillator 49 34 MHz to 12 33 MHz which is what the NTSC color pixel clock is Under some circumstances the analog and digital ports can be used simultaneously Sharp LQ10DH11 and LQ10DH15 panels use standard VGA timing but oftentimes the timing r...

Page 136: ...2 24 576 27 00 1 fixed Digital port 24 576 27 00 1 fixed D4 D8 Digital 24 27 32 max 1 MF Digital BT482 67 2 80 64 3 4 5 6 7 8 16 1 not valid Table 5 21 VCD V Analog Only Zoom Register BT459 Bit Mnemonic Function 31 8 spare not used not defined reads 0 or 1 7 RJP12 Reads the state of jumper JP12 6 VCMODE Vertical Composite Mode for J3 pin 14 clear vertical sync set composite sync 5 VCSYNCPOL Vertic...

Page 137: ...2 is open VCD V is initialized for flat panel 640 x 480 output 6 1 xxx Reads 0 0 Mode Display mode enable Mode 0 then Analog output is selected Mode 1 selects digital output Table 5 23 VGA style Zoom Control Register Bit Mnemonic Function 7 VCMODE Vertical Composite Mode for J3 pin 14 clear vertical sync set composite sync 6 VCSYNCPOL Vertical Composite Sync Polarity for J3 pin 14 clear sync is ac...

Page 138: ...d It is not necessary to provide more than 1 bit for FB and BP because VCLK is in increments of 2 pixel clocks Additional changes can be made directly to the HSBLNK and HESYNC 2 SM Sync mode Affects Sync on VGA connector SM 0 selects Composite Sync Horizontal serrations are present during Vertical Sync SM 1 selects Block Sync Horizontal serrations are absent during Vertical Sync 1 INTER Set to pro...

Page 139: ... the display memory into analog voltages which drive the display monitor There are two ways to make this conversion true color and pseudo color The BT463 latches four pixels of primary screen data plus four bits for overlay The data is synchronized internally through another register and then fed pixel by pixel through the chip Two additional mode control bits window type are also latched at each ...

Page 140: ...ese bits work see the BT463 data sheet The BT463 has twenty internal registers plus the window type table and the color palette RAM They are accessed via a four single byte register data buffer group programmed through the device buffer VCTLAR 400 Each byte is located on a long word boundary The first two bytes make a 12 bit address register Byte 3 is the data buffer for register and window type t...

Page 141: ...sters VMEbus Offset Mnemonic Function 3 ADRLO Low 8 bits of the address register Autoincrements after access to REGDBR or PALET See description on previous page 7 ADRHI High 4 bits of the address register Autoincrements after access to REGDBR or PALET See description on previous page B REGDBR Data Buffer for control registers window type table and cursor colors 2 x 3 R G B R G B locations cycled b...

Page 142: ... diagram show what color value you get depending on the various inputs to the color map Table 5 26 BT463 Color Map Input Conversion Window Primary Type Cursor Overlay Input Inputs Input Input R G B Color Value 0 3 0 n a b c Color map section controlled by window type RAM see BT463 data sheet 0 3 0 0 0 0 0 R G B palettes 0 3 0 0 a b c R G B palettes 0 3 0 0 FF FF FF R G B palettes 0 3 0 1 xx xx xx ...

Page 143: ...additional table entries for the 4 bit graphics overlay planes and 3 for the 2 bit cursor Each table entry is a 24 bit value 8 bits each for R G and B It occupies four register locations in the VCU Device Buffer The registers use only the low 8 bits of each word The BT468 is controlled through an 8 bit I O port It functions exactly the same way as the BT463 described in the previous section The sa...

Page 144: ... and cursor and overlay color maps F PRIPAL Primary plane color map palette 256 x 3 R G B locations R G B locations cycled by mod 3 counter The following table and block diagram show what color value you get depending on the various inputs to the color map inputs are called Cursor Overlay Graphics Overlay and Primary Screen Table 5 28 BT468 Color Map Input Conversion Cursor Overlay Primary Input I...

Page 145: ...el 6 40 43 Overlay Pixel 5 32 35 Overlay Pixel 4 24 27 Overlay Pixel 3 16 19 Overlay Pixel 2 8 11 Overlay Pixel 1 0 3 Overlay Pixel 0 primary 56 63 Primary Pixel 7 48 55 Primary Pixel 6 40 47 Primary Pixel 5 32 39 Primary Pixel 4 Video Outputs 24 31 Primary Pixel 3 16 23 Primary Pixel 2 B Blue 8 15 Primary Pixel 1 G Green 0 7 Primary Pixel 0 R Red BT468 latches 8 pixels at a time ...

Page 146: ...r Each table entry is a 24 bit value 8 bits each for R G and B It occupies four register locations in the VCD Device Buffer The registers use only the low 8 bits of each word The BT459 is controlled through an 8 bit I O port It functions exactly the same way as the BT463 described in the Section 5 6 The BT459 has a two bit graphics cursor It contains a 64 x 64 x 2 bit map position match registers ...

Page 147: ... registers are documented in the BT459 data sheet Table 5 29 BT459 registers VMEbus Offset Mnemonic Function 3 CMAPARL Low byte of BT459 address register Two bit low order internal counter addresses individual R G and B locations when color maps are accessed See description above 7 CMAPARH High byte of BT459 address register See description above B CSRMAP BT459 control status buffer cursor positio...

Page 148: ...0 primary palette entry 0 0 0 FF primary palette entry FF 0 1 xx overlay palette entry 1 0 F xx overlay palette entry F 1 xx xx cursor palette entry 1 2 xx xx cursor palette entry 2 3 xx xx cursor palette entry 3 Figure 5 4 BT459 Display Memory Bit Assignments display data bits BT459 RAMDAC overlay 24 27 Overlay Pixel 3 16 19 Overlay Pixel 2 8 11 Overlay Pixel 1 0 3 Overlay Pixel 0 primary Video O...

Page 149: ...aphics overlay planes and 3 for the 2 bit cursor Each table entry is a 24 bit value 8 bits each for R G and B The BT482 has a two bit graphics cursor It contains a 32 x 32 x 2 bit map position match registers and counters triggered by the dot clock and referenced to horizontal and vertical sync The match registers compare a programmed value corresponding to an X Y position on the screen to the cou...

Page 150: ...The low two bits count mod 3 and thus cycle through the R G and B parts of each of the 256 LUT entries Since the address register is autoincrementing it needs to be initialized only with the base address of the color map to read or write the entire map The red and green values are held in a temporary register inside the BT482 until the blue value is entered at which time all three are loaded The t...

Page 151: ...t to drive the color palette F PRRADR Primary RGB triplet 0 255 read address register and cursor bitmap read address register 13 OLWADR Overlay RGB triplet 0 255 write address register and cursor palette write address register 17 OLYPAL Overlay color map palette 256 x 3 R G B locations R G B locations cycled by mod 3 counter Cursor palette data buffer 1B Command Register A 1F OLRADR Overlay RGB tr...

Page 152: ...s are called Cursor Overlay Graphics Overlay and Primary Screen Table 5 32 BT482 Color Map Input Conversion Cursor Overlay Primary Input Input Input Color Value 0 0 00 primary palette entry 0 0 0 FF primary palette entry FF 0 1 xx overlay palette entry 1 0 F xx overlay palette entry F 1 xx xx cursor palette entry 1 2 xx xx cursor palette entry 2 3 xx xx cursor palette entry 3 ...

Page 153: ...lly intended for DRAMs are also connected to the MACH130 When UCASO is high the high order lines in this case LAR bits 0 5 are active and are latched into a register buried in the 130 When UCASO goes low address lines 1 6 are selected and latched Thus a 12 bit address is formed inside the 130 Three additional address lines are latched inside the VCDV4 MACH130 and are multiplexed onto the cursor an...

Page 154: ...imes We have found that a very effective way to quickly load the table is to use the 34020 graphics FILL instruction The CDP and PX Windows software available from Peritek both take advantage of this trick In the tables shown on the next page the term invalid indicates that the entry is not defined In some cases an invalid location actually duplicates valid entries in other cases there is no dupli...

Page 155: ...Cursor 0 1 Blanking 7 Overlay 8 Cursor 0 Cursor 1 Cursor 0 1 Blanking 8 Overlay 9 Cursor 0 Cursor 1 Cursor 0 1 Blanking 9 Overlay 10 Cursor 0 Cursor 1 Cursor 0 1 Blanking 10 Overlay 11 Cursor 0 Cursor 1 Cursor 0 1 Blanking 11 Overlay 12 Cursor 0 Cursor 1 Cursor 0 1 Blanking 12 Overlay 13 Cursor 0 Cursor 1 Cursor 0 1 Blanking 13 Overlay 14 Cursor 0 Cursor 1 Cursor 0 1 Blanking 14 Overlay 15 Cursor ...

Page 156: ...invalid Overlay 2 invalid invalid Blanking 2 invalid Overlay 3 invalid invalid Blanking 3 invalid Overlay 4 invalid invalid Blanking 4 invalid Overlay 5 invalid invalid Blanking 5 invalid Overlay 6 invalid invalid Blanking 6 invalid Overlay 7 invalid invalid Blanking 7 invalid Overlay 8 invalid invalid Blanking 8 invalid Overlay 9 invalid invalid Blanking 9 invalid Overlay 10 invalid invalid Blank...

Page 157: ...zed to the rest of the video timing with HSYNC and VSYNC The cursor coordinates are a function of the color map load clock which makes a transition every 4 or 8 pixel times and horizontal and vertical syncs which clear the cursor s X and Y position counters It then counts load pulses to position itself along the horizontal axis and counts horizontal sync pulses to determine vertical position Since...

Page 158: ...time The cursor colors on the BT463 are not used because to do so requires special gating to force the high four bits in the BT463 to be E or F this method was used however on VCT V revisons 0 2 Instead the cursors use the high two bits of the 4 bit window type table inputs see BT463 data sheet This requires some unusual programming of the window type table inputs and means you effectively only ge...

Page 159: ... BT431 cursors 0 1 Control register data buffer write only 83 BT431 cursor 0 Low byte address register read write 87 BT431 cursor 0 High byte address register read write 8B BT431 cursor 0 Bitmap RAM data buffer read write 8F BT431 cursor 0 Control register data buffer read write C3 BT431 cursor 1 Low byte address register read write C7 BT431 cursor 1 High byte address register read write CB BT431 ...

Page 160: ...nd green LEDs The RS 232 interface is provided by a MAX238 CMOS quad EIA RS 232 receiver transmitter This chip provides four complete channels as well as built in slew rate control The chip also includes 10 volt charge pump generators to supply the necessary RS 232 voltage swings and clamping diodes for protection against static charges on both inputs and outputs The DUART contains 16 register loc...

Page 161: ...atus Register A CC Write CSRA Clock Select Register A 38 4 Kbaud m B Read Reserved Read inhibited by hardware 15 Write CRA Command Register A m F Recv Data Read RHRA Receive Holding Register A Xmit Data Write THRA Transmit Holding Register A m 13 Read IPCR Input Port Change Register 70 Write ACR Auxiliary Control Register m 17 Read ISR Interrupt Status Register 0 Write IMR Interrupt Mask Register ...

Page 162: ...oned in Chapter 2 the SCSI and the High Speed Port HSP share some signals on the P2 connector thus precluding simultaneous installation of both options on a given board The 5380 contains several registers which facilitate control of the SCSI bus and as input buffers which allow the direct readback of all SCSI signals The 5380 provides the actual electrical interface but doesn t have any intelligen...

Page 163: ...0 into DMA mode when transferring data some of the bit toggling will be assumed by the 5380 itself Set bit 1 in the MDR poll bit 6 DRQ in the Bus Status Register and when active read or write data as required to the Pseudo DMA Data Buffer LAR 800 offset 0 or 34020 address C100 0000 DMA transfers are initiated by writing anything to the correct DMA start register While the SCSI chip is intended to ...

Page 164: ...K etc Keep sending until phase changes The ACB 4000A knows when to stop Now the controller will want to transfer data or send termination status Check the CSBS register to find out what is needed If data is to be transferred call the 34020 routine to transfer data Using pseudo DMA mode will speed data transfers If a message is to be sent read it in The Termination consists of a status byte and a m...

Page 165: ...Bidirectional clock and data lines communicate with an intelligent keyboard scan controller Both chips must arbitrate and re send if there is a collision on the clock data lines 5 15 High Speed Data Port HSP The HSP is a 32 bit input port which allows the 34020 to transfer data from User Equipment UE into on board memory The HSP is available only by special order and its use must be qualified by t...

Page 166: ...4020 a line of data is written into graphics board display memory at a position determined by software Frames are transferred at a rate determined by software but can be as often as 30 times per second A write mask register protects any or all bits in the display memory from being written during the transfer process Experiment has shown that data can be transferred at a sustainable rate of one 640...

Page 167: ...s are being transferred to the graphics board No set duty cycle is ascribed to VSL Its period will vary depending on the size of the frames being transferred Only the falling edge is important Bit 1 HSL going low indicates preparation to transfer a line of data The first data of a line should be presented to the HSP data bus in response When frames of data are not being transferred a programmable ...

Page 168: ... interrupt from the 34020 A VMEbus interrupt enable in CSR VINTEN is used to disable interrupts to the VMEbus See note about VINTEN in Table 5 2 See Section 5 2 5 for information about the VMEbus Interrupt Vector Address The following table provides information regarding the interrupts For the 34020 side interrupts all device interrupts are OR d into X2P interrupt see 34020 internal registers INTE...

Page 169: ...kage can now be supplied in EEPROM As an added bonus a control bit buried in the 34020 address decoder MACH130 allows the EPROM memory to respond to the highest 1 MB section of 34020 memory blocking out the DRAM This bit is initialized on SYSRESET from the VMEbus The graphics board can autoboot on power up or reset when enabling jumpers are installed see Section 2 4 5 Although the program boots fr...

Page 170: ...nes OP0 OP1 and IP2 on DUART0 and also uses the chip select of DUART1 The pin functions are as follows DUART EEPROM Signal Name Mnemonic Description OP0 ECLK Serial EEPROM clock OP1 EDIN Serial EEPROM data input IP2 EDOUT Serial EEPROM data output DUACS1 ECS Serial EEPROM chip select The EEPROM is programmed using a four wire protocol although DUACS1 is actually only used during write and erase to...

Page 171: ...ch should assist you in tracking down installation and functional problems with your board There are several sections to this chapter 6 2 Selecting an Address Range for your Board 6 3 Memory Map Address Example 6 4 Does this board talk at all 6 5 General procedures 6 6 Maintenance Warranty and Service ...

Page 172: ...ally the CPU board s boot PROM will set up the A16 A24 and A32 address space assignments in its local bus controller If a controller chip isn t used then the map will be hardwired into the CPU board design For A16 space the high 16 bits of the CPU chip s address space is determined by the memory map and thus the bus controller What this means is that although the CSR block in the graphics board it...

Page 173: ...0000 FBFF7FFF VME Short I O A16 D32 GMS V36 and V46 80000000 EFFFFFFF VSB VME A32 D32 F1000000 F100FFFF VME Short I O A16 D32 Motorola MVME147S DRAMsize 01000000 VME Standard A24 D32 01000000 EFFFFFFF VME Extended A32 D32 FFFF0000 FFFFFFFF VME Short I O A16 D16 Motorola MVME162 167 187 188 197 F0000000 FEFFFFFF VME A24 A32 D32 FFFF0000 FFFFFFFF VME Short I O A16 D32 Themis SPARC CPU s 04000000 FCF...

Page 174: ...ammable register in the CSR block These bits correspond to address lines 10 15 for A16 and lines 10 23 for A24 On the MVME CPU s Peritek uses is 8000 giving a CPU address of FFFF8000 for A16 The graphics board also can respond to a 64 MB window in A32 space giving access to the entire on board memory In this case a programmable register in the CSR block allows you program the address of that windo...

Page 175: ...ay have an address conflict This section tells you how to check to be sure there are no other devices which respond to its addresses The board in this example follows MVME167 VMEbus address assignments with respect to A16 A24 and A32 areas If you are not using a 167 see Chapter for other CPU board addresses The graphics board responds to A16 and A32 bus masters but not A24 unless specially enabled...

Page 176: ...cs board CSR is set Since we can t use the bottom of A16 space in a 167 or 187 it is also necessary to load the Line Buffer Address Register LBAR at FFFFC008 This is because the register comes up zero enter MM FFFFC000 W CR receive FFFFC000 4000 enter 60 CR sets MEMON and CRTCON receive WARNING NO MATCH get an error because the 4000 bit is lways set enter CR end the dialog enter MM FFFFC008 W CR r...

Page 177: ...o see if you are within specification Consult your computer s technical manual for information on how to correctly determine this A typical VCT V VCU V or VCD V will draw about 2 amps at 5 volts When attempting to verify that the power supply is working properly it is not unusual to unplug everything and measure the supply without a load While this practice is acceptable for linear supplies switch...

Page 178: ... System crashes or you get a Trap message Software not installed correctly Check installation procedures See Software Release Notes No image on Monitor COAX cables not connected properly or monitor is not on Check BNC cables replace if necessary Be sure to initialize board with correct initialization table Image is smeared or doing flip flops Sync signals missing or monitor sync failure Make sure ...

Page 179: ...ctory Peritek s obligation under this warranty is limited to replacing or repairing at its option any board which is returned to the factory within this warranty period and is found by Peritek to be defective in proper usage This warranty does not apply to modules which have been subjected to mechanical abuse electrical abuse overheating or other improper usage This warranty is made in lieu of all...

Page 180: ...fee will be charged for normal repairs and must be covered by a valid purchase order If extensive repairs are required Peritek will request authorization for an estimated time and materials charge If replacement is required additional authorization will be requested All repair work will be done at the Peritek factory in Oakland California unless otherwise designated by Peritek ...

Page 181: ...y Bit Assignments 5 46 BT463 registers 5 45 BT468 5 47 BT468 Color Map Input Conversion 5 48 BT468 Display Memory Bit Assignments 5 49 BT468 registers 5 48 BT482 5 53 BT482 Color Map Input Conversion 5 56 BT482 cursor controller 5 61 BT482 Display Memory Bit Assignments 5 55 BT482 output level VCD V T only 2 18 BT482 registers 5 55 bus architecture 4 3 byte sense 5 17 byte swapper 5 19 Byte Word L...

Page 182: ... Interrupt Grant Level 2 14 Interrupt Priority Jumpers 2 14 interrupt settings 2 3 interrupt vector 4 7 4 12 interrupt vector address 2 3 Interrupt Vector Address Register 5 11 Interrupt Vector Register 5 10 interrupts 4 7 5 4 5 72 J4 Type 1 Digital Video Connector to Sharp TFT LCD Panels 2 32 J4 Type 2 Digital Video Connector to Sharp EL Panels 2 33 Jumper Locations for the VCD V 2 11 Jumper Loca...

Page 183: ...on Horizontal Zoom Register 5 38 VCD V X12 D8 Analog Digital Zoom Register 5 41 VCnVDMP 3 15 VCnVGO 3 14 VCnVHLT 3 14 VCnVINT 3 12 VCnVLD 3 14 VCnVOFF 3 15 VCnVTST 3 12 VCnVWT 3 14 VCT and VCU DRAM and VRAM Size 2 16 VCT and VCU Unique PLD Device Summary 4 14 VCT VCU VCD Common PLD Device Summary 4 13 VCT V and VCU V PTERM Serial Jumpers JP22 2 20 VCT V Block Diagram 4 17 VCU V and VCT V SCSI Conn...

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