Peritek VCD-V, User Manual

Page: 105 / 183

Peritek
Programming On-board Devices and Memories 5-9
5.2.4 A16/A24 Address Map and DBRADR Address Match Register
The graphics board's A16/A24 (I/O/standard) addressing function allows
the board to respond for the line buffer (DBR) in A16 (or A24) space. In
order for the A16/A24 space on the board to respond the DBRADR
register must be set up with a valid address, the 34020 must be initialized,
and CSR bit
MEMON must be set.
The only reason for selecting A24 space is if your CPU doesn't support
D32 (long word) accesses in A16 space. You will pay a small (10-20%)
performance for running D16 only. Peritek software must be explicity told
to use A24 space, because the A24EN bit in the CSR must be set. Note
that the 4 register CSR block can only respond in A16 space. To enable
A24 response, turn off MEMON, set the DBRADR to match the upper 14
bits of the A24 address, then set both MEMON and A24EN. The hardware
byte-swapping function can be enabled for A16/A24 space. You must first
set the
A1624SWAPEN bit in the CSR. Note that the A16/A24 space
usage increases to 4 KB when byte swapping is enabled. The reason for
this is revealed in Section 5.3.5, which contains detailed information on
the byte swapping.
The XARDBR/DBRADR Address Match Registers are programmed
through a single register in the CSR block. Which register is accessed
through the register slot is controlled by the
XARSEL bit in the CSR..
When XARSEL = 0, the DBRADR address match register is selected.
Remember that MEMON in CSR also has to be set.
The size of the DBRADR register varies is a function of A24 and byte-
swapping (see table).