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ML7065-033 User’s Manual

Chapter 8 Electrical Characteristics

65

When SCLK is a positive clock

SCEN

SCLK

SDO

SDIN

MSB IN

BITS6-1

LSB IN

T

CEEN0

F

SCLK1

or F

SCLK2

T

WCKH

T

DISU

T

WCKL

MSB OUT

BITS6-1

LSB OUT

(*24)

T

CEH

T

CEDIS

T

DOH

T

CKOD

T

DIH

T

DOH

T

CESU

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Summary of Contents for ML7065-033

Page 1: ...ML7065 033 User s Manual Issue Date September 15 2005 FEUL7065_033 01...

Page 2: ...operty right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third part...

Page 3: ...EEE802 15 4 The following related manual is available Read it as required ML7065 Design Guide Contains the hardware information that should be referenced when designing circuits ZigBee is a registered...

Page 4: ...10 6 Nano n 10 9 Unit Second s lowercase Second H level The signal level on the high voltage side It indicates the voltage level of VIH and VOH defined in electrical characteristics Terminology L leve...

Page 5: ...ist of Commands 17 7 2 Config Commands 18 7 2 1 RST_CTL0 18 7 2 2 RST_CTL1 18 7 2 3 CLK_CTL0 19 7 2 4 CLK_CTL1 19 7 3 MAC Commands 20 7 3 1 MCPS DATA request 22 7 3 2 MCPS DATA confirm 22 7 3 3 MCPS D...

Page 6: ...firm 35 7 3 36 MLME PROTOCOL ERROR indication 35 7 3 37 PANDescriptor Details 36 7 3 38 Status Details 37 7 4 Notes on Operation and Restrictions 58 8 Electrical Characteristics 59 8 1 Absolute Maximu...

Page 7: ...Covers 16 channel 2 4 GHz band radio A maximum data transfer speed of 250 kbps CSMA CA channel access IEEE802 15 4 2 4 GHz PHY mounted IEEE802 15 4 MAC mounted O QPSK modulation demodulation function...

Page 8: ...control circuit PHY Block IEEE802 15 4 compliant PHY circuit AES Block AES function provided NIST FIPS 197 with a key size of 128 bits available MAC Block IEEE802 15 4 compliant MAC circuit Synchronou...

Page 9: ...GND_RF 36 35 34 33 32 31 30 29 28 27 26 25 MODE2 37 24 N C MODE3 38 23 N C CLKOUT 39 22 VDD_MIX SDO 40 21 GND_RF SDIN 41 20 VDD_RF SINT 42 19 ANT_1 N C 43 18 GND_RF GND 44 17 ANT_2 SCLK 45 16 N C VDDC...

Page 10: ...or ISU Input pin with Schmitt trigger pull up resistor IOS Input pin for oscillation circuit ORF RF control output pin OA Analog output pin O Regular output pin OOS Output pin for oscillation circuit...

Page 11: ...sizer and LocalGen Typ 2 5 V 12 Power supply pin for the BPF Limiter RSSI and DAC 13 VDD_IF Typ 2 5 V 31 VDD_D_RF Power supply pin for the Synthesizer Charge Pump Typ 2 5 V 5 36 48 VDDIO Power supply...

Page 12: ...l clock 64 MHz max input pin Used for testing purposes only 33 MODE1 I IO Mode setting pin 1 37 MODE2 I I Mode setting pin 2 38 MODE3 I I Mode setting pin 3 32 N C 23 N C 24 N C 16 N C 15 N C 11 N C N...

Page 13: ...pin Software reset can be executed from the host by connecting the SRESETN pin to the GPIO pin of the host This operation is enabled only when the RESETN pin is deasserted In a sleep state the SRESET...

Page 14: ...ed As for the internal register data values prior to the sleep state are retained In a sleep state only the device is returned to the normal state without being reset by asserting the SRESETN pin or t...

Page 15: ...put output CLKOUT pin No OSC clock is output after reset release 2 H L L SCI MSB data input output CLKOUT pin No OSC clock is output after reset release 3 L H L SCI LSB data input output CLKOUT pin Th...

Page 16: ...1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 5 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 0 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 7 1 1 1...

Page 17: ...as Q data Also because of OQPSK modulation the Q data delays from I data by 1 2 chip as shown below 5 3 Pulse Waveforms As shown below the waveforms of the I and Q data are created in the front stage...

Page 18: ...rt of frame Delimiter Frame length 7 bits Reserved 1 bit PSDU 4 bytes 1 byte 1 byte 127 bytes max 1 Preamble 0000 0000 0000 0000 0000 0000 0000 0000 symbol 0 0 0 0 2 Start of frame delimiter Bit 0 Bit...

Page 19: ...065 033 is applied to a slave mode only and the input clock from the host is applied to the rising edge only Two types of transmit receive data formats are available for selection big endian and littl...

Page 20: ...a write enable Config 2 Data read enable Data read request 1 Data write request Data write enable MAC RAM PHY 0 Data read enable Data read request 2nd transfer byte Indicates the transfer data length...

Page 21: ...ta Write RAM Little endian 2 byte transfer command 0x0a data 0x07 During transfer do not release 1 scen If it is released the transfer data becomes invalid The interrupt sintn changes only when scen i...

Page 22: ...ta Write Config Little endian 2 byte transfer command 0x0a data 0x07 During transfer do not release 1 scen If it is released the transfer data becomes invalid The interrupt sintn changes only when sce...

Page 23: ...rts the PIB attribute information acquisition results MAC 0x4F MLME_GTS request Makes a request to allocate or deallocate a GTS MAC 0x50 MLME_GTS confirm Reports the GTS allocation deallocation reques...

Page 24: ...oftware reset for the MODEM section 0 Disable 1 Enable W R 1 0 M_P_RSTN_EN Enables software reset for the MAC and PHY sections 0 Disable 1 Enable W R 1 7 2 2 RST_CTL1 Function Controls software reset...

Page 25: ...MHz 1 16 MHz W R 0 14 8 Reserve Reserved RO 0b000_0000 7 0 CLK_DIV_OUT Specifies the divide ratio of the external supply clock Settable range 1000_0000 to 0000_0000 W R 0b0010_0000 CLKGEN uses CLK_DI...

Page 26: ...d bit 1 are used Bit 2 to bit 7 are not used always set to 0 bit 0 This bit is set to 1 when the host system is ready to receive data from MAC This bit is set to 0 when the host system cannot receive...

Page 27: ...the host system bit 2 to bit 7 Unused Length field The length following the Length field Primitive Code Payload is set The unit is bytes Primitive Code field The Primitive Code of the data event that...

Page 28: ...ed 10 msdu Byte data of the MSDU to be transferred 11 msduHandle U8 0x00 0xFF Handle of the MSDU to be transferred 12 TxOptions U8 0b0000_xxxx Logical OR of the transfer option in terms of bit 0x01 ac...

Page 29: ...ination 7 msduLength U8 aMaxMACFrameSize or less Number of bytes in the MSDU to be posted 8 msdu Byte data of the MSDU to be posted 9 mpduLinkQuality U8 0x00 0xFF Value of LinkQuality that has been me...

Page 30: ...ities of the device that attempts association bit0 Alternate PAN coordinator bit1 Device type bit2 Power source bit3 Receiver on when idle 1 bit4 5 Reserved bit6 Security capability bit7 Allocate addr...

Page 31: ...0x08 Value of MacSecurityMode for ACL entry 3 Pad B5 B7 7 3 9 MLME ASSOCIATE response Function Makes a response to the MLME ASSOCIATE indication primitive Command symbol 0x48 Access MAC No Parameter...

Page 32: ...ommand symbol 0x4A Access MAC No Parameter Type Value range Description 1 Status U8 SUCCESS TRANSACTION_OVERFLOW TRANSACTION_EXPIRED NO_ACK CHANNEL_ACCESS_FAILURE UNAVAILABLE_KEY FAILED_SECURITY_CHECK...

Page 33: ...4 2003 When the reception beacon does not contain the pending address to be included in this indication AddrList is omitted 7 3 14 MLME GET request Function Acquires information about a PIB attribute...

Page 34: ...ection 7 3 3 1 2 Bit stream indicating the characteristics of the GTS 2 Status U8 SUCCESS DENIED NO_SHORT_ADDRESS CHANNEL_ACCESS_FAILURE NO_ACK NO_DATA UNAVAILABLE_KEY FAILED_SECURITY_CHECK INVALID_PA...

Page 35: ...tive Command symbol 0x53 Access MAC No Parameter Type Value range Description 1 OrphanAddress 0 2 OrphanAddress 1 3 OrphanAddress 2 4 OrphanAddress 3 5 OrphanAddress 4 6 OrphanAddress 5 7 OrphanAddres...

Page 36: ...nable can be deferred until during the next superframe or FALSE if RX enable is only to be attempted in the current superframe 1 Pad B1 B7 2 RxOnTime 0 3 RxOnTime 1 4 RxOnTime 2 U8 3 0x000000 0xFFFFFF...

Page 37: ...is required set ScanDuration to 0x05 7 3 26 MLME SCAN confirm Function Reports the results of the scan request Command symbol 0x59 Access MAC No Parameter Type Value range Description 1 Status U8 SUC...

Page 38: ...short address 0x03 64 bit extended address 5 DstAddr Depends on the value of DstAddrMode Device address of the communication destination 6 Status U8 SUCCESS TRANSACTION_OVERFLOW TRANSACTION_EXPIRED CH...

Page 39: ...terval The relationship between BeaconOrder BO and BeaconInterval BI is BI aBaseSuperframeDuration 2BO when 0 BO 14 When BO 15 the coordinator does not transmit any beacon and the SuperframeOrder para...

Page 40: ...2 Pad B1 B7 To make a SYNC request the BeaconOrder of the PIBAttribute parameter must be set 7 3 33 MLME SYNC LOSS indication Function Gives notice that synchronization with the coordinator has been l...

Page 41: ...rror occurred other than errors specified in IEEE802 15 4 2003 unique primitive Command symbol 0xFF Access MAC No Parameter Type Value range Description 1 Status U8 0xF5 or 0xF7 Status value 0xF5 When...

Page 42: ...ports Current logical channel 6 SuperframeSpec 0 7 SuperframeSpec 1 U16 Refer to IEEE 802 15 4 2003 Value of the SuperframeSpec parameter 8 GTSPermit U8 TRUE or FALSE Flag that indicates whether a GTS...

Page 43: ...ED 0 x E2 DISABLE_TRX_FAILURE 0 x E3 FAILED_SECURITY_CHECK 0 x E4 FRAME_TOO_LONG 0 x E5 INVALID_GTS 0 x E6 INVALID_HANDLE 0 x E7 INVALID_PARAMETER 0 x E8 NO_ACK 0 x E9 NO_BEACON 0 x EA NO_DATA 0 x EB...

Page 44: ...is for no transmission of a data request command Obtain the data from MLME POLL request issued by the upper level software 1 0x43 macBattLifeExt 0 or 1 This attribute indicates if a battery life exte...

Page 45: ...number will be increased for each frame transmitted Random 0x4D macGTSPermit 0 or 1 This attribute indicates if a PAN coordinator will accept a GTS request ML7065 03 does not support GTS If an MLME G...

Page 46: ...me containing a beacon frame MacSuperframeOrder SO and duration of a super frame SD is related as follows When 0 SO BO 14 SD aBaseSuperframeDuration 2SO Symbol When SO 15 a super frame will not be con...

Page 47: ...ID_PARAMETER status will be returned 0x00 macDefault Security 0 x 72 0x00 0x01 This attribute is used for default security settings Using macDefault SecurityMaterial and macDefault SecuritySuite this...

Page 48: ...t address of the device 0xFFFF ACLPANId 0x0000 0xFFFF PANId of the device Null ACLSecurityMaterialLength 0 21 The number of bytes in ACLSecurityMaterial 21 ACLSecurityMaterial Variable Security materi...

Page 49: ...f the retrieved ACLEntryDescriptor will be set in the ACL entry field The security use field will be then set to TRUE and notified by MCPS DATA INDICATION If there are no hits in the ACL entry the ACL...

Page 50: ...cated by macDefaultSecurityMaterial PIB ID 0x74 will be used to combine the received frames If the source address is a 16 bit address then the received data will be notified to the HOST without combin...

Page 51: ...the suspend function will not be executed The default power saving function will be in effect The suspend status will be in effect when the device is waiting for data from the HOST data from PHY or e...

Page 52: ...ATE REQUEST Set the suspend or sleep function after association is complete 2 Cancel the suspend or sleep function when making an MLME SYNC REQUEST Set the suspend or sleep function after synchronizat...

Page 53: ...es from 0x0000 to 0xFFFD To start PAN in 64 bit address mode set the value to 0xFFFE 5 Turn the receiver to RX_ON PIB ID 0x52 macRxOnWhenIdle 6 Transmit an MLME START REQUEST Example Initiating PAN wi...

Page 54: ...rtAddress SCI header Payload LSB MSB Field name Request Length Primitive Code PIBAttribute PIBAttributeValue Code 0x02 0x04 0x5B 0x53 0x00 0x55 MLME SET CONFIRM SCI header Payload LSB MSB Field name S...

Page 55: ...mitive Code PANId Logical Channel BO SO PAN Coordinator BatteryLife Extension Coord Realignment Security Enable Code 0x02 0x06 0x5D 0xEE 0xEE 0x0B 0x11 0x01 Set BO SO to 0xFF to initiate PAN with no b...

Page 56: ...he PAN coordinator MAC will set macCoordExtendAddress PIB ID 0x4A macCoordShortAddress PIB ID 0x53 and macPANId PIB ID 0x50 of the MAC PIB attribute Example Association with PAN described in Section 7...

Page 57: ...xCF 0x00 0xED 0x48 0xF3 0x55 0x10 4 MLME ASSOCIATE REQUEST SCI header Payload LSB Field name Request Length Primitive Code Logical Chaneel CoordAddr Mode Coord PANId Coord Address Code 0x02 0x09 0x45...

Page 58: ...47 2 MLME SYNC REQUEST SCI header Payload LSB MSB Field name Request Length Primitive Code Logical Channel TrackBeacon Code 0x02 0x07 0x5F 0x0B 0x01 In the IEEE802 15 4 instructions MLME SYNC CONFIRM...

Page 59: ...is shown below 1 Transmit an MLME RESET REQUEST to MAC SetDefaultPIB TRUE 2 Set Logical Channel 0x0B to 0x1A for non discriminating mode reception 3 Set non discriminating mode PIB ID 0x51 Promiscuou...

Page 60: ...FIRM SCI header Payload LSB MSB Field name Status Length Primitive Code status PIBAttribute Code 0x03 0x03 0x5C 0x00 0x51 The following data will be outputted when beacons are received after non discr...

Page 61: ...t Length Primitive Code PIBAttribute PIBAttributeValue Code 0x02 0x03 0x5B 0x76 0x00 MLME SET CONFIRM SCI header Payload LSB MSB Field name Status Length Primitive Code status PIBAttribute Code 0x03 0...

Page 62: ...name Request Length Primitive Code PIBAttribute PIBAttributeValue Code 0x02 0x03 0x5B 0x76 0x02 MLME SET CONFIRM SCI header Payload LSB MSB Field name Status Length Primitive Code status PIBAttribute...

Page 63: ...e when PAN started Example Settings for resuming PAN 1 MLME RESET REQUEST SCI header Payload LSB MSB Field name Request Length Primitive Code SetDefaultPIB Code 0x02 0x02 0x54 0x00 MLME RESET CONFIRM...

Page 64: ...ization with PAN with beacons described in Section 7 7 3 Example Pan re entry settings 1 MLME RESET REQUEST SCI header Payload LSB MSB Field name Request Length Primitive Code SetDefaultPIB Code 0x02...

Page 65: ...VRFIN 0 3 to VDDRFIO 0 3 V Analog input voltage VAIN 0 3 to VDDIO 0 3 V Digital output voltage VDO Ta 25 C 0 3 to VDDIO 0 3 V RF output voltage VRFO VSS 0 V 0 to VDDIO 0 3 V Analog output voltage VAO...

Page 66: ...requency FSCLK SCLK pin 1 2 8 MHz SCI clock input duty ratio DSCLK SCLK pin 45 50 55 RF channel frequency 8 FRF ANT_1 pin ANT_2 pin 2405 2480 MHz Maximum RF input level PRFIN 40 ppm PER 1 20 0 dBm 6 V...

Page 67: ...te 10 11 56 mA 10 The standard conditions are when VDDIO 3 0 V and VDDCORE VDDRF VDDANA 2 5 V 11 These values may be exceeded depending on the operation of the MCU used along with the ML7065 These val...

Page 68: ...V CIN Input pins 12 13 14 15 16 6 pF COUT Output pins 17 18 19 9 pF CRFIO RF input output pin 20 9 pF Input capacitance CA Analog input pin 21 9 pF 12 Applies to the pins that are indicated as I in t...

Page 69: ...Internal TX RX SW used 50 ohm Receiver Receiver sensitivity RIN 40 ppm PER 1 90 85 dBm Receiver jamming resistance adjacent channel PER 1 Wanted 82 dBm 0 dB Receiver jamming resistance alternate chann...

Page 70: ...le time TCEON 50 us SCEN disable time TCEOFF 50 us SINTN disable time TSINTDIS 0 68 us SCLK H pulse width TWCKH 50 ns SCLK L pulse width TWCKL 50 ns SDIN input setup time TDISU 5 ns SDIN input hold ti...

Page 71: ...al Chapter 8 Electrical Characteristics 65 When SCLK is a positive clock SCEN SCLK SDO SDIN MSB IN BITS6 1 LSB IN TCEEN0 FSCLK1 or FSCLK2 TWCKH TDISU TWCKL MSB OUT BITS6 1 LSB OUT 24 TCEH TCEDIS TDOH...

Page 72: ...SINT pin signal occurs at the timing independent of the signals of other clock synchronous serial interface related pins The above diagrams show the case of input output from the MSB It can be changed...

Page 73: ...TN delay time at power ON TRDL Applies to all power supply pins After power ON 5 ms RESETN pulse time TRPLS 200 ns SRESETN pulse time TSRPLS RESETN 1 200 ns SRESETN delay time when ti TRDOP 5 ms RESET...

Page 74: ...Min Typ Max Unit Power ON time difference TPWON At power ON Applies to all power supply pins 1 5 ms Notes Power can be applied to the power supply pins in any sequence However the time difference betw...

Page 75: ...ht g 0 095 TYP 5 Rev No Last Revised Preliminary Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed...

Page 76: ...VDD_IO power supply Therefore if VDD_IO is used with 2 75 V or higher a regulator is required We are currently considering our future plan to replace the PLL_LFO pin with an N C pin by eliminating the...

Page 77: ...DDIO 3 0 V and VDDCORE VDDRF VDDANA 2 5 V VDD_CORE common GND common 1 F VDD_IO common GND common 1 F VDD_D_RF GND_D 100pF 0 1 F VDD_RF GND_RF CORE power supply 2 5 V 7pF 0 1 F VDD_VCO GND_RF 100pF 2...

Page 78: ...ML7065 033 User s Manual Revision History 72 Revision History Page Document No Date Previous Edition Current Edition Description FEUL7065_033 01 Sep 15 2005 Final edition 1...

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