ML7065-033 User’s Manual
Chapter 7 Commands
19
7.2.3 CLK_CTL0
Function: Controls clocks.
Command: 0x1D
Address: 0xF004
Access: Config
Initial value: 0x0000
Bit
Register name
Function
W/R
Initial value
15 SLEEP
Stops all the clocks including OSC.
0: Operate 1: Stop
W/R 0
14 SUSPEND
Stops all the clocks except OSC and PLL
0: Operate 1: Stop
W/R 0
13-0 Reserve
Reserved
W/R
0b00_0000_0000_0000
* Returning from the sleep mode is carried out by an input to the SRESETN pin.
* Do not write data to any bits other than bits 15 and 14.
Always write “0s” to bits 13 to 0. If other than 0 is written, the device operates abnormally.
7.2.4 CLK_CTL1
Function: Controls clocks.
Command: 0x1E
Address: 0xF006
Access: Config
Initial value: 0x0020
Bit
Register name
Function
W/R
Initial value
15 OUT_CLK_SEL
Selects the source oscillation clock of the external
supply clock.
0: 2 MHz 1: 16 MHz
W/R 0
14-8 Reserve
Reserved
RO
0b000_0000
7-0 CLK_DIV_OUT
Specifies the divide ratio of the external supply clock.
Settable range: 1000_0000 to 0000_0000
W/R 0b0010_0000
CLKGEN uses CLK_DIV_OUT-1 as the comparing value of the frequency divider and inverts the most significant bit
of the frequency divider if the value of the frequency divider matches the compared value. CLKGEN outputs the most
significant bit of the frequency divider as the external supply clock (CLKOUT).
Therefore an external supply clock of CLK_DIV_OUT*2 (divide ratio) is output.
The default external supply clock frequency is as follows:
CLKOUT = 2 MHz/32(divide ratio)*2 = 31.25 kHz
When CLK_DIV_OUT is set to 0b0000_0000, clock dividing is not performed and the clock that has been selected by
OUT_CLK_SEL is directly output to CLKOUT.
When CLK_DIV_OUT is set to a value between 0b1111_1111 and 0b1000_0000, it is set to 0b1000_0000.
When 2 MHz is selected, the settable range is 7.8125 kHz to 2 MHz.
When 16 MHz is selected, the settable range is 62.5 kHz to 16 MHz.
