Ocean Optics Flame-S, User Manual

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8: Firmware and Advanced Communications
225-00000-000-11-201604 77
Register
Address
Description
Default
Value
Min
Value
Max
Value
Time Base
0x00
*
Master Clock Counter Divisor 24 1 0xFFFF 48MHz
0x04 FPGA Firmware Version (Read Only)
0x08 Continuous Strobe Timer Interval Divisor 48000 0 0xFFFF
Continuous
Strobe Base
Clock
(see Register
0x0C)
0x0C Continuous Strobe Base Clock Divisor 4800 0 0xFFFF 48MHz
0x0C Continuous Strobe LSB Register 4800 0 0xFFFF 48MHz
0x10
*
Integration Period Base Clock Divisor 480 0 0xFFFF 48MHz
0x10
*
Integration Period LSB Register 480 0 0xFFFF 1KHz
0x14
Set base_clk or base_clkx2
0: base_clk
1: base_clkx2
0 0 1 N/A
0x18
*
Integration Clock Timer Divisor 600 0 0xFFFF
Integration
Period Base
Clock
(see Register
0x10)
0x18
*
Integration Period MSB Register
0x20 Reserved
0x28
Hardware Trigger Delay
– Number of Master
Clock cycles to delay when in External
Hardware Trigger mode before the start of the
integration period
0 0 0xFFFF
0x28
Hardware Trigger Delay
– Delay the start of
integration from the rising edge of the trigger in
500ns increments 0 0 0xFFFF