NXP Semiconductors MC9S08PA4, Reference Manual

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The result of the FIFO is accessed by ADC_RH:ADC_RL registers, when FIFO function
is enabled. The result must be read via these two registers by the same order of analog
input channel FIFO to get the proper results. Don't read ADC_RH:ADC_RL until all of
the conversions are completed in FIFO mode. The ADC_SC1[COCO] bit will be set only
when all conversions indicated by the analog input channel FIFO complete whatever
software or hardware trigger is set. An interrupt request will be submitted to CPU if the
ADC_SC1[AIEN] is set when the FIFO conversion completes and the
ADC_SC1[COCO] bit is set.
AD CHANNEL FIFO
AD RESUL
T FIFO
AFDEP
ADC_RL read
ADC_RH read
ADCH write
FIFO Read/Write Logic reset
Result FIFO read pointer
Channel FIFO write pointer
Result FIFO write pointer
Channel FIFO read pointer
FIFO conversion start
FIFO Read/Write Logic
FIFO Work Logic
COMPARE
LOGIC
COMPARE
LOGIC
Result FIFO Fulfilled
Channel FIFO Fulfilled
COCO
CK
D Q
BUS CLK
CK
D Q
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result 0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7 5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
ADCH ADC_RH ADC_RL
Figure 15-2. FADC FIFO structure
If software trigger is enabled, the next analog channel is fetched from analog input
channel FIFO as soon as a conversion completes and its result is stored in the result
FIFO. When all conversions set in the analog input channel FIFO completes, the
ADC_SC1[COCO] bit is set and an interrupt request will be submitted to CPU if the
ADC_SC1[AIEN] bit is set.
Functional description
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
314 NXP Semiconductors