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NXP Semiconductors MC9S08PA4, Reference Manual

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A AND B Data (Full Mode) 

̶ 

This is called a full mode because address, data, and R/W

(optionally) must match within the same bus cycle to cause a trigger event. Comparator A
checks address, the low byte of comparator B checks data, and R/W is checked against
RWA if RWAEN = 1. The high-order half of comparator B is not used.

In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN =
TAG = 1), but if you do, the comparator B data match is ignored for the purpose of
issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator
A address matches.

A AND NOT B Data (Full Mode) 

̶ 

Address must match comparator A, data must not

match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All
three conditions must be met within the same bus cycle to cause a trigger.

In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN =
TAG = 1), but if you do, the comparator B data match is ignored for the purpose of
issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator
A address matches.

Event-Only B (Store Data) 

̶ 

Trigger events occur each time the address matches the

value in comparator B. Trigger events cause the data to be captured into the FIFO. The
debug run ends when the FIFO becomes full.

A Then Event-Only B (Store Data) 

̶ 

After the address has matched the value in

comparator A, a trigger event occurs each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run
ends when the FIFO becomes full.

Inside Range (A ≤ Address ≤ B) 

̶ 

A trigger occurs when the address is greater than or

equal to the value in comparator A and less than or equal to the value in comparator B at
the same time.

Outside Range (Address < A or Address > B) 

̶ 

A trigger occurs when the address is

either less than the value in comparator A or greater than the value in comparator B.

18.3.6 Hardware breakpoints

The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger
conditions described in 

Trigger modes

 to be used to generate a hardware breakpoint

request to the CPU. TAG in DBGC controls whether the breakpoint request will be
treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the
current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches

On-chip debug system (DBG)

MC9S08PA4 Reference Manual, Rev. 5, 08/2017

364

NXP Semiconductors

Summary of Contents for MC9S08PA4

Page 1: ...MC9S08PA4 Reference Manual Supports MC9S08PA4 Document Number MC9S08PA4RM Rev 5 08 2017 ...

Page 2: ...MC9S08PA4 Reference Manual Rev 5 08 2017 2 NXP Semiconductors ...

Page 3: ...ackground mode select BKGD MS 33 2 2 5 Port A input output I O pins PTA5 PTA0 34 2 2 6 Port B input output I O pins PTB7 PTB0 34 2 2 7 Port C input output I O pins PTC3 PTC0 34 2 2 8 True open drain pins PTB0 34 2 2 9 High current drive pins PTB4 PTB5 34 2 3 Peripheral pinouts 35 Chapter 3 Power management 3 1 Introduction 37 3 2 Features 37 3 2 1 Run mode 37 3 2 2 Wait mode 38 3 2 3 Stop3 mode 38...

Page 4: ...rrupt vector assignments 46 4 3 Register addresses and bit assignments 47 4 4 Random access memory RAM 55 4 5 Flash and EEPROM 56 4 5 1 Overview 56 4 5 2 Function descriptions 58 4 5 2 1 Modes of operation 58 4 5 2 2 Flash and EEPROM memory map 58 4 5 2 3 Flash and EEPROM initialization after system reset 58 4 5 2 4 Flash and EEPROM command operations 59 4 5 2 5 Flash and EEPROM interrupts 64 4 5 ...

Page 5: ...ter NVM_FOPT 95 Chapter 5 Interrupt 5 1 Interrupts 97 5 1 1 Interrupt stack frame 98 5 1 2 Interrupt vectors sources and local masks 99 5 1 3 Hardware nested interrupt 101 5 1 3 1 Interrupt priority level register 103 5 1 3 2 Interrupt priority level comparator set 104 5 1 3 3 Interrupt priority mask update and restore mechanism 104 5 1 3 4 Integration and application of the IPC 105 5 2 IRQ 105 5 ...

Page 6: ...onnection 115 6 5 1 ACMP output selection 115 6 5 2 SCI0 TxD modulation 116 6 5 3 SCI0 RxD capture 116 6 5 4 SCI0 RxD filter 117 6 5 5 RTC capture 117 6 5 6 ADC hardware trigger 117 6 6 System Control Registers 118 6 6 1 System Reset Status Register SYS_SRS 119 6 6 2 System Background Debug Force Reset Register SYS_SBDFR 121 6 6 3 System Device Identification Register High SYS_SDIDH 121 6 6 4 Syst...

Page 7: ...t 7 1 Introduction 131 7 2 Port data and data direction 133 7 3 Internal pullup enable 133 7 4 Input glitch filter setting 134 7 5 High current drive 134 7 6 Pin behavior in stop mode 134 7 7 Port data registers 134 7 7 1 Port A Data Register PORT_PTAD 135 7 7 2 Port B Data Register PORT_PTBD 136 7 7 3 Port C Data Register PORT_PTCD 136 7 7 4 Port High Drive Enable Register PORT_HDRVE 137 7 7 5 Po...

Page 8: ... reference clock ICSIRCLK 154 8 2 1 4 Fixed frequency clock ICSFFCLK 155 8 2 1 5 BDC clock 156 8 2 2 Modes of operation 156 8 2 2 1 FLL engaged internal FEI 157 8 2 2 2 FLL engaged external FEE 158 8 2 2 3 FLL bypassed internal FBI 158 8 2 2 4 FLL bypassed internal low power FBILP 158 8 2 2 5 FLL bypassed external FBE 159 8 2 2 6 FLL bypassed external low power FBELP 159 8 2 2 7 Stop STOP 160 8 2 ...

Page 9: ... Control Register 3 ICS_C3 169 8 6 4 ICS Control Register 4 ICS_C4 169 8 6 5 ICS Status Register ICS_S 170 8 6 6 OSC Status and Control Register ICS_OSCSC 171 8 7 System clock gating control registers 172 8 7 1 System Clock Gating Control 1 Register SCG_C1 173 8 7 2 System Clock Gating Control 2 Register SCG_C2 174 8 7 3 System Clock Gating Control 3 Register SCG_C3 175 8 7 4 System Clock Gating C...

Page 10: ... infrared functions 186 9 9 Analog 187 9 9 1 Analog to digital converter ADC 187 9 9 1 1 ADC channel assignments 188 9 9 1 2 Alternate clock 189 9 9 1 3 Hardware trigger 190 9 9 1 4 Temperature sensor 190 9 9 2 Analog comparator ACMP 191 9 9 2 1 ACMP configuration information 192 9 9 2 2 ACMP in stop3 mode 193 9 9 2 3 ACMP to FTM configuration information 193 9 9 2 4 ACMP for SCI0 RXD filter 193 9...

Page 11: ...10 3 6 Indexed Addressing Mode 204 10 3 6 1 Indexed No Offset IX 204 10 3 6 2 Indexed No Offset with Post Increment IX 204 10 3 6 3 Indexed 8 Bit Offset IX1 204 10 3 6 4 Indexed 8 Bit Offset with Post Increment IX1 205 10 3 6 5 Indexed 16 Bit Offset IX2 205 10 3 6 6 SP Relative 8 Bit Offset SP1 205 10 3 6 7 SP Relative 16 Bit Offset SP2 206 10 3 7 Memory to memory Addressing Mode 206 10 3 7 1 Dire...

Page 12: ...p modes 226 11 1 2 3 KBI in Active Background mode 226 11 1 3 Block Diagram 226 11 2 External signals description 227 11 3 Register definition 227 11 4 Memory Map and Registers 227 11 4 1 KBI Status and Control Register KBIx_SC 228 11 4 2 KBIx Pin Enable Register KBIx_PE 228 11 4 3 KBIx Edge Select Register KBIx_ES 229 11 5 Functional Description 229 11 5 1 Edge only sensitivity 230 11 5 2 Edge an...

Page 13: ...8 12 3 4 Counter High FTMx_CNTH 239 12 3 5 Counter Low FTMx_CNTL 240 12 3 6 Modulo High FTMx_MODH 240 12 3 7 Modulo Low FTMx_MODL 241 12 3 8 Channel Status and Control FTMx_CnSC 241 12 3 9 Channel Value High FTMx_CnVH 243 12 3 10 Channel Value Low FTMx_CnVL 244 12 4 Functional Description 244 12 4 1 Clock Source 245 12 4 1 1 Counter Clock Source 245 12 4 2 Prescaler 246 12 4 3 Counter 246 12 4 3 1...

Page 14: ...troduction 259 13 2 Features 259 13 2 1 Modes of operation 259 13 2 1 1 Wait mode 259 13 2 1 2 Stop modes 260 13 2 2 Block diagram 260 13 3 Register definition 260 13 3 1 RTC Status and Control Register 1 RTC_SC1 261 13 3 2 RTC Status and Control Register 2 RTC_SC2 262 13 3 3 RTC Modulo Register High RTC_MODH 263 13 3 4 RTC Modulo Register Low RTC_MODL 263 13 3 5 RTC Counter Register High RTC_CNTH...

Page 15: ... SCI Status Register 1 SCIx_S1 277 14 3 6 SCI Status Register 2 SCIx_S2 279 14 3 7 SCI Control Register 3 SCIx_C3 280 14 3 8 SCI Data Register SCIx_D 282 14 4 Functional description 282 14 4 1 Baud rate generation 283 14 4 2 Transmitter functional description 283 14 4 2 1 Send break and queued idle 284 14 4 3 Receiver functional description 285 14 4 3 1 Data sampling technique 286 14 4 3 2 Receive...

Page 16: ...297 15 3 ADC Control Registers 298 15 3 1 Status and Control Register 1 ADC_SC1 298 15 3 2 Status and Control Register 2 ADC_SC2 300 15 3 3 Status and Control Register 3 ADC_SC3 301 15 3 4 Status and Control Register 4 ADC_SC4 302 15 3 5 Conversion Result High Register ADC_RH 303 15 3 6 Conversion Result Low Register ADC_RL 304 15 3 7 Compare Value High Register ADC_CVH 305 15 3 8 Compare Value Lo...

Page 17: ... 15 5 Initialization information 318 15 5 1 ADC module initialization example 318 15 5 1 1 Initialization sequence 318 15 5 1 2 Pseudo code example 319 15 5 2 ADC FIFO module initialization example 319 15 5 2 1 Pseudo code example 320 15 6 Application information 321 15 6 1 External pins and routing 321 15 6 1 1 Analog supply pins 321 15 6 1 2 Analog reference pins 321 15 6 1 3 Analog input pins 3...

Page 18: ...d Status Register ACMP_CS 330 16 3 2 ACMP Control Register 0 ACMP_C0 331 16 3 3 ACMP Control Register 1 ACMP_C1 331 16 3 4 ACMP Control Register 2 ACMP_C2 332 16 4 Functional description 332 16 5 Setup and operation of ACMP 333 16 6 Resets 334 16 7 Interrupts 334 Chapter 17 Watchdog WDOG 17 1 Introduction 335 17 1 1 Features 335 17 1 2 Block diagram 336 17 2 Memory map and register definition 337 ...

Page 19: ...uring the Watchdog 345 17 3 2 1 Reconfiguring the Watchdog 345 17 3 2 2 Unlocking the Watchdog 346 17 3 2 3 Example code Reconfiguring the Watchdog 346 17 3 3 Clock source 346 17 3 4 Using interrupts to delay resets 348 17 3 5 Backup reset 348 17 3 6 Functionality in debug and low power modes 348 17 3 7 Fast testing of the watchdog 349 17 3 7 1 Testing each byte of the counter 349 17 3 7 2 Enterin...

Page 20: ...BDC Breakpoint Register Low BDC_BKPTL 368 18 4 4 System Background Debug Force Reset Register BDC_SBDFR 368 Chapter 19 Debug module DBG 19 1 Introduction 371 19 1 1 Features 371 19 1 2 Modes of operation 372 19 1 3 Block diagram 372 19 2 Signal description 373 19 3 Memory map and registers 373 19 3 1 Debug Comparator A High Register DBG_CAH 374 19 3 2 Debug Comparator A Low Register DBG_CAL 375 19...

Page 21: ...gister DBG_CNT 387 19 4 Functional description 388 19 4 1 Comparator 388 19 4 1 1 RWA and RWAEN in full modes 388 19 4 1 2 Comparator C in loop1 capture mode 388 19 4 2 Breakpoints 389 19 4 2 1 Hardware breakpoints 389 19 4 3 Trigger selection 390 19 4 4 Trigger break control TBC 390 19 4 4 1 Begin and end trigger 391 19 4 4 2 Arming the DBG module 391 19 4 4 3 Trigger modes 392 19 4 5 FIFO 394 19...

Page 22: ...MC9S08PA4 Reference Manual Rev 5 08 2017 22 NXP Semiconductors ...

Page 23: ...wing table summarizes the peripheral availability per package type for the devices available Table 1 1 Memory and package availability Feature MC9S08PA4 Flash size bytes 4 096 EEPROM size bytes 128 RAM size bytes 512 SOIC 20 Yes TSSOP 16 Yes DFN 8 Yes Table 1 2 Feature availability Pin number 20 pin 16 pin 8 pin Bus frequency MHz 20 20 20 IRQ Yes WDOG Yes DBG Yes IPC Yes ICS Yes XOSC Yes No RTC Ye...

Page 24: ...nels 2 ch 2 ch 2 ch FTM1 channels 2 ch 2 ch 1 ch FTM2 channels internal 2 ch 2 ch 2 ch ADC 8 8 4 KBI pins 8 8 4 GPIO 18 14 6 1 2 MCU block diagram The block diagram below shows the structure of the MCUs MCU block diagram MC9S08PA4 Reference Manual Rev 5 08 2017 24 NXP Semiconductors ...

Page 25: ...TB0 KBI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTB2 KBI0P6 ADP6 PTB3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes KEYBOARD INTERRUPT MC9S08PA4 512 bytes MODULE KBI0 2 CH FLEX TIMER MODULE FTM1 ANALOG COMPARATOR ACMP CONTROLLER IPC 1 PTA4 ACMPO BKGD MS is an output only pin when ...

Page 26: ...fter reset 1 2 FTM2 Figure 1 2 System clock distribution diagram The clock system supplies ICSCLK BUS This up to 20 MHz clock source is used as the bus clock that is the reference to CPU and all peripherals Control bits in the ICS control registers determine which of the clock sources is connected Internal reference clock External reference clock Frequency locked loop FLL output ICSLCLK This clock...

Page 27: ...y independent of the ICS module The LPOCLK can be selected as the clock source to the RTC or WDOG modules OSCOUT This is the direct output of the external oscillator module and can be selected as the clock source for RTC WDOG and ADC TCLK0 This is an optional external clock source for the FTM0 module The TCLK0 must be limited to 1 4th frequency of the bus clock for synchronization TCLK1 This is an...

Page 28: ...System clock distribution MC9S08PA4 Reference Manual Rev 5 08 2017 28 NXP Semiconductors ...

Page 29: ...ins in PTA5 IRQ FTM1CH0 RESET PTB5 FTM1CH1 PTC3 PTC2 2 2 True open drain pins Figure 2 1 MC9S08PA4 20 pin SOIC package 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 VDD VSS PTB7 EXTAL PTB6 XTAL 1 PTB4 FTM1CH01 PTB3 KBI0P7 TCLK1 ADP7 PTB2 KBI0P6 ADP6 PTA2 KBI0P2 FTM0CH0 RxD0 ADP2 PTA3 KBI0P3 FTM0CH1 TxD0 ADP3 PTB0 KBI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 PTA1 KBI0P1 FTM0...

Page 30: ...voltage regulator provides a regulated lower voltage source to the CPU and to the MCU s other internal circuitry Typically application systems have two separate capacitors across the power pins In this case there should be a bulk electrolytic capacitor such as a 10 µF tantalum capacitor that provides bulk charge storage for the overall system and a 0 1 µF ceramic bypass capacitor located as near t...

Page 31: ...ypical crystal or resonator circuit RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup its value is not generally critical Typical systems use 1 M to 10 M Higher values are sensitive to humidity and lower values reduce gain and in extreme cases could prevent startup C1 and C2 are typically in the 5 pF to 25 pF range and are chosen to match the requ...

Page 32: ...ed a manual external reset can be added by supplying a simple switch to ground pull reset pin low to force a reset When the RESET pin function is enabled an internal pullup resistor is connected to this pin and a reset signal can feed into MCU with an input hysteresis POR reset brings RESET pin into its default configuration reset other than POR has no effect on the RESET pin function configuratio...

Page 33: ...he MCU into active background mode The BKGD pin is used primarily for background debug controller BDC communications using a custom protocol that uses 16 clock cycles of the target MCU s BDC clock per bit time The target MCU s BDC clock can run as fast as the bus clock so there should never be any significant capacitance connected to the BKGD MS pin that interferes with background serial communica...

Page 34: ...dual port bit basis The pulling devices are disengaged when configured for output mode PTB0 provide true open drain when operated as output 2 2 7 Port C input output I O pins PTC3 PTC0 PTC3 PTC0 are general purpose bidirectional I O port pins These port pins also have selectable pullup devices when configured for input mode and the pullup devices are selectable on an individual port bit basis The ...

Page 35: ...hen on chip peripheral systems use these pins see the appropriate module chapter Immediately after reset all pins are configured as high impedance general purpose IO with internal pullup devices disabled Table 2 1 Pin availability by package pin count Pin Number Lowest Priority Highest 20 SOIC 16 TSSOP 8 DFN Port Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 1 PTA5 IRQ FTM1CH0 RESET 2 2 2 PTA4 ACMPO BKGD MS 3 3...

Page 36: ...ble to get a spurious edge to the module User software must clear any associated flags before interrupts are enabled The table above illustrates the priority if multiple modules are enabled The highest priority module will have control over the pin Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module Disable a...

Page 37: ...wer Bus clocks are running Full voltage regulation is maintained Stop3 modes System clocks stopped voltage regulator in standby all internal circuits powered for fast recovery 3 2 1 Run mode This is the normal operating mode In this mode the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE 0xFFFF after reset The power supply is fully regu...

Page 38: ... all of the clocks in the MCU are halted by default but OSC clock and internal reference clock can be turned on by setting the ICS control registers The ICS enters its standby state as does the voltage regulator and the ADC The states of all of the internal registers and logic as well as the RAM content are maintained The I O pin states are not latched at the pin Instead they are maintained by vir...

Page 39: ...ailable 3 2 5 LVD enabled in stop mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage If the LVD is enabled in stop LVDE and LVDSE bits in SPMSC1 both set at the time the CPU executes a STOP instruction then the voltage regulator remains active during stop3 mode 3 2 6 Power modes behaviors Executing the WAIT or STOP comman...

Page 40: ...s and control MCU system states during supply voltage variations This system consists of a power on reset POR circuit and an LVD circuit with a user selectable trip voltage either high VLVDH or low VLVDL The LVD circuit is enabled when SPMSC1 LVDE is set and the trip voltage is selected by SPMSC2 LVDV The LVD is disabled upon entering the stop modes unless the SPMSC1 LVDSE bit is set or active BDM...

Page 41: ...tion by setting SPMSC1 LVDRE to 1 After an LVD reset has occurred the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV The SRS LVD bit is set following either an LVD reset or POR 3 3 3 Low voltage warning LVW The LVD system has a low voltage warning flag to indicate that the supply voltage is approaching the LVD voltage When a low voltage ...

Page 42: ... 8 R W 00h 3 5 2 44 3 5 1 System Power Management Status and Control 1 Register PMC_SPMSC1 This high page register contains status and control bits to support the low voltage detection function and to enable the bandgap voltage reference for use by the ADC module This register should be written during the user s reset initialization program to set the desired controls even if the desired settings ...

Page 43: ...ime after reset Additional writes are ignored 0 LVD events do not generate hardware resets 1 Force an MCU reset when an enabled low voltage detect event occurs 3 LVDSE Low Voltage Detect Stop Enable Provided LVDE 1 this read write bit determines whether the low voltage detect function operates when the MCU is in stop mode 0 Low voltage detect disabled during stop mode 1 Low voltage detect enabled ...

Page 44: ...d only field is reserved and always has the value 0 6 LVDV Low Voltage Detect Voltage Select This write once bit selects the low voltage detect LVD trip point setting See data sheet for details 0 Low trip point selected VLVD VLVDL 1 High trip point selected VLVD VLVDH 5 4 LVWV Low Voltage Warning Voltage Select This bit selects the low voltage warning LVW trip point voltage See data sheet for deta...

Page 45: ...h memory flash MC9S08PA4 4 096 bytes 8 pages of 512 bytes each Random access memory RAM MC9S08PA4 512 bytes Electrically erasable programmable read only memory EEPROM MC9S08PA4 128 bytes 64 pages of 2 bytes each Direct page registers 0x0000 through 0x003F High page registers 0x3000 through 0x30FF MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semiconductors 45 ...

Page 46: ...es shown in this table are the labels used in the header files for the device Table 4 1 Reset and interrupt vectors Address high low Vector Vector name 0xFFB0 FFB1 NVM Vnvm 0xFFB2 FFB3 Reserved Reserved 0xFFB4 FFB5 KBI0 Vkbi0 0xFFB6 FFB7 Reserved Reserved 0xFFB8 FFB9 RTC Vrtc 0xFFBA FFBB Reserved Reserved 0xFFBC FFBD Reserved Reserved 0xFEBE FFBF Reserved Reserved 0xFFC0 FFC1 Reserved Reserved 0xF...

Page 47: ...xFFE4 FFE5 FTM1 channel 0 Vftm1ch0 0xFFE6 FFE7 FTM2 overflow Vftm2ovf 0xFFE8 FFE9 Reserved Reserved 0xFFEA FFEB Reserved Reserved 0xFFEC FFED Reserved Reserved 0xFFEE FFEF Reserved Reserved 0xFFF0 FFF1 FTM2 channel 1 Vftm2ch1 0xFFF2 FFF3 FTM2 channel 0 Vftm2ch0 0xFFF4 FFF5 Reserved Reserved 0xFFF6 FFF7 Clock loss of lock Vclk 0xFFF8 FFF9 Low voltage warning Vlvw 0xFFFA FFFB IRQ or Watchdog Virq or...

Page 48: ...0x30B8 0x30BA 3 Port input enable 0x30C0 0x30CA 11 FTM2 0x30EC 0x30EF 4 Port filter 0x30F0 0x30F2 3 Port pullup 0x30F8 0x30FF 8 SYS The registers in the devices are divided into two groups Direct page registers are located in the first 64 locations in the memory map so they can be accessed with efficient direct addressing mode instructions High page registers are used much less often so they are l...

Page 49: ...O AIEN ADCO ADCH 0x0011 ADC_SC2 ADACT ADTRG ACFE ACFGT FEMPT Y FFULL 0x0012 ADC_SC3 ADLPC ADIV ADLSM P MODE ADICLK 0x0013 ADC_SC4 ASCAN E ACFSEL AFDEP 0x0014 ADC_RH Bit 15 14 13 12 11 10 9 Bit 8 0x0015 ADC_RL Bit 7 6 5 4 3 2 1 Bit 0 0x0016 ADC_CVH Bit 15 14 13 12 11 10 9 Bit 8 0x0017 ADC_CVL Bit 7 6 5 4 3 2 1 Bit 0 0x0018 0X001F Reserved 0x0020 FTM0_SC TOF TOIE CPWMS CLKS1 CLKS0 PS2 PS1 PS0 0x0021...

Page 50: ...QIE IRQMO D 0x003C KBI0_SC KBF KBACK KBIE KBMOD 0x003D Reserved 0x003E IPC_SC IPCE PSE PSF PULIPM IPM 0x003F IPC_IPMPS IPM3 IPM2 IPM1 IPM0 Table 4 4 High page register allocation Address Register name Bit 7 6 5 4 3 2 1 Bit 0 0x3000 SYS_SRS POR PIN WDOG ILOP ILAD LOC LVD 0x3001 SYS_SBDFR BDFR 0x3002 SYS_SDIDH ID11 ID10 ID9 ID8 0x3003 SYS_SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x3004 SYS_SOPT1 SCI0PS...

Page 51: ...Reserved 0x3024 NVM_FCNFG CCIE IGNSF FDFD FSFD 0x3025 NVM_FERCNFG DFDIE SFDIE 0x3026 NVM_FSTAT CCIF ACCER R FPVIOL MGBUS Y MGSTA T1 MGSTA T0 0x3027 NVM_FERSTAT DFDIF SFDIF 0x3028 NVM_FPROT FPOEN FPHDIS FPHS1 FPHS0 0x3029 NVM_EEPROT DPOPE N DPS1 DPS0 0x302A NVM_FCCOBHI CCOB1 5 CCOB1 4 CCOB1 3 CCOB1 2 CCOB1 1 CCOB1 0 CCOB9 CCOB8 0x302B NVM_FCCOBLO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x30...

Page 52: ...0x3051 IPC_ILRS1 ILR7 ILR6 ILR5 ILR4 0x3052 IPC_ILRS2 ILR11 ILR10 ILR9 ILR8 0x3053 IPC_ILRS3 ILR15 ILR14 ILR13 ILR12 0x3054 IPC_ILRS4 ILR19 ILR18 ILR17 ILR16 0x3055 IPC_ILRS5 ILR23 ILR22 ILR21 ILR20 0x3056 IPC_ILRS6 ILR27 ILR26 ILR25 ILR24 0x3057 IPC_ILRS7 ILR31 ILR30 ILR29 ILR28 0x3058 IPC_ILRS8 ILR35 ILR34 ILR33 ILR32 0x3059 IPC_ILRS9 ILR39 ILR38 ILR37 ILR36 0x305A 0x305F Reserved 0x3060 0x3069 ...

Page 53: ...3 PTBOE2 PTBOE1 PTBOE0 0x30B2 PORT_PTCOE PTCOE 3 PTCOE 2 PTCOE 1 PTCOE 0 0x30B3 0x30B7 Reserved 0x30B8 PORT_PTAIE PTAIE5 PTAIE3 PTAIE2 PTAIE1 PTAIE0 0x30B9 PORT_PTBIE PTBIE7 PTBIE6 PTBIE5 PTBIE4 PTBIE3 PTBIE2 PTBIE1 PTBIE0 0x30BA PORT_PTCIE PTCIE3 PTCIE2 PTCIE1 PTCIE0 0x30BB 0x30BF Reserved 0x30C0 FTM2_SC TOF TOIE CPWMS CLKS1 CLKS0 PS2 PS1 PS0 0x30C1 FTM2_CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x30C2 ...

Page 54: ...ry locations shown in the following table are used for storing values used by several registers These registers include an 8 byte backdoor key NV_BACKKEY which can be used to gain access to secure memory resources During reset events the contents of NVPROT and NVOPT in the reserved flash memory are transferred into corresponding FPROT and FOPT registers in the high page registers area to control s...

Page 55: ... The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode Any single bit in this area can be accessed with the bit manipulation instructions BCLR BSET BRCLR and BRSET The RAM retains data when the MCU is in low power wait or stop3 mode At power on the contents of RAM are uninitialized RAM data is unaffected by any reset provided that the supply voltage does...

Page 56: ... parameters The memory controller must complete the execution of a command before the FCCOB register is written to with a new command CAUTION A flash byte or longword must be in the erased state before being programmed Cumulative programming of bits within a flash byte or longword is not allowed The flash memory is read as bytes Read access time is one bus cycle for bytes For flash memory an erase...

Page 57: ...sh memory EEPROM features 128 bytes of EEPROM memory composed of one 128 byte EEPROM block divided into 64 sectors of 2 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verification and generation of ECC parity bits Fast sector erase and byte program operation Protection scheme to prevent accidental pro...

Page 58: ...e current NVM operation will be completed before the MCU is allowed to enter stop mode 4 5 2 2 Flash and EEPROM memory map The MCU places the flash memory between global address 0x0000 and 0xFFFF as shown in the following table Not all flash are available to users because some addresses are overlapped with RAM EEPROM and registers MC9S08PA4 contains a piece of 4 KB flash that is fully available fo...

Page 59: ...are allowed after the hold is removed Completion of the initialization sequence is marked by setting FSTAT CCIF high which enables user commands If a reset occurs while any flash or EEPROM command is in progress that command will be immediately aborted The state of the word being programmed or the sector block being erased is not guaranteed 4 5 2 4 Flash and EEPROM command operations Flash and EEP...

Page 60: ...register to launch command Read FSTAT register CCIF Set Bit Polling for Command Completion Check Clear CCIF 0x80 Parameters Write FSTAT register Clear ACCERR FPVIOL 0x30 or FPVIOL Set Access Error and Protection Violation Check Set No No No Yes Yes Yes No Yes END register No No Yes Yes Clock Divider Value Check FCCOB Availability Check register Correct register Figure 4 3 Generic flash and EEPROM ...

Page 61: ... 0x06 7 6 8 6 0x07 8 6 9 6 0x08 9 6 10 6 0x09 10 6 11 6 0x0A 11 6 12 6 0x0B 12 6 13 6 0x0C 13 6 14 6 0x0D 14 6 15 6 0x0E 15 6 16 6 0x0F 16 6 17 6 0x10 17 6 18 6 0x11 18 6 19 6 0x12 19 6 20 0 0x13 1 BUSCLK is greater than this value 2 BUSCLK is less than or equal to this value CAUTION Programming or erasing the flash and EEPROM memory cannot be performed if the bus clock runs at less than 0 8 MHz S...

Page 62: ...ister to provide a command code and its relevant parameters to the memory controller First the user must set up all required FCCOB field Then they can initiate the command s execution by writing a 1 to the FSTAT CCIF bit This action clears the CCIF command completion flag to 0 When the user clears the FSTAT CCIF bit all FCCOB parameter field are locked and cannot be changed by the user until the c...

Page 63: ...n the memory controller will return FSTAT CCIF to 1 and the FCCOB register will be used to communicate any results The following table presents the valid flash and EEPROM commands as enabled by the combination of the functional MCU mode with the MCU security state of unsecured or secured MCU secured state is selected by NVM_FSEC SEC Table 4 9 Flash and EEPROM commands by mode and security state FC...

Page 64: ...mplete CCIF FSTAT register CCIE FCNFG register I Bit ECC double bit fault on flash and EEPROM read DFDIF FERSTAT register DFDIE FERCNFG register I Bit ECC single bit fault on flash and EEPROM read SFDIF FERSTAT register SFDIE FERCNFG register I Bit 4 5 2 5 1 Description of flash and EEPROM interrupt operation The flash module uses the FSTAT CCIF flag in combination with the FCNFG CCIE interrupt en...

Page 65: ...n The flash memory addresses covered by these protectable regions are shown in the flash memory map The higher address region is mainly targeted to hold the boot loader code because it covers the vector space Flash Configuration Field 16 bytes 0xFF70 0xFF7F Flash Protected Unprotected Higher Region 1 2 3 4Kbytes Protection Movable End Protection Fixed End 0x0000 Flash START 0xF000 0xF400 0xFC00 0x...

Page 66: ... provides protection to the MCU During the reset sequence the FPROT register is loaded with the contents of the flash protection byte in the flash configuration field at global address 0xFF7C in flash memory The protection functions depend on the configuration of bit settings in FPORT register Table 4 12 Flash protection function FPOPEN FPHDIS Function1 1 1 No flash protection 1 0 Protected high r...

Page 67: ...o the FPROT register will be ignored The contents of the FPROT register reflect the active protection scenario See the FPROT FPHS and FPROT FPLS bit descriptions for additional restrictions Table 4 13 Flash protection scenario transitions From protection scenario To protection scenario 0 1 2 3 0 1 2 3 The flash protection address range is listed in the following two tables regarding the scenarios ...

Page 68: ...SEC register using data read from the security byte of the flash and EEPROM configuration field at global address 0xFF7F The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary flash and EEPROM erase and program commands are available and that the upper region of the flash is unprotected If the fl...

Page 69: ... SEC bits are forced to the unsecure state of 10 The verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command A reset of the MCU is the only method to re enable the verify backdoor access key command The security as defined in the flash and EEPROM security byte 0xFF7F is not changed by using the v...

Page 70: ...5 2 8 Flash and EEPROM commands 4 5 2 8 1 Flash commands The following table summarizes the valid flash commands as well as the effects of the commands on the flash block and other resources within the flash and EEPROM module Table 4 16 Flash commands FCMD Command Function on flash memory 0x01 Erase verify all blocks Verify that all flash and EEPROM blocks are erased 0x02 Erase verify block Verify...

Page 71: ...OM commands FCMD Command Function on flash memory 0x01 Erase verify all blocks Verify that all EEPROM and flash blocks are erased 0x02 Erase verify block Verify that an EEPROM block is erased 0x08 Erase all block Erase all EEPROM and flash blocks An erase of all EEPROM blocks is possible only when the FPROT FPHDIS and FPROT FPOEN bits and the DPOPEN bit in the EEPORT register are set prior to laun...

Page 72: ...lash and EEPROM command summary This section provides details of all available flash commands launched by a command write sequence The FSTAT ACCERR bit will be set during the command write sequence if any of the following illegal steps are performed causing the command not to be processed by the memory controller Starting any command write sequence that programs or erases flash memory before initi...

Page 73: ...and both NVM_FSTAT MGSTAT bits will be set Table 4 20 Erase verify all blocks command error handling Register Error bit Error condition NVM_FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch FPVIOL None MGSTAT1 Set if any errors have been encountered during the read1 or if blank check failed MGSTAT0 Set if any non correctable errors have been encountered during the read or if blank check failed ...

Page 74: ...rify flash section command The erase verify flash section command will verify that a section of code in the flash memory is erased The erase verify flash section command defines the starting point of the code to be verified and the number of longwords Table 4 23 Erase verify flash section command FCCOB requirements CCOBIX 2 0 NVM_FCCOBHI parameters NVM_FCCOBLO parameters 000 0x03 Global address 23...

Page 75: ...nce and can not be erased It can be used to store the product ID or any other information that can be written only once It is programmed using the program once command described in Program once command To avoid code runaway the read once command must not be executed from the flash block containing the program once reserved field Table 4 25 Read once command FCCOB requirements CCOBIX 2 0 FCCOB para...

Page 76: ...LO parameters 000 0x06 Global address 23 16 to identify flash block 001 Global address 15 0 of longwords location to be programmed1 010 Word 0 longword 0 program value 011 Word 1 longword 0 program value 100 Word 2 longword 1 program value 101 Word 3 longword 1 program value 1 Global address 1 0 must be 00 Upon clearing NVM_FSTAT CCIF to launch the program flash command the memory controller will ...

Page 77: ...ce command must not be executed from the flash block containing the program once reserved field Table 4 29 Program once command FCCOB requirements CCOBIX 2 0 FCCOB parameters 000 0x07 Not required 001 Program Once phrase index 0x000 0x0007 010 Program once Word 0 value 011 Program once Word 1value 100 Program once Word 2 value 101 Program once Word 3 value Upon clearing FSTAT CCIF to launch the pr...

Page 78: ...ot required Upon clearing NVM_FSTAT CCIF to launch the erase all blocks command the memory controller will erase the entire NVM memory space and verify that it is erased If the memory controller verifies that the entire NVM memory space was properly erased security will be released Therefore the device is in unsecured state During the execution of this command NVM_FSTAT CCIF 0 the user must not wr...

Page 79: ...see Table 4 9 Set if an invalid global address 23 16 is supplied1 FPVIOL Set if an area of the selected flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation2 MGSTAT0 Set if any non correctable errors have been encountered during the verify operation2 1 As defined by the memory map for NVM 2 As found in the memory map for NVM 4 5 2 9 9 Erase flash sec...

Page 80: ...ash command the memory controller will erase the entire flash and EEPROM memory space and verify that it is erased If the memory controller verifies that the entire flash and EEPROM memory space was properly erased security will be released If the erase verify is not successful the unsecure flash operation sets FSTAT MGSTAT1 and terminates without changing the security state During the execution o...

Page 81: ...mory controller sets the NVM_FSTAT ACCERR bit If the command is enabled the memory controller compares the key provided in FCCOB to the backdoor comparison key in the flash configuration field with Key 0 compared to 0xFF70 and so on If the backdoor keys match security will be released If the backdoor keys do not match security is not released and all future attempts to execute the verify backdoor ...

Page 82: ... otherwise eventually share the same address on the MCU global memory map Upon clearing NVM_FSTAT CCIF to launch the set user margin level command the memory controller will set the user margin level for the targeted block and then set the NVM_FSTAT CCIF flag Note When the EEPROM block is targeted the EEPROM user margin levels are applied only to the EEPROM reads However when the Flash block is ta...

Page 83: ... point of the data to be verified and the number of bytes Table 4 44 Erase verify EEPROM section command FCCOB requirements CCOBIX 2 0 NVM_FCCOBHI parameters NVM_FCCOBLO parameters 000 0x10 Global address 23 16 to identify the EEPROM block 001 Global address 15 0 of the first byte to be verified 010 Number of bytes to be verified Upon clearing NVM_FSTAT CCIF to launch the erase verify that EEPROM ...

Page 84: ...ble 4 46 Program EEPROM command FCCOB requirements CCOBIX 2 0 NVM_FCCOBHI parameters NVM_FCCOBLO parameters 000 0x11 Global address 23 16 to identify the EEPROM block 001 Global address 15 0 of the first word to be verified 010 Byte 0 program value 011 Byte 1 program value if desired 100 Byte 2 program value if desired 101 Byte 3 program value if desired Upon clearing NVM_FSTAT CCIF to launch the ...

Page 85: ...address 23 16 to identify EEPROM block 001 Global address 15 0 anywhere within the sector to be erased See Overview for EEPROM sector size Upon clearing NVM_FSTAT CCIF to launch the erase EEPROM sector command the memory controller will erase the selected EEPROM sector and verify that it is erased The NVM_FSTAT CCIF flag will set after the erase EEPROM sector operation has completed Table 4 49 Era...

Page 86: ...6 4 88 3025 Flash Error Configuration Register NVM_FERCNFG 8 R W 00h 4 6 5 89 3026 Flash Status Register NVM_FSTAT 8 R W 80h 4 6 6 90 3027 Flash Error Status Register NVM_FERSTAT 8 R W 00h 4 6 7 91 3028 Flash Protection Register NVM_FPROT 8 R Undefined 4 6 8 92 3029 EEPROM Protection Register NVM_EEPROT 8 R W Undefined 4 6 9 93 302A Flash Common Command Object Register High NVM_FCCOBHI 8 R W 00h 4...

Page 87: ...egister NVM_FSEC The FSEC register holds all bits associated with the security of the MCU and NVM module All bits in the FSEC register are readable but not writable During the reset sequence the FSEC register is loaded with the contents of the flash security byte in the flash configuration field at global address 0xFF7F located in flash memory See Security for security function Address 3020h base ...

Page 88: ...Bit 7 6 5 4 3 2 1 0 Read 0 CCOBIX Write Reset 0 0 0 0 0 0 0 0 NVM_FCCOBIX field descriptions Field Description 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 CCOBIX Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to 4 6 4 Flash Configuration Register NVM_FCNFG The FCNFG...

Page 89: ... cleared by writing a 0 to FDFD 0 Flash array read operations will set the FERSTAT DFDIF flag only if a double bit fault is detected 1 Any flash array read operation will force the FERSTAT DFDIF flag to be set and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set 0 FSFD Force Single Bit Fault Detect The FSFD bit allows the user to simulate a single...

Page 90: ...h Bit 7 6 5 4 3 2 1 0 Read CCIF 0 ACCERR FPVIOL MGBUSY 0 MGSTAT Write Reset 1 0 0 0 0 0 0 0 NVM_FSTAT field descriptions Field Description 7 CCIF Command Complete Interrupt Flag The CCIF flag indicates that a flash command has completed The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation 0 Flash command in progres...

Page 91: ...MGSTAT Memory Controller Command Completion Status Flag One or more MGSTAT flag bits are set if an error is detected during execution of a flash command or during the flash reset sequence NOTE Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence 4 6 7 Flash Error Status Register NVM_FERSTAT The FERSTAT register reflects the error status of intern...

Page 92: ...eration returning invalid data was attempted on a flash block that was under a flash command operation The SFDIF flag is cleared by writing a 1 to SFDIF Writing a 0 to SFDIF has no effect on SRFDIF 0 No single bit fault detected 1 Single bit fault detected and corrected or a flash array read operation returning invalid data was attempted while command running 4 6 8 Flash Protection Register NVM_FP...

Page 93: ...led 1 Protection Unprotection disabled 4 3 FPHS Flash Protection Higher Address Size The FPHS bits determine the size of the protected unprotected area in flash memory The FPHS bits can be written to only while the FPHDIS bit is set Reserved This field is reserved This read only field is reserved and always has the value 0 4 6 9 EEPROM Protection Register NVM_EEPROT The EEPROT register defines whi...

Page 94: ...EN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 6 2 Reserved This field is reserved This read only field is reserved and always has the value 0 DPS EEPROM Protection Size These bits determine the size of the protected area in the EEPROM memory 4 6 10 Fl...

Page 95: ...0 0 0 0 0 0 0 NVM_FCCOBLO field descriptions Field Description CCOB Common Command Object Bit 7 0 Low 8 bits of common command object register 4 6 12 Flash Option Register NVM_FOPT The FOPT register is the flash option register During the reset sequence the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory as i...

Page 96: ...ble as nonvolatile bits During the reset sequence the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory Flash and EEPROM registers descriptions MC9S08PA4 Reference Manual Rev 5 08 2017 96 NXP Semiconductors ...

Page 97: ...gram initializes the stack pointer and performs other system setups before clearing the I bit to allow the CPU to respond to interrupts When the CPU receives a qualified interrupt request it completes the current instruction before responding to the interrupt The interrupt sequence obeys the same cycle by cycle sequence as the SWI instruction and consists of Saving the CPU registers on the stack S...

Page 98: ...pt service routine ISR and restore it immediately before the RTI that is used to return from the ISR When two or more interrupts are pending when the I bit is cleared the highest priority source is serviced first 5 1 1 Interrupt stack frame The following figure shows the contents and organization of a stack frame Before the interrupt the stack pointer SP points at the next available byte location ...

Page 99: ... it will be registered so that it can be serviced after completion of the current ISR 5 1 2 Interrupt vectors sources and local masks The following table provides a summary of all interrupt sources High priority sources are located toward the bottom of the table The high order byte of the address for the interrupt service routine is located at the first address in the vector address column and the...

Page 100: ...used Unused Unused 27 0xFFC8 FFC9 Unused Unused Unused Unused Unused 26 0xFFCA FFCB Unused Unused Unused Unused Unused 25 0xFFCC FFCD Vsci0tx SCI0 TRDE TC TIE TCIE SCI0 transmit 24 0xFFCE FFCF Vsci0rx SCI0 IDLE RDRF LBKDIF RXEDGIF ILIE RIE LBKDIE RXEDGIE SCI0 receive 23 0xFFD0 FFD1 Vsci0err SCI0 OR NF FE PF ORIE NEIE FEIE PEIE SCI0 error 22 0xFFD2 FFD3 Vadc ADC COCO AIEN ADC conversion complete in...

Page 101: ...s of lock 3 0xFFF8 FFF9 Vlvw System control LVWF LVWIE Low voltage warning 2 0xFFFA FFFB Vwdog Virq WDOG IRQ WDOGF IRQF WDOGI IRQIE WDOG timeout IRQ interrupt 1 0xFFFC FFFD Vswi Core SWI Instruction Software interrupt 0 0xFFFE FFFF Vreset System control WDOG LVD RESET pin Illegal opcode Illegal address POR ICS BDFR WDOGE LVDRE RSTPE CME Watchdog timer Low voltage detect External pin Illegal opcode...

Page 102: ... update of interrupt priority mask with being serviced interrupt source priority level when the interrupt vector is being fetched Interrupt priority mask can be modified during main flow or interrupt service execution Previous interrupt mask level is automatically stored when interrupt vector is fetched four levels of previous values accommodated Interrupts MC9S08PA4 Reference Manual Rev 5 08 2017...

Page 103: ...able 00 1 0 Stop Figure 5 2 Interrupt priority controller block diagram The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts with programmable priority levels This module also allows implementation of preemptive interrupt according to the programmed interrupt priority with minimal software overhead The IPC consists of three major functional blocks The interrupt prio...

Page 104: ...interrupt priority arbitration as defined by the HCS08 CPU because the IPC is an external module Therefore if two or more interrupts are present in the HCS08 CPU at the same time the inherent priority in HCS08 CPU will perform arbitration by the inherent interrupt priority 5 1 3 3 Interrupt priority mask update and restore mechanism The interrupt priority mask IPM is two bits located in the least ...

Page 105: ...ritical part which it cannot be interrupted CLI global interrupt enable and nested interrupt enabled continue the less critical BSET PULIPM PULIPM_R restore the old IPM value before leaving RTI then you can return A minimum overhead of six bus clock cycles is added inside an interrupt services routine to enable preemptive interrupts As an interrupt of the same priority level is allowed to pass thr...

Page 106: ...IRQMOD IRQF TO CPU FOR INSTRUCTIONS RESET BYPASS STOP STOP BUSCLK IRQPE IRQ 1 0 S IRQEDG SYNCHRO SYNCHRO NIZER NIZER IRQPDD WAKE UP INPUTS MODULES TO INTERNAL IRQACK BIL BIH To pullup enable logic for IRQ Figure 5 3 IRQ module block diagram External interrupts are managed by the IRQSC status and control register When the IRQ function is enabled synchronous logic monitors the pin for edge only or e...

Page 107: ... The internal gates connected to this pin are pulled all the way to VDD When enabling the IRQ pin for use the IRQF will be set and must be cleared prior to enabling the interrupt When configuring the pin for falling edge and level sensitivity in a 3 V system it is necessary to wait at least cycles between clearing the flag and enabling the interrupt 5 2 1 2 Edge and level sensitivity The IRQSC IRQ...

Page 108: ... set The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges When the IRQ pin is enabled as the IRQ input and is configured to detect rising edges the optional pullup resistor is disabled 0 IRQ is falling edge or falling edge low level sensitive 1 IRQ is rising edge or rising edge high level sensitive 4 IRQPE IRQ Pin Enable This read write control ...

Page 109: ...0 3F Interrupt Priority Mask Pseudo Stack Register IPC_IPMPS 8 R 00h 5 4 2 111 3050 Interrupt Level Setting Registers n IPC_ILRS0 8 R W 00h 5 4 3 111 3051 Interrupt Level Setting Registers n IPC_ILRS1 8 R W 00h 5 4 3 111 3052 Interrupt Level Setting Registers n IPC_ILRS2 8 R W 00h 5 4 3 111 3053 Interrupt Level Setting Registers n IPC_ILRS3 8 R W 00h 5 4 3 111 3054 Interrupt Level Setting Register...

Page 110: ...PMPS register is full It is automatically updated after each IPMPS register push or pull operation If additional interrupt is nested after this bit is set the earliest interrupt mask value IPM0 1 0 stacked in IPMPS will be lost 0 IPMPS register is not full 1 IPMPS register is full 3 PULIPM Pull IPM from IPMPS This bit pulls stacked IPM value from IPMPS register to IPM bits of IPCSC Zeros are shift...

Page 111: ...n is stored in IPM3 5 4 IPM2 Interrupt Priority Mask pseudo stack position 2 This field is the pseudo stack register for IPM2 The most recent information is stored in IPM2 3 2 IPM1 Interrupt Priority Mask pseudo stack position 1 This field is the pseudo stack register for IPM1 The most recent information is stored in IPM1 IPM0 Interrupt Priority Mask pseudo stack position 0 This field is the pseud...

Page 112: ... Source n 4 2 This field sets the interrupt level for interrupt source n 4 2 3 2 ILRn1 Interrupt Level Register for Source n 4 1 This field sets the interrupt level for interrupt source n 4 1 ILRn0 Interrupt Level Register for Source n 4 0 This field sets the interrupt level for interrupt source n 4 0 Interrupt priority control register MC9S08PA4 Reference Manual Rev 5 08 2017 112 NXP Semiconducto...

Page 113: ...l conditions During reset most control and status registers are forced to initial values and the program counter is loaded from the reset vector 0xFFFE 0xFFFF On chip peripheral modules are disabled and I O pins are initially configured as general purpose high impedance inputs with disabled pullup devices The CCR I bit is set to block maskable interrupts so that the user program has a chance to in...

Page 114: ... pin enable After POR PTA4 ACMPO BKGD MS pin functions as BKGD output The SYS_SOPT1 BKGDPE bit must be set to enable the background debug mode pin enable function When this bit is clear this pin can function as PTA4 or ACMP output 6 4 2 RESET pin enable After POR reset PTA5 IRQ FTM1CH0 RESET functions as RESET The SOPT1 RSTPE bit must be set to enable the reset functions When this bit is clear thi...

Page 115: ...system level logics for module to module interconnection for flexible configuration These interconnections provide the hardware trigger function between modules with least software configuration which is ideal for infrared communication serial communication baudrate detection low end motor control metering clock calibration and other general purpose applications SCI0 txd rxd FTM0 ch1 ch0 RTC ADC t...

Page 116: ...hannel 0 value register specifies the duty cycle of the PWM Then when TXDME bit is enabled each data transmitted via TXD0 from SCI0 is modulated by the FTM0 channel 0 output and the FTM0CH0 pin is released to other shared functions regardless of the configuration of FTM0 pin reassignment SCI0 TXDME FTM0CH0 PORT LOGIC PTB1 KBI0P5 TXD0 ADP5 TXD0 0 1 Figure 6 2 IR modulation diagram 6 5 3 SCI0 RxD ca...

Page 117: ...tions regardless of the configuration of SCI0 pin reassignment When SCI0 RxD capture function is active the ACMP output is injected to FTM0CH1 as well SCI0 0 1 RXDFE RXD0 To SCI0 RxD Capture Function From Internal or External Reference Voltage ACMP0 ACMP1 Figure 6 4 IR demodulation diagram 6 5 5 RTC capture RTC overflow may be captured by FTM1 channel 1 by setting SYS_SOPT2 RTCC bit When this bit ...

Page 118: ...hannel is selected as the ADC hardware trigger source because of the input pin is not controlled by FTM modules System Control Registers SYS memory map Absolute address hex Register name Width in bits Access Reset value Section page 3000 System Reset Status Register SYS_SRS 8 R 82h 6 6 1 119 3001 System Background Debug Force Reset Register SYS_SBDFR 8 W always reads 0 00h 6 6 2 121 3002 System De...

Page 119: ...SYS_SBDFR BDFR bit none of the status bits in SRS will be set The reset state of these bits depends on what caused the MCU to reset NOTE For PIN WDOG and ILOP any of these reset sources that are active at the time of reset not including POR or LVR will cause the corresponding bit s to be set bits corresponding to sources that are not active at the time of reset will be cleared NOTE The RESET value...

Page 120: ...sed by an illegal opcode 1 Reset caused by an illegal opcode 3 ILAD Illegal Address Reset was caused by an attempt to access a illegal address The illegal address is captured in illegal address register ILLAH ILLAL 0 Reset not caused by an illegal address 1 Reset caused by an illegal address 2 LOC Internal Clock Source Module Reset Reset was caused by an ICS module reset 0 Reset not caused by ICS ...

Page 121: ...kground command such as WRITE_BYTE may be used to allow an external debug host to force a target system reset Writing logic 1 to this bit forces an MCU reset This bit cannot be written from a user program NOTE BDFR is writable only through serial background debug commands not from user programs 6 6 3 System Device Identification Register High SYS_SDIDH This read only register together with SYS_SDI...

Page 122: ...its are located in a target MCU Address 3000h base 3h offset 3003h Bit 7 6 5 4 3 2 1 0 Read ID Write Reset 0 1 0 0 0 0 1 1 SYS_SDIDL field descriptions Field Description ID Part Identification Number These bits together with the SYS_SDIDH indicate part identification number Each derivative in the HCS08 family has a unique identification number This device is hard coded to the value 0x43 6 6 5 Syst...

Page 123: ...RESET pin functions as RESET When clear the pin functions as one of its alternative functions This pin defaults to RESET following an MCU POR Other resets will not affect this bit When RSTPE is set an internal pullup device on RESET is enabled 0 PTA5 IRQ TCLK0 RESET pin functions as PTA5 IRQ or TCLK0 1 PTA5 IRQ TCLK0 RESET pin functions as RESET 1 FWAKE Fast Wakeup Enable This write once bit can s...

Page 124: ... ACMP When this function is enabled any signal tagged with ACMP inputs can be regarded SCI0 0 RXD0 input signal is connected to SCI0 module directly 1 RXD0 input signal is filtered by ACMP then injected to SCI0 4 RXDCE SCI0 RxD Capture Select This bit enables the SCI0 RxD is captured by FTM0 channel 1 0 RXD0 input signal is connected to SCI0 module only 1 RXD0 input signal is connected to SCI0 mod...

Page 125: ...1 0 Read 0 FTMCHS 0 Write Reset 0 0 0 0 0 0 0 0 SYS_SOPT3 field descriptions Field Description 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 4 FTMCHS FTM Channel Select These bits select one channel from those of FTM0 and FTM1 to be used as the ADC hardware trigger source 00 FTM0 channel 0 is selected for the ADC hardware trigger 01 FTM0 channel ...

Page 126: ...ion ADDR 15 8 High 8 bit of illegal address NOTE For ILAD it reset to the high 8 bit of the illegal address in other cases the reset to values are undetermined 6 6 9 Illegal Address Register Low SYS_ILLAL The SYS_ILLAL is a read only register containing the low 8 bit of the illegal address of ILAD reset Address 3000h base 4Bh offset 304Bh Bit 7 6 5 4 3 2 1 0 Read ADDR 7 0 Write Reset x x x x x x x...

Page 127: ...0h base F8h offset 30F8h Bit 7 6 5 4 3 2 1 0 Read ID 63 56 Write Reset x x x x x x x x Notes x Undefined at reset SYS_UUID1 field descriptions Field Description ID 63 56 Universally Unique Identifier 6 6 11 Universally Unique Identifier Register 2 SYS_UUID2 The read only SYS_UUIDx registers contain a series of 63 bit number to identify the unique device in the family Address 3000h base F9h offset ...

Page 128: ...ined at reset SYS_UUID3 field descriptions Field Description ID 47 40 Universally Unique Identifier 6 6 13 Universally Unique Identifier Register 4 SYS_UUID4 The read only SYS_UUIDx registers contain a series of 63 bit number to identify the unique device in the family Address 3000h base FBh offset 30FBh Bit 7 6 5 4 3 2 1 0 Read ID 39 32 Write Reset x x x x x x x x Notes x Undefined at reset SYS_U...

Page 129: ...Field Description ID 31 24 Universally Unique Identifier 6 6 15 Universally Unique Identifier Register 6 SYS_UUID6 The read only SYS_UUIDx registers contain a series of 64 bit number to identify the unique device in the family Address 3000h base FDh offset 30FDh Bit 7 6 5 4 3 2 1 0 Read ID 23 16 Write Reset x x x x x x x x Notes x Undefined at reset SYS_UUID6 field descriptions Field Description I...

Page 130: ...s Field Description ID 15 8 Universally Unique Identifier 6 6 17 Universally Unique Identifier Register 8 SYS_UUID8 The read only SYS_UUIDx registers contain a series of 64 bit number to identify the unique device in the family Address 3000h base FFh offset 30FFh Bit 7 6 5 4 3 2 1 0 Read ID 7 0 Write Reset x x x x x x x x Notes x Undefined at reset SYS_UUID8 field descriptions Field Description ID...

Page 131: ...ns are disabled After reset the shared peripheral functions are disabled so that the pins are controlled by the parallel I O except PTA4 and PTA5 that are default to BKGD MS and RESET function All of the parallel I O are configured as high impedance Hi Z The pin control functions for each pin are configured as follows input disabled PTxIEn 0 output disabled PTxOEn 0 and internal pullups disabled P...

Page 132: ...xIEn PTxDn CPU read PTxDn Figure 7 1 Normal I O structure 1 0 PTxPEn PTxOEn PTxIEn PTxDn CPU read PTxDn HDRVE Figure 7 2 High drive I O structure Introduction MC9S08PA4 Reference Manual Rev 5 08 2017 132 NXP Semiconductors ...

Page 133: ...tem has overriding control of the actual pin direction When a shared analog function is enabled for a pin all digital pin functions are disabled A read of the port data register returns a value of 0 for any bits that have shared analog functions enabled In general whenever a pin is shared with both an alternate digital function and an analog function the analog function has priority such that if b...

Page 134: ...B4 Output high sink source current when they are operated as output High current drive function is disabled if the pin is configured as an input by the parallel I O control logic When configured as any shared peripheral function high current drive function still works on these pins but only when they are configured as outputs 7 6 Pin behavior in stop mode In stop3 mode all I O is maintained becaus...

Page 135: ...ble Register PORT_PTCPE 8 R W 00h 7 7 16 148 7 7 1 Port A Data Register PORT_PTAD Address 0h base 0h offset 0h Bit 7 6 5 4 3 2 1 0 Read 0 PTAD Write Reset 0 0 0 0 0 0 0 0 PORT_PTAD field descriptions Field Description 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 PTAD Port A Data Register Bits For port A pins that are configured as inputs a read re...

Page 136: ... disabled 7 7 3 Port C Data Register PORT_PTCD Address 0h base 2h offset 2h Bit 7 6 5 4 3 2 1 0 Read 0 PTCD Write Reset 0 0 0 0 0 0 0 0 PORT_PTCD field descriptions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 PTCD Port C Data Register Bits For port C pins that are configured as inputs a read returns the logic level on the pin Fo...

Page 137: ... 0 PTB4 is disabled to offer high current drive capability 1 PTB4 is enable to offer high current drive capability 7 7 5 Port A Output Enable Register PORT_PTAOE Address 0h base 30B0h offset 30B0h Bit 7 6 5 4 3 2 1 0 Read 0 PTAOE5 PTAOE4 PTAOE3 PTAOE2 PTAOE1 PTAOE0 Write Reset 0 0 0 0 0 0 0 0 PORT_PTAOE field descriptions Field Description 7 6 Reserved This field is reserved This read only field i...

Page 138: ... output 0 Output Disabled for port A bit 1 1 Output Enabled for port A bit 1 0 PTAOE0 Output Enable for Port A Bit 0 This read write bit enables the port A pin as an output 0 Output Disabled for port A bit 0 1 Output Enabled for port A bit 0 7 7 6 Port B Output Enable Register PORT_PTBOE Address 0h base 30B1h offset 30B1h Bit 7 6 5 4 3 2 1 0 Read PTBOE7 PTBOE6 PTBOE5 PTBOE4 PTBOE3 PTBOE2 PTBOE1 PT...

Page 139: ...t Disabled for port B bit 3 1 Output Enabled for port B bit 3 2 PTBOE2 Output Enable for Port B Bit 2 This read write bit enables the port B pin as an output 0 Output Disabled for port B bit 2 1 Output Enabled for port B bit 2 1 PTBOE1 Output Enable for Port B Bit 1 This read write bit enables the port B pin as an output 0 Output Disabled for port B bit 1 1 Output Enabled for port B bit 1 0 PTBOE0...

Page 140: ... bit 1 1 Output Enabled for port C bit 1 0 PTCOE0 Output Enable for Port C Bit 0 This read write bit enables the port C pin as an output 0 Output Disabled for port C bit 0 1 Output Enabled for port C bit 0 7 7 8 Port A Input Enable Register PORT_PTAIE Address 0h base 30B8h offset 30B8h Bit 7 6 5 4 3 2 1 0 Read 0 PTAIE5 0 PTAIE3 PTAIE2 PTAIE1 PTAIE0 Write Reset 0 0 0 0 0 0 0 0 PORT_PTAIE field desc...

Page 141: ...t enabled for port A bit 1 0 PTAIE0 Input Enable for Port A Bit 0 This read write bit enables the port A pin as an input 0 Input disabled for port A bit 0 1 Input enabled for port A bit 0 7 7 9 Port B Input Enable Register PORT_PTBIE Address 0h base 30B9h offset 30B9h Bit 7 6 5 4 3 2 1 0 Read PTBIE7 PTBIE6 PTBIE5 PTBIE4 PTBIE3 PTBIE2 PTBIE1 PTBIE0 Write Reset 0 0 0 0 0 0 0 0 PORT_PTBIE field descr...

Page 142: ...bit 3 1 Input enabled for port B bit 3 2 PTBIE2 Input Enable for Port B Bit 2 This read write bit enables the port B pin as an input 0 Input disabled for port B bit 2 1 Input enabled for port B bit 2 1 PTBIE1 Input Enable for Port B Bit 1 This read write bit enables the port B pin as an input 0 Input disabled for port B bit 1 1 Input enabled for port B bit 1 0 PTBIE0 Input Enable for Port B Bit 0 ...

Page 143: ...ut disabled for port C bit 1 1 Input enabled for port C bit 1 0 PTCIE0 Input Enable for Port C Bit 0 This read write bit enables the port C pin as an input 0 Input disabled for port C bit 0 1 Input enabled for port C bit 0 7 7 11 Port Filter Register 0 PORT_IOFLT0 This register sets the filters for input from PTA to PTD Address 0h base 30ECh offset 30ECh Bit 7 6 5 4 3 2 1 0 Read 0 FLTC FLTB FLTA W...

Page 144: ...LT2 field descriptions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 2 FLTKBI0 Filter selection for input from KBI0 00 BUSCLK 01 Select FLTDIV1 and will switch to FLTDIV3 in stop mode automatically 10 Select FLTDIV2 and will switch to FLTDIV3 in stop mode automatically 11 FLTDIV3 FLTRST Filter selection for input from RESET IRQ ...

Page 145: ...0 0 0 0 PORT_FCLKDIV field descriptions Field Description 7 5 FLTDIV3 Filter Division Set 3 Port Filter Division Set 3 000 LPOCLK 001 LPOCLK 2 010 LPOCLK 4 011 LPOCLK 8 100 LPOCLK 16 101 LPOCLK 32 110 LPOCLK 64 111 LPOCLK 128 4 2 FLTDIV2 Filter Division Set 2 Port Filter Division Set 2 000 BUSCLK 32 001 BUSCLK 64 010 BUSCLK 128 011 BUSCLK 256 100 BUSCLK 512 101 BUSCLK 1024 110 BUSCLK 2048 111 BUSC...

Page 146: ...onfigured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port A bit 3 1 Pullup enabled for port A bit 3 2 PTAPE2 Pull Enable for Port A Bit 2 This control bit determines if the internal pullup device is enabled for the associated PTA pin For port A pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port A bit 2 1 Pullup enabled for port ...

Page 147: ...TB pin For port B pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port B bit 5 1 Pullup enabled for port B bit 5 4 PTBPE4 Pull Enable for Port B Bit 4 This control bit determines if the internal pullup device is enabled for the associated PTB pin For port B pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port B...

Page 148: ...ions Field Description 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 PTCPE3 Pull Enable for Port C Bit 3 This control bit determines if the internal pullup device is enabled for the associated PTC pin For port C pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port C bit 3 1 Pullup enabled for port C bit...

Page 149: ...Port C Bit 0 This control bit determines if the internal pullup device is enabled for the associated PTC pin For port C pins that are configured as outputs or Hi Z these bits have no effect 0 Pullup disabled for port C bit 0 1 Pullup enabled for port C bit 0 Chapter 7 Parallel input output MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semiconductors 149 ...

Page 150: ...Port data registers MC9S08PA4 Reference Manual Rev 5 08 2017 150 NXP Semiconductors ...

Page 151: ... which allows a lower output clock frequency to be derived The external oscillator XOSC module allows an external crystal ceramic resonator or other external clock source to produce the external reference clock The output of XOSC module can be used as the reference of ICS to generate system bus clock and or clock source of watchdog WDOG real time counter RTC and analog to digital ADC modules The l...

Page 152: ...C MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only pin when used as port pin 3 PTB4 and PTB5 can provide high sink source current drive 2 CH FLEX TIMER MODULE FTM0 KEYBOARD INTERRUPT MODULE KBI0 2 CH FLEX TIMER MODULE FTM1 2 CH FLEX TIME...

Page 153: ...s the clock source for the MCU Whichever clock is selected as the source can be divided down by 1 2 4 8 16 32 64 or 128 FLL Engaged Internal mode is automatically selected out of reset A constant divide by 2 of the DCO output that can be select as BDC clock Digitally controlled oscillator DCO optimized for 16 MHz to 20 MHz frequency range FLL lock detector and external clock monitor FLL lock detec...

Page 154: ...ICS_C2 LP is provided to allow the FLL to be disabled and thus conserve power when it is not used However in some applications it may be desirable to allow the FLL to be enabled and to lock for maximum accuracy before switching to an FLL engaged mode To do this write the ICS_C2 LP bit to 0 8 2 1 3 Internal reference clock ICSIRCLK When ICS_C1 IRCLKEN is set the internal reference clock signal is p...

Page 155: ...essed by users This value is uploaded to the ICS_C3 register and ICS_C4 register during any reset initialization For finer precision trim the internal oscillator in the application and set the ICS_C4 SCFTRIM bit accordingly NOTE Some tools like ProcessorExpert or USB Multilink may use flash memory location such as 0xFF6F and or 0xFF6E to store the temporary trim value 8 2 1 4 Fixed frequency clock...

Page 156: ... FLL bypassed internal low power FBILP and FLL bypassed external low power FBELP modes The ICSLCLK can be selected as BDC clock 8 2 2 Modes of operation There are seven modes of operation for the ICS FEI FEE FBI FBILP FBE FBELP and stop The following figure shows the seven states of the ICS as a state diagram The arrows indicate the allowed movements between the states Internal clock source ICS MC...

Page 157: ...e changed at anytime but the actual switch to the newly selected clock is shown by the ICS_S IREFST bit When switching between FLL engaged internal FEI and FLL engaged external FEE modes the FLL will lock again after the switch is completed The ICS_C1 CLKS bits can also be changed at anytime but the actual switch to the newly selected clock is shown by the ICS_S CLKST bits If the newly selected cl...

Page 158: ...ternal reference clock source The FLL loop locks the frequency to the 512 times the external reference frequency as selected by the ICS_C1 RDIV bits The ICSLCLK is available for BDC communications and the external reference clock is enabled 8 2 2 3 FLL bypassed internal FBI The FLL bypassed internal FBI mode is entered when all of the following conditions occur ICS_C1 CLKS bits are written to 01 I...

Page 159: ...S_C1 IREFS bit is written to 0 ICS_C1 RDIV bits are written to divide external reference clock to be within the range of 31 25 kHz to 39 0625 kHz BDM mode is active or ICS_C2 LP bit is written to 0 In FLL bypassed external mode the ICSOUT clock is derived from the external reference clock source The FLL clock is controlled by the external reference clock and the FLL loop locks the FLL frequency to...

Page 160: ...never the MCU enters a stop state In this mode all ICS clock signals are static except in the following cases ICSIRCLK will be active in stop mode when all of the following conditions occur ICS_C1 IRCLKEN bit is written to 1 ICS_C1 IREFSTEN bit is written to 1 OSCOUT will be active in stop mode when all of the following conditions occur ICS_OSCSC OSCEN bit is written to 1 ICS_OSCSC OSCSTEN bit is ...

Page 161: ...modes the FLL is not on therefore lock detect function is not applicable 8 2 3 2 External reference clock monitor In FBE FEE FEI or FBI modes if ICS_C4 CME bit is written to 1 the clock monitor is enabled If the external reference falls below a certain frequency such as floc_high or floc_low depending on the ICS_OSCSC RANGE bit the MCU will reset The SYS_SRS CLK bit will be set to indicate the err...

Page 162: ... 32 ICS_C3 TRIM_VALUE_31K25HZ FLL output 16MHz TRIM_VALUE_31K25HZ is 0x90 typically 8 3 2 Initializing FBI mode The following code segment demonstrates setting ICS to FBI mode Example 8 3 2 1 FBI mode initialization routine the following code segment demonstrates setting ICS to FBI mode generating 32768Hz bus ICS_C2 0x00 ICS_C1 0x40 ICS_C2 0x00 ICS_C3 TRIM_VALUE_32K768HZ TRIM_VALUE_31K25HZ is 0x90...

Page 163: ... waiting until oscillator is ready ICS_C1 0x80 external clock reference 20MHZ to FLL output ICS_C2 0x00 BDIV 0 prescalar 1 8 3 5 External oscillator OSC The oscillator module provides the reference clock for internal reference clock module ICS the real time counter clock module and other MCU sub systems OSCOUT OSCINIT High Gain Oscillator MCU EXTAL XTAL Rs RF C1 C2 X1 EN XTLCLK Initialization Osci...

Page 164: ...l clock module is disabled EXTAL can be used as the input of external clock source When external clock source is not used in this mode the EXTAL can be used as GPIO or other function muxed with this pinout XTAL can be used as GPIO or other function muxed with its pinout even EXTAL is used as external clock source The following figure shows the typical OSC bypass mode connection MCU EXTAL GPIO XTAL...

Page 165: ... be carefully selected to get best performance The following figure shows the typical OSC high gain mode connection MCU EXTAL XTAL RS C1 C2 X1 RF Figure 8 7 OSC high gain mode connection 8 3 5 4 Initializing external oscillator for peripherals The following code segment demonstrates initializing external oscillator Example 8 3 5 4 1 External oscillator initialization routine Chapter 8 Clock manage...

Page 166: ...e thereby reducing the overall run and wait mode currents Out of reset all peripheral clocks will be enabled For lowest possible run wait currents user software should disable the clock source to any peripheral not in use The actual clock will be enabled or disabled immediately following the write to the Clock Gating Control registers SCG_Cx Any peripheral with a gated clock cannot be used unless ...

Page 167: ... Reset 0 0 0 0 0 1 0 0 ICS_C1 field descriptions Field Description 7 6 CLKS Clock Source Select Selects the clock source that controls the bus frequency The actual bus frequency depends on the value of the BDIV bits 00 Output of FLL is selected 01 Internal reference clock is selected 10 External reference clock is selected 11 Reserved 5 3 RDIV Reference Divider Selects the amount to divide down th...

Page 168: ...t or if ICS is in FEI FBI or FBILP mode before entering stop 1 Reset default 8 6 2 ICS Control Register 2 ICS_C2 Address 3038h base 1h offset 3039h Bit 7 6 5 4 3 2 1 0 Read BDIV LP 0 Write Reset 0 0 1 0 0 0 0 0 ICS_C2 field descriptions Field Description 7 5 BDIV Bus Frequency Divider Selects the amount to divide down the clock source selected by the CLKS bits This controls the bus frequency 000 E...

Page 169: ...ernal reference clock frequency by controlling the internal reference clock period The bits are binary weighted In other words bit 1 adjusts twice as much as bit 0 Increasing the binary value in SCTRIM will increase the period and decreasing the value will decrease the period An additional fine trim bit is available in ICSC4 as the SCFTRIM bit 8 6 4 ICS Control Register 4 ICS_C4 Address 3038h base...

Page 170: ...t in any BDM mode 8 6 5 ICS Status Register ICS_S Address 3038h base 4h offset 303Ch Bit 7 6 5 4 3 2 1 0 Read LOLS LOCK 0 IREFST CLKST 0 Write Reset 0 0 0 1 0 0 0 0 ICS_S field descriptions Field Description 7 LOLS Loss of Lock Status This bit is a sticky indication of lock status for the FLL LOLS is set when lock detection is enabled and after acquiring lock the FLL output frequency has fallen ou...

Page 171: ...l clock 1 Source of reference clock is internal clock 3 2 CLKST Clock Mode Status The CLKST bits indicate the current clock mode The CLKST bits don t update immediately after a write to the CLKS bits due to internal synchronization between clock domains 00 Output of FLL is selected 01 FLL Bypassed internal reference clock is selected 10 FLL Bypassed external reference clock is selected 11 Reserved...

Page 172: ...he frequency range for the OSC module 0 Low frequency range of 31 25kHz 39 0625kHz 1 High frequency range of 4 20MHz 1 HGO High Gain Oscillator Select The HGO bit controls the OSC mode of operation 0 Low gain mode 1 High gain mode 0 OSCINIT OSC Initialization This bit set after the initialization cycles of oscillator completes 0 Oscillator initialization not completes 1 Oscillator initialization c...

Page 173: ...e Control This bit controls the clock gate to the FTM2 module 0 Bus clock to the FTM2 module is disabled 1 Bus clock to the FTM2 module is enabled 6 FTM1 FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module 0 Bus clock to the FTM1 module is disabled 1 Bus clock to the FTM1 module is enabled 5 FTM0 FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module 0 ...

Page 174: ...Field Description 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 DBG DBG Clock Gate Control This bit controls the clock gate to the DBG module 0 Bus clock to the DBG module is disabled 1 Bus clock to the DBG module is enabled 4 NVM NVM Clock Gate Control This bit controls the clock gate to the NVM module 0 Bus clock to the NVM module is disabled 1...

Page 175: ...reserved and always has the value 0 4 SCI0 SCI0 Clock Gate Control This bit controls the clock gate to the SCI0 module 0 Bus clock to the SCI0 module is disabled 1 Bus clock to the SCI0 module is enabled Reserved This field is reserved This read only field is reserved and always has the value 0 8 7 4 System Clock Gating Control 4 Register SCG_C4 This high page register contains control bits to ena...

Page 176: ...us clock to the ADC module is disabled 1 Bus clock to the ADC module is enabled 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 IRQ IRQ Clock Gate Control This bit controls the clock gate to the IRQ module 0 Bus clock to the IRQ module is disabled 1 Bus clock to the IRQ module is enabled 2 1 Reserved This field is reserved This read only field is res...

Page 177: ...veral instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers 9 2 2 Debug module DBG The DBG module implements an on chip ICE in circuit emulation system and allows non intrusive debug of application software by providing an on chip trace buffer with flexi...

Page 178: ...er an internal or external reference clock The module can select clock from the FLL or bypass the FLL as a source of the MCU system clock The selected clock source is passed through a reduced bus divider which allows a lower output clock frequency to be derived The external oscillator XOSC module allows an external crystal ceramic resonator or other external clock source to produce the external re...

Page 179: ...BI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTB2 KBI0P6 ADP6 PTB3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only pin when us...

Page 180: ...e storage of program and constant The EEPROM is used for storing frequently modified non volatile data Non volatile memory NVM includes Flash memory 4 096 bytes 8 sectors of 512 bytes EEPROM memory 128 bytes 64 sectors of 2 bytes 9 6 Power modules This device contains on chip regulator for various operational power modes of run wait and stop3 modes The low voltage detect LVD system allows the syst...

Page 181: ...ible to the TPM FTM2 has no pin out Each FTM module has independent external clock input The following table summarizes the external signals of FTM modules Table 9 1 FTM module external signals FTM Functions Default Alternate FTM0 channel 0 PTA0 FTM0CH0 PTA2 FTM0CH0 channel 1 PTA1 FTM0CH1 PTA3 FTM0CH1 alternate clock PTB0 TCLK0 FTM1 channel 0 PTB4 FTM1CH0 PTA5 FTM1CH0 channel 1 PTB5 FTM1CH1 altern...

Page 182: ...LK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes KEYBOARD INTERRUPT MC9S08PA4 512 bytes MODULE KBI0 2 CH FLEX TIMER MODULE FTM1 ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only pin when used as port pin 3 P...

Page 183: ...er one 16 bit comparator several binary based and decimal based prescaler dividers two clock sources and one programmable periodic interrupt This module can be used for time of day calendar or any task scheduling functions It can also serve as a cyclic wakeup from low power modes without external components RTC overflow trigger can be used as hardware trigger for ADC module Furthermore when the tr...

Page 184: ... RESET PTB0 KBI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTB2 KBI0P6 ADP6 PTB3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only ...

Page 185: ...d Transmit and receive within the same SCI use a common baud rate and each SCI module has a separate baud rate generator This SCI system offers many advanced features not commonly found on other asynchronous serial I O peripherals of the embedded controllers The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection Hardware parity receiver wak...

Page 186: ...K1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only pin when used as port pin 3 PTB4 and PTB5 can provide high sink source current drive 2 2 ...

Page 187: ...C This device contains an analog to digital converter ADC of 12 bit a successive approximation ADC for operation within an integrated microcontroller system on chip The ADC channel assignments alternate clock function and hardware trigger function are configured as described following sections The following figure shows device block diagram highlighting ADC module and pins 9 9 Chapter 9 Chip confi...

Page 188: ...3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 2 PTB0 operates as true open drain when working as output 1 PTA4 ACMPO BKGD MS is an output only pin when used as port pin 3 PTB4 and PTB5 can provide high sink source curr...

Page 189: ...S 01100 AD12 VSS 01101 AD13 VSS 01110 AD14 VSS 01111 AD15 VSS 10000 AD16 VSS 10001 AD17 VSS 10010 AD18 VSS 10011 AD19 Reserved 10100 AD20 Reserved 10101 AD21 Reserved 10110 AD22 Temperature sensor 10111 AD23 Bandgap 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Reserved 11011 AD27 Reserved 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Chapter 9 Chip configur...

Page 190: ...n clock source while the MCU is in stop3 mode 9 9 1 3 Hardware trigger The ADC hardware trigger is selectable from RTC overflow the ACMP output the FTM output The MCU can be configured to use any of those four hardware trigger sources in run and wait modes The RTC overflow can be used as ADC hardware trigger in STOP3 mode Please refer to ADC hardware trigger 9 9 1 4 Temperature sensor The ADC modu...

Page 191: ...or both hot and cold In application code you can calculate the temperature as detailed above and determine if it is above or below 25 C After you have determined whether the temperature is above or below 25 C you can recalculate the temperature using the hot or cold slope value obtained during calibration 9 9 2 Analog comparator ACMP The analog comparator module ACMP provides a circuit for compari...

Page 192: ...0 ADP3 PTA4 ACMPO BKGD MS PTA5 IRQ FTM1CH0 RESET PTB0 KBI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTB2 KBI0P6 ADP6 PTB3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes MC9S08PA4 512 bytes ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 2 PTB0 operates as true open drain when working as ou...

Page 193: ...continues to operate in stop3 mode if enabled If ACMP_SC ACOPE is enabled comparator output will operate as in the normal operating mode and will control ACMPO pin The MCU is brought out of stop when a compare event occurs and ACMP_SC ACIE is enabled ACF flag sets accordingly 9 9 2 3 ACMP to FTM configuration information The ACMP module can be configured to connect the output of the analog compara...

Page 194: ...es with up to 8 keyboard interrupt inputs grouped in a KBI modules available depending on packages The following figure shows the device block diagram with the KBI modules and pins highlighted 9 10 Human machine interfaces HMI MC9S08PA4 Reference Manual Rev 5 08 2017 194 NXP Semiconductors ...

Page 195: ...MS PTA5 IRQ FTM1CH0 RESET PTB0 KBI0P4 RxD0 TCLK0 ADP4 PTB1 KBI0P5 TxD0 ADP5 PTB2 KBI0P6 ADP6 PTB3 KBI0P7 TCLK1 ADP7 PTB4 FTM1CH03 PTB5 FTM1CH13 PTB6 XTAL PTB7 EXTAL PTC0 PTC1 PTC2 PTC3 USER RAM CONTROLLER PMC MC9S08PA4 128 bytes USER FLASH MC9S08PA4 4 096 bytes KEYBOARD INTERRUPT MC9S08PA4 512 bytes MODULE KBI0 2 CH FLEX TIMER MODULE FTM1 ANALOG COMPARATOR ACMP CONTROLLER IPC 1 2 PTB0 operates as ...

Page 196: ...Human machine interfaces HMI MC9S08PA4 Reference Manual Rev 5 08 2017 196 NXP Semiconductors ...

Page 197: ... with M68HC05 and M68HC08 families 16 bit stack pointer any size stack anywhere in 64 KB CPU address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instructions treat X as a second general purpose 8 bit register Seven addressing modes Inherent Operands in internal registers Relative 8 bit signed offset to branch destination Immediate Operand in next...

Page 198: ...s the five CPU registers CPU registers are not part of the memory map SP PC CARRY ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 ACCUMULATOR A INDEX REGISTER X INDEX REGISTER H STACK POINTER PROGRAM COUNTER CCR C V 1 1 H I N Z TWO S COMPLEMENT OVERFLOW 0 7 0 0 15 15 0 15 CONDITION CODE REGISTER 16 BIT INDEX REGISTER H X 7 8 0 7 Figure 10 1 CPU Registers 10 2 1 Accumulator A The A accumulator i...

Page 199: ... with the earlier M68HC05 family H is forced to 0x00 during reset Reset has no effect on the contents of X 10 2 3 Stack Pointer SP This 16 bit address pointer register points at the next available location on the automatic last in first out LIFO stack The stack may be located anywhere in the 64 KB address space that has RAM and can be any size up to the amount of available RAM The stack is used to...

Page 200: ...ranch instructions BGT BGE BLE and BLT use the overflow flag 0 No overflow 1 Overflow 4 H Half Carry Flag The CPU sets the half carry flag when a carry occurs between accumulator bits 3 and 4 during an add without carry ADD or add with carry ADC operation The half carry flag is required for binary coded decimal BCD arithmetic operations The DAA instruction uses the states of the H and C condition ...

Page 201: ...In the HCS08 V6 memory status and control registers and input output I O ports share a single 64 KB CPU address space This arrangement means that the same instructions that access variables in RAM can also be used to access I O and control registers or nonvolatile program space Some instructions use more than one addressing mode For instance move instructions use one addressing mode to specify the...

Page 202: ...nd is added to the current contents of the program counter which causes program execution to continue at the branch destination address If a branch condition is false the CPU executes the next instruction 10 3 3 Immediate Addressing Mode IMM The operand for instructions with the immediate addressing mode is contained in the byte s immediately following the opcode The byte or bytes that follow the ...

Page 203: ...address is assumed to be zero During execution the CPU combines the value 55 from the instruction with the assumed value of 00 to form the address 0055 which is then used to access the data to be loaded into accumulator LDHX 20 In this example the value 20 is combined with the assumed value of 00 to form the address 0020 Since the LDHX instruction requires a 16 bit value a 16 bit word of data is r...

Page 204: ...6 2 Indexed No Offset with Post Increment IX Instructions using the indexed no offset with post increment addressing mode are two byte instructions that address the operands and then increment the Index register H X The X Index register low byte register contains the low byte of the conditional address of the operand and the H Index register high byte register contains the high byte of the address...

Page 205: ...the most significant byte of the 16 bit offset the second byte is the least significant byte of the 16 bit offset As with direct and extended addressing most assemblers determine the shortest form of indexed addressing Indexed 16 bit offset instructions are useful in selecting the k th element in an n element table The table can begin anywhere and can extend as far as the address map allows The k ...

Page 206: ...g the k th element a an n element table The table can begin anywhere and can extend anywhere in memory The k value would typically be in the stack pointer register and the address of the beginning of the table is located in the two bytes following the two byte opcode 10 3 7 Memory to memory Addressing Mode Memory to memory addressing mode has the following four variations 10 3 7 1 Direct to Direct...

Page 207: ...ntrol the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing Unlike the earlier M68HC05 and M68HC08 MCUs the HCS08 V6 can be configured to keep a minimum set of clocks running in stop mode This optionally allows an internal periodic signal to wake the target MCU from stop mode When a host debug system is connected to the background debug pi...

Page 208: ...CPU is in either stop or wait mode The BACKGROUND command can be used to wake the CPU from wait mode and enter active background mode 10 4 3 Background mode Background instruction BGND is not used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode waiting for serial background commands The only way to resume execution of the ...

Page 209: ...ound mode to return to the user s application program GO The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time The active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed 10 4 4 Security mode Usually HCS08 V6 MCUs a...

Page 210: ... blocked during the stacking cycles of interrupt service routines 6 Data accesses to either secure or non secure memory are allowed when the current instruction is tagged as secure 7 BDC accesses to non secure memory are allowed When the device is in the non secure mode secure memory is treated the same as non secure memory and all accesses are allowed Table 10 2 details the security conditions fo...

Page 211: ...uded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted At the conclusion of a reset event the CPU performs a 6 cycle sequence to fetch the reset vector from FFFE and FFFF and to fill the instruction queue in preparation for execution of the first program instruction 10 6 2 Interrupt Sequence When an interrupt is reque...

Page 212: ... stack as part of the interrupt sequence The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt service routine It is not necessary to save H if you are certain that the interrupt service routine does not use any instructions or auto increment addressing modes that might change the value of ...

Page 213: ...o a 16 bit value IMM AF ii 2 AND opr8i 0 IMM A4 ii 2 AND opr8a 0 DIR B4 dd 3 AND opr16a 0 EXT C4 hh ll 4 AND oprx16 X 0 IX2 D4 ee ff 4 AND oprx8 X Logical AND A A M 0 IX1 E4 ff 3 AND X 0 IX F4 3 AND oprx16 SP 0 SP2 9ED4 ee ff 5 AND oprx8 SP 0 SP1 9EE4 ff 4 ASL opr8a DIR 38 dd 5 ASLA INH 48 1 ASLX INH 58 1 ASL oprx8 X Arithmetic Shift Left same as LSL C MSB LSB 0 IX1 68 ff 5 ASL X IX 78 4 ASL oprx8...

Page 214: ...if Greater Than Signed Operands Branch if Z N V 0 REL 92 rr 3 BHCC rel Branch if Half Carry Bit Clear Branch if H 0 REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set Branch if H 1 REL 29 rr 3 BHI rel Branch if Higher Branch if C Z 0 REL 22 rr 3 BHS rel Branch if Higher or Same same as BCC Branch if C 0 REL 24 rr 3 BIH rel Branch if IRQ Pin High Branch if IRQ pin 1 REL 2F rr 3 BIL rel Branch if IRQ...

Page 215: ...2D rr 3 BNE rel Branch if Not Equal Branch if Z 0 REL 26 rr 3 BPL rel Branch if Plus Branch if N 0 REL 2A rr 3 BRA rel Branch Always No Test REL 20 rr 3 DIR b0 01 dd rr 5 DIR b1 03 dd rr 5 DIR b2 05 dd rr 5 DIR b3 07 dd rr 5 BRCLR n opr8a rel Branch if Bit n in Memory Clear Branch if Mn 0 DIR b4 09 dd rr 5 DIR b5 0B dd rr 5 DIR b6 0D dd rr 5 DIR b7 0F dd rr 5 BRN rel Branch Never Uses 3 Bus Cycles...

Page 216: ... 61 ff rr 5 CBEQ X rel Branch if A M IX 71 rr 5 CBEQ oprx8 SP rel Branch if A M SP1 9E61 ff rr 6 CLC Clear Carry Bit C 0 0 INH 98 1 CLI Clear Interrupt Mask Bit I 0 0 INH 9A 1 CLR opr8a M 0x00 0 0 1 DIR 3F dd 5 CLRA A 0x00 0 0 1 INH 4F 1 CLRX X 0x00 0 0 1 INH 5F 1 CLRH Clear H 0x00 0 0 1 INH 8C 1 CLR oprx8 X M 0x00 0 0 1 IX1 6F ff 5 CLR X M 0x00 0 0 1 IX 7F 4 CLR oprx8 SP M 0x00 0 0 1 SP1 9E6F ff ...

Page 217: ...IMM A3 ii 2 CPX opr8a DIR B3 dd 3 CPX opr16a EXT C3 hh ll 4 CPX oprx16 X Compare X Index Register Low with Memory X M CCR Updated But Operands Not Changed IX2 D3 ee ff 4 CPX oprx8 X IX1 E3 ff 3 CPX X IX F3 3 CPX oprx16 SP SP2 9ED3 ee ff 5 CPX oprx8 SP SP1 9EE3 ff 4 DAA Decimal Adjust Accumulator After ADD or ADC of BCD Values A 10 U INH 72 1 DBNZ opr8a rel DIR 3B dd rr 7 DBNZA rel INH 4B rr 4 DBNZ...

Page 218: ...A A 0x01 INH 4C 1 INCX X X 0x01 INH 5C 1 INC oprx8 X Increment M M 0x01 IX1 6C ff 5 INC X M M 0x01 IX 7C 4 INC oprx8 SP M M 0x01 SP1 9E6C ff 6 JMP opr8a DIR BC dd 3 JMP opr16a EXT CC hh ll 4 JMP oprx16 X Jump PC Jump Address IX2 DC ee ff 4 JMP oprx8 X IX1 EC ff 3 JMP X IX FC 3 JSR opr8a DIR BD dd 5 JSR opr16a PC PC n n 1 2 or 3 Push PCL EXT CD hh ll 6 JSR oprx16 X Jump to Subroutine SP SP 0x0001 P...

Page 219: ... CE hh ll 4 LDX oprx16 X 0 IX2 DE ee ff 4 LDX oprx8 X Load X Index Register Low from Memory X M 0 IX1 EE ff 3 LDX X 0 IX FE 3 LDX oprx16 SP 0 SP2 9EDE ee ff 5 LDX oprx8 SP 0 SP1 9EEE ff 4 LSL opr8a DIR 38 dd 5 LSLA INH 48 1 LSLX INH 58 1 LSL oprx8 X Logical Shift Left Same as ASL C MSB LSB 0 IX1 68 ff 5 LSL X IX 78 4 LSL oprx8 SP SP1 9E68 ff 6 LSR opr8a 0 DIR 34 dd 5 LSRA 0 INH 44 1 LSRX 0 INH 54 ...

Page 220: ...MM AA ii 2 ORA opr8a 0 DIR BA dd 3 ORA opr16a 0 EXT CA hh ll 4 ORA oprx16 X 0 IX2 DA ee ff 4 ORA oprx8 X Inclusive OR Accumulator and Memory A A M 0 IX1 EA ff 3 ORA X 0 IX FA 3 ORA oprx16 SP 0 SP2 9EDA ee ff 5 ORA oprx8 SP 0 SP1 9EEA ff 4 PSHA Push Accumulator onto Stack Push A SP SP 0x0001 INH 87 2 PSHH Push H Index Register High onto Stack Push H SP SP 0x0001 INH 8B 2 PSHX Push X Index Register ...

Page 221: ...fected INH 9C 1 SP SP 0x0001 Pull CCR SP SP 0x0001 Pull A RTI Return from Interrupt SP SP 0x0001 Pull X INH 80 9 SP SP 0x0001 Pull PCH SP SP 0x0001 Pull PCL SP SP 0x0001 Pull PCH RTS Return from Subroutine INH 81 6 SP SP 0x0001 Pull PCL SBC opr8i IMM A2 ii 2 SBC opr8a DIR B2 dd 3 SBC opr16a EXT C2 hh ll 4 SBC oprx16 X IX2 D2 ee ff 4 SBC oprx8 X Subtract with Carry A A M C IX1 E2 ff 3 SBC X IX F2 3...

Page 222: ...sing Refer to MCU Documentation I bit 0 Stop Processing 0 INH 8E 3 STX opr8a 0 DIR BF dd 3 STX opr16a 0 EXT CF hh ll 4 STX oprx16 X 0 IX2 DF ee ff 4 STX oprx8 X 0 IX1 EF ff 3 STX X Store X Low 8 Bits of Index Register in Memory M X 0 IX FF 2 STX oprx16 SP 0 SP2 9EDF ee ff 5 STX oprx8 SP 0 SP1 9EEF ff 4 SUB opr8i IMM A0 ii 2 SUB opr8a DIR B0 dd 3 SUB opr16a EXT C0 hh ll 4 SUB oprx16 X IX2 D0 ee ff ...

Page 223: ...97 1 TPA Transfer CCR to Accumulator A CCR INH 85 1 TST opr8a M 0x00 0 DIR 3D dd 4 TSTA A 0x00 0 INH 4D 1 TSTX X 0x00 0 INH 5D 1 TST oprx8 X Test for Negative or Zero M 0x00 0 IX1 6D ff 4 TST X M 0x00 0 IX 7D 3 TST oprx8 SP M 0x00 0 SP1 9E6D ff 5 TSX Transfer SP to Index Register H X SP 0x0001 INH 95 2 TXA Transfer X Index Reg Low to Accumulator A X INH 9F 1 TXS Transfer Index Register to SP SP H ...

Page 224: ...Instruction Set Summary MC9S08PA4 Reference Manual Rev 5 08 2017 224 NXP Semiconductors ...

Page 225: ...rammable as falling edge sensitivity only rising edge sensitivity only both falling edge and low level sensitivity both rising edge and high level sensitivity One software enabled keyboard interrupt Exit from low power modes 11 1 2 Modes of Operation This section defines the KBI operation in Wait mode Stop mode Background debug mode MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semiconductors 225 ...

Page 226: ...BI interrupt must be enabled KBI_SC KBIE 1 before executing the Stop instruction allowing the KBI to continue to operate while the MCU is in Stop3 mode An enabled KBI pin KBI_PE KBIPEn 1 can be used to bring the MCU out of Stop3 mode if the KBI interrupt is enabled KBI_SC KBIE 1 11 1 2 3 KBI in Active Background mode When the MCU is in Active Background mode the KBI will continue to operate normal...

Page 227: ...PE An edge select register KBIx_ES See the direct page register summary in the Memory chapter for the absolute address assignments for all KBI registers This section refers to registers and control bits only by their names Some MCUs may have more than one KBI so register names include placeholder characters to identify which KBI is being referenced Memory Map and Registers KBI memory map Absolute ...

Page 228: ... detected 1 KBI interrupt request detected 2 KBACK KBI Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism 1 KBIE KBI Interrupt Enable KBIE determines whether a KBI interrupt is enabled or not 0 KBI interrupt not enabled 1 KBI interrupt enabled 0 KBMOD KBI Detection Mode KBMOD along with the KBEDG bits controls the detection mode of the KBI interrupt pins 0 Keyboard detects edg...

Page 229: ...odule is called a keyboard interrupt module because originally it was designed to simplify the connection and use of row column matrices of keyboard switches However these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low power modes The KBI module allows up to eight pins to act as additional interrupt sources Writing to the ...

Page 230: ...l be presented to the MPU Clearing of KBIx_SC KBF is accomplished by writing a 1 to KBIx_SC KBACK 11 5 2 Edge and level sensitivity A valid edge or level on an enabled KBI pin will set KBIx_SC KBF If KBIx_SC KBIE is set an interrupt request will be presented to the MCU Clearing of KBIx_SC KBF is accomplished by writing a 1 to KBIx_SC KBACK provided all enabled keyboard inputs are at their deassert...

Page 231: ...rupts by clearing KBIx_SC KBIE 2 Enable the KBI polarity by setting the appropriate KBIx_ES KBEDGn bits 3 Before using internal pullup resistors configure the associated bits in PORT_PTxPE 4 Enable the KBI pins by setting the appropriate KBIx_PE KBIPEn bits 5 Write to KBIx_SC KBACK to clear any false interrupts 6 Set KBIx_SC KBIE to enable interrupts Chapter 11 Keyboard Interrupts KBI MC9S08PA4 Re...

Page 232: ...Functional Description MC9S08PA4 Reference Manual Rev 5 08 2017 232 NXP Semiconductors ...

Page 233: ...or many years on NXP s 8 bit microcontrollers the HCS08 Timer PWM Module TPM The FlexTimer extends the functionality to meet the demands of motor control digital lighting solutions and power conversion while providing low cost and backwards compatibility with the TPM module All of the features common with the TPM module have fully backwards compatible register assignments and the FlexTimer can use...

Page 234: ...an be configured for center aligned PWM mode The generation of an interrupt per channel The generation of an interrupt when the counter overflows Backwards compatible with TPM 12 1 3 Modes of operation When the MCU is in active BDM background or BDM foreground mode the FTM temporarily suspends all counting until the MCU returns to normal user operating mode During stop mode all FTM input clocks ar...

Page 235: ...ture mode logic CPWMS MS0B MS0A ELS0B ELS0A CH0IE CH0F channel 0 interrupt channel 0 output C0VH L Output modes logic channel 1 input Input capture mode logic CPWMS MS1B MS1A ELS1B ELS1A CH1IE CH1F channel 1 interrupt channel 1 output C1VH L Output modes logic channel 7 input Input capture mode logic CPWMS MS7B MS7A ELS7B ELS7A CH7IE CH7F channel 7 interrupt channel 7 output C7VH L Output modes lo...

Page 236: ...used when an external clock is selected 12 2 2 CHn FTM channel n I O pin Each FTM channel can be configured to operate either as input or output The direction associated with each channel input or output is selected according to the mode assigned for that channel 12 3 Memory map and register definition This section provides a detailed description of all FTM registers 12 3 1 Module memory map This ...

Page 237: ...odulo Low FTM1_MODL 8 R W 00h 12 3 7 241 35 Channel Status and Control FTM1_C0SC 8 R W 00h 12 3 8 241 36 Channel Value High FTM1_C0VH 8 R W 00h 12 3 9 243 37 Channel Value Low FTM1_C0VL 8 R W 00h 12 3 10 244 38 Channel Status and Control FTM1_C1SC 8 R W 00h 12 3 8 241 39 Channel Value High FTM1_C1VH 8 R W 00h 12 3 9 243 3A Channel Value Low FTM1_C1VL 8 R W 00h 12 3 10 244 30C0 Status and Control F...

Page 238: ...earing sequence for a previous TOF 0 FTM counter has not overflowed 1 FTM counter has overflowed 6 TOIE Timer Overflow Interrupt Enable Enables FTM overflow interrupts 0 Disable TOF interrupts Use software polling 1 Enable TOF interrupts An interrupt is generated when TOF equals one 5 CPWMS Center aligned PWM Select Selects CPWM mode This mode configures the FTM to operate in up down counting mode...

Page 239: ...H or COUNT_L updates the FTM counter with its initial 16 bit value all zeroes and resets the read coherency mechanism regardless of the data involved in the write When BDM is active the FTM counter is frozen this is the value that you may read the read coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both counter ...

Page 240: ...Update of the registers with write buffers This write coherency mechanism may be manually reset by writing to the SC register whether BDM is active or not When BDM is active this write coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both bytes of the modulo register are written while BDM is active Any write to th...

Page 241: ... used to configure the interrupt enable channel configuration and pin function Table 12 2 Mode edge and level selection CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X XX 00 None Pin not used for FTM 0 00 01 Input capture Capture on Rising Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge 01 01 Output compare Toggle Output on match 10 Clear Output on match 11 Set Outp...

Page 242: ...has occurred 1 A channel event has occurred 6 CHIE Channel Interrupt Enable Enables channel interrupts 0 Disable channel interrupts Use software polling 1 Enable channel interrupts 5 MSB Channel Mode Select Used for further selections in the channel logic Its functionality is dependent on the channel mode See the table in the register description 4 MSA Channel Mode Select Used for further selectio...

Page 243: ...s the value into a buffer The registers are updated with the value of their write buffer according to Update of the registers with write buffers This write coherency mechanism may be manually reset by writing to the CnSC register whether BDM mode is active or not When BDM is active the write coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM be...

Page 244: ... 3 2 1 0 Read VAL_L Write Reset 0 0 0 0 0 0 0 0 FTMx_CnVL field descriptions Field Description VAL_L Channel Value Low Byte Captured FTM counter value of the input capture function or the match value for the output modes 12 4 Functional Description The following sections describe the FTM features The notation used in this document to represent the counters and the generation of the signals is show...

Page 245: ...by writing 0 0 to the CLKS 1 0 bits does not affect the FTM counter value or other registers The fixed frequency clock is an alternative clock source for the FTM counter that allows the selection of a clock other than the system clock or an external clock This clock input is defined by chip integration Refer to chip specific documentation for further information Due to FTM hardware implementation ...

Page 246: ... the selected clock divided by the prescaler see Prescaler The FTM counter has these modes of operation up counting see Up counting up down counting see Up down counting 12 4 3 1 Up counting Up counting is selected when CPWMS 0 The starting value of the count is 0x0000 and MODH L defines the final value of the count see the following figure The value of 0x0000 is loaded into the FTM counter and th...

Page 247: ...e count is 0x0000 and MODH L defines the final value of the count The value of 0x0000 is loaded into the FTM counter and the counter increments until the value of MODH L is reached at which point the counter is decremented until it returns to the value of 0x0000 and the up down counting restarts The FTM period when using up down counting is 2 MODH L period of the FTM counter clock The TOF bit is s...

Page 248: ...t when the FTM counter changes from 0xFFFF to 0x0000 See the following figure FTM counter 0x0004 0x0004 0xFFFE 0xFFFF 0x0003 0x0000 0x0001 0x0002 0x0003 0x0005 0x0006 TOF bit set TOF bit MODH L 0x0000 Figure 12 6 Example when the FTM counter is a free running 12 4 3 4 Counter reset Any write to CNTH or CNTL register resets the FTM counter to the value of 0x0000 and the channels output to its initi...

Page 249: ...t by writing to CnSC register Writes to the CnVH L registers are ignored in input capture mode While in BDM the input capture function works as configured When a selected edge event occurs the FTM counter value which is frozen because of BDM is captured into the CnVH L registers and the CHnF bit is set channel n input synchronizer edge detector was falling edge selected was rising edge selected ri...

Page 250: ...rflow channel n match channel n match CNTH L MODH L 0x0005 CnVH L 0x0003 CHnF bit Figure 12 8 Example of the output compare mode when the match toggles the channel output TOF bit 0 1 1 1 2 2 3 3 4 4 5 5 0 0 previous value previous value channel n output counter overflow counter overflow counter overflow channel n match channel n match CNTH L MODH L 0x0005 CnVH L 0x0003 CHnF bit Figure 12 9 Example...

Page 251: ... aligned because the leading edges of all PWM signals are aligned with the beginning of the period which is the same for all channels within an FTM period counter overflow counter overflow counter overflow channel n output channel n match channel n match channel n match pulse width Figure 12 11 EPWM period and pulse width with ELSnB ELSnA 1 0 If ELSnB ELSnA 0 0 when the counter reaches the value i...

Page 252: ... the channel n output is a 0 duty cycle EPWM signal and CHnF bit is not set even when there is the channel n match If CnVH L MODH L then the channel n output is a 100 duty cycle EPWM signal and CHnF bit is not set even when there is the channel n match Therefore MODH MODL must be less than 0xFFFF in order to get a 100 duty cycle EPWM signal 12 4 7 Center aligned PWM CPWM mode The center aligned mo...

Page 253: ...LSnA 0 0 when the counter reaches the value in the CnVH L registers the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If ELSnB ELSnA 1 0 then the channel n output is forced high at the channel n match FTM counter CnVH L when counting down and it is forced low at the channel n match when counting up see the following figure...

Page 254: ...nal This is not a significant limitation because the resulting period is much longer than required for normal applications The CPWM mode must not be used when the FTM counter is a free running counter 12 4 8 Update of the registers with write buffers This section describes the updating of registers that have write buffers 12 4 8 1 MODH L registers If CLKS 1 0 0 0 then MODH L registers are updated ...

Page 255: ...re updated after both bytes have been written and the FTM counter changes from MODH L to MODH L 0x0001 12 4 9 BDM mode When BDM mode is active the FlexTimer counter and the channels output are frozen However the value of FlexTimer counter or the channels output are modified in BDM mode when A write of any value to the CNTH or CNTL registers Counter reset resets the FTM counter to the value of 0x00...

Page 256: ... except for channels in output compare mode Counter reset The next step is to select the FTM counter clock by the CLKS 1 0 bits item 4 It is important to highlight that the pins are controlled only by FTM when CLKS 1 0 bits are different from zero table Mode Edge and Level Selection 1 FTM reset 0x0006 0x0005 0x0004 0x0003 0x0001 0x0008 0x0007 XXXX 0x0000 0x0002 FTM counter CLKS 1 0 4 write 0b01 to...

Page 257: ...e and the channel n output is toggled when there is a match C n VH L 0x0004 00 XX 01 Figure 12 18 FTM behavior after the reset when the channel n is in output compare mode FTM Interrupts 12 6 1 Timer overflow interrupt The timer overflow interrupt is generated when TOIE 1 and TOF 1 12 6 2 Channel n interrupt The channel n interrupt is generated when CHnIE 1 and CHnF 1 12 6 Chapter 12 FlexTimer Mod...

Page 258: ...FTM Interrupts MC9S08PA4 Reference Manual Rev 5 08 2017 258 NXP Semiconductors ...

Page 259: ...e as a cyclic wake up from low power modes Stop3 and Wait without the need of external components 13 2 Features Features of the RTC module include 16 bit up counter 16 bit modulo match limit Software controllable periodic interrupt on match Software selectable clock sources for input to prescaler with programmable 16 bit prescaler XOSC 32 768KHz nominal LPO 1 kHz Bus clock 13 2 1 Modes of operatio...

Page 260: ...e RTC can be used to bring the MCU out of stop modes with no external components if the real time interrupt is enabled 13 2 2 Block diagram The block diagram for the RTC module is shown in the following figure CLOCK DIVIDER EXT CLK RTCLKS RTCPS 16 bit counter 16 bit modulo 16 bit modulo 16 bit comparator 16 bit latch R 1 RTIF Write 1 to RTIF RTC INTERRUPT REQUEST RTIE RTCCNT RTCMOD BUS CLK BUS CLK...

Page 261: ...rrupt Flag This status bit indicates the RTC counter register reached the value in the RTC modulo register Writing a logic 0 has no effect Writing a logic 1 clears the bit and the real time interrupt request Reset clears RTIF to 0 0 RTC counter has not reached the value in the RTC modulo register 1 RTC counter has reached the value in the RTC modulo register 6 RTIE Real Time Interrupt Enable This ...

Page 262: ...lock 5 3 Reserved This field is reserved This read only field is reserved and always has the value 0 RTCPS Real Time Clock Prescaler Select These four read write bits select binary based or decimal based divide by values for the clock source Changing the prescaler value clears the prescaler and RTCCNT counters Reset clears RTCPS to 0000 000 Off 001 If RTCLKS x0 it is 1 if RTCLKS x1 it is 128 010 I...

Page 263: ...ster Low RTC_MODL RTC_MODL together with RTC_MODH indicates the value of the 16 bit modulo value Address 306Ah base 3h offset 306Dh Bit 7 6 5 4 3 2 1 0 Read MODL Write Reset 0 0 0 0 0 0 0 0 RTC_MODL field descriptions Field Description MODL RTC Modulo Low These sixteen read write bits MODH and MODL contain the modulo value used to reset the count to 0x0000 upon a compare match and set the RTIF sta...

Page 264: ...ly value of the current RTC count of the 16 bit counter Address 306Ah base 5h offset 306Fh Bit 7 6 5 4 3 2 1 0 Read CNTL Write Reset 0 0 0 0 0 0 0 0 RTC_CNTL field descriptions Field Description CNTL RTC Count Low CNTH and CNTL contain the current value of the 16 bit counter Writes have no effect to this register Reset or writing different values to RTCLKS and RTCPS clear the count to 0x00 13 4 Fu...

Page 265: ...escaler period RTCLKS 10 Bus clock 8 MHz source prescaler period RTCLKS 11 000 Off Off Off Off 001 30 5176 µs 128 ms 125 ns 16 µs 010 61 0351 µs 256 ms 250 ns 32 µs 011 122 0703 µs 512 ms 500 ns 64 µs 100 244 1406 µs 1024 ms 1 µs 128 µs 101 488 28125 µs 2048 ms 2 µs 256 µs 110 976 5625 µs 100 ms 4 µs 12 5 µs 111 1 9531 ms 1 s 8 µs 125 µs The RTC Modulo register RTC_MODH and RTC_MODL allows the com...

Page 266: ...en the counter RTC_CNTH and RTC_CNTL reaches the modulo value of 32767 the counter overflows to 0x00 and continues counting The modulo value is updated by fetching from RTC_MODH and RTC_MODL registers The real time interrupt flag RTC_SC1 RTIF sets when the counter value changes from 0x7FFF to 0x0000 13 5 Initialization application information This section provides example code to give some basic d...

Page 267: ...SC1_RTIE_MASK interrupt cleared and enabled Function Name RTC_ISR Notes Interrupt service routine for RTC module void RTC_ISR void Clears the interrupt flag RTIF and interrupt request RTC_SC1 RTC_SC1_RTIF_MASK RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes in an hour if Minutes 59 Hours Minutes 0 24 hours in a day if Hours 23 Days Hours 0 Ch...

Page 268: ...Initialization application information MC9S08PA4 Reference Manual Rev 5 08 2017 268 NXP Semiconductors ...

Page 269: ... error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8 bit or 9 bit character length Programmable 1 bit or 2 bit stop bits Receiver wakeup by idle line or address mark Optional 13 bit break character generation 11 bit break character detection Selectable transmitter output polarity 14 1...

Page 270: ...on Transmit Control Shift Enable SCI Controls TxD Loop Control To Receive Data In Tx Interrupt Request TXDIR Load From SCIxD TXINV BRK13 LOOPS RSRC TIE TC TDRE PT PE TCIE TE SBK T8 Pin Logic TO TxD TxD Direction Break All 0s Preamble All 1s To TxD Pin M 1x Baud Rate Clock Figure 14 1 SCI transmitter block diagram The following figure shows the receiver portion of the SCI Introduction MC9S08PA4 Ref...

Page 271: ...trol Wakeup Logic All 1s From Transmitter Error Interrupt Request Parity Checking Divide By 16 Active Edge Detect RXINV LBKDE RWUID From RxD Pin msb RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PF PEIE PT PE LOOPS RSRC WAKE ILT RWU M LBKDIF LBKDIE RXEDGIF RXEDGIE Figure 14 2 SCI receiver block diagram Chapter 14 Serial communications interface SCI MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semicon...

Page 272: ...smitter State meaning Whether TxD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings Timing Driven at the beginning or within a bit time according to the bit encoding method along with other configuration settings Otherwise transmissions are independent of reception timing 14 3 Register definition The SCI has 8 bit registers to control baud rate s...

Page 273: ..._BDH to buffer the high half of the new value and then write to SCI_BDL The working value in SCI_BDH does not change until SCI_BDL is written Address 3080h base 0h offset 3080h Bit 7 6 5 4 3 2 1 0 Read LBKDIE RXEDGIE SBNS SBR Write Reset 0 0 0 0 0 0 0 0 SCIx_BDH field descriptions Field Description 7 LBKDIE LIN Break Detect Interrupt Enable for LBKDIF 0 Hardware interrupts from SCI_S2 LBKDIF disab...

Page 274: ...reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled that is SCI_C2 RE or SCI_C2 TE bits are written to 1 Address 3080h base 1h offset 3081h Bit 7 6 5 4 3 2 1 0 Read SBR Write Reset 0 0 0 0 0 1 0 0 SCIx_BDL field descriptions Field Description SBR Baud Rate Modulo Divisor These 13 bits in SBR 12 0 are referred to collectively as BR They set the...

Page 275: ...d receiver input 4 M 9 Bit or 8 Bit Mode Select 0 Normal start 8 data bits lsb first stop 1 Receiver and transmitter use 9 bit data characters start 8 data bits lsb first 9th data bit stop 3 WAKE Receiver Wakeup Method Select 0 Idle line wakeup 1 Address mark wakeup 2 ILT Idle Line Type Select Setting this bit to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count ...

Page 276: ...E flag is 1 3 TE Transmitter Enable TE must be 1 to use the SCI transmitter When TE is set the SCI forces the TxD pin to act as an output for the SCI system When the SCI is configured for single wire operation LOOPS RSRC 1 TXDIR controls the direction of traffic on the single SCI communication line TxD pin TE can also queue an idle character by clearing TE then setting TE while a transmission is i...

Page 277: ...s Register 1 SCIx_S1 This register has eight read only status flags Writes have no effect Special software sequences which do not involve writing to this register clear these status flags Address 3080h base 4h offset 3084h Bit 7 6 5 4 3 2 1 0 Read TDRE TC RDRF IDLE OR NF FE PF Write Reset 1 1 0 0 0 0 0 0 SCIx_S1 field descriptions Field Description 7 TDRE Transmit Data Register Empty Flag TDRE is ...

Page 278: ...set IDLE is set only once even if the receive line remains idle for an extended period 0 No idle line detected 1 Idle line was detected 3 OR Receiver Overrun Flag OR is set when a new serial character is ready to be transferred to the receive data register buffer but the previously received character has not been read from SCI_D yet In this case the new character and all associated error informati...

Page 279: ...eshold changes from 10 bits to 11 bits preventing false detection of a 0x00 data character as a LIN break symbol Address 3080h base 5h offset 3085h Bit 7 6 5 4 3 2 1 0 Read LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF Write Reset 0 0 0 0 0 0 0 0 SCIx_S2 field descriptions Field Description 7 LBKDIF LIN Break Detect Interrupt Flag LBKDIF is set when the LIN break detect circuitry is enabled and a L...

Page 280: ...ength of 13 bit times if M 0 SBNS 0 or 14 if M 1 SBNS 0 or M 0 SBNS 1 or 15 if M 1 SBNS 1 1 LBKDE LIN Break Detection Enable LBKDE selects a longer break character detection length While LBKDE is set framing error FE and receive data register full RDRF flags are prevented from setting 0 Break character is detected at length 10 bit times if M 0 SBNS 0 or 11 if M 1 SBNS 0 or M 0 SBNS 1 or 12 if M 1 ...

Page 281: ... bit determines the direction of data at the TxD pin 0 TxD pin is an input in single wire mode 1 TxD pin is an output in single wire mode 4 TXINV Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output NOTE Setting TXINV inverts the TxD output for all cases data bits start and stop bits break and idle 0 Transmit data not inverted 1 Transmit data inverted 3 ORI...

Page 282: ... write transmit data buffer 7 6 R6T6 Read receive data buffer 6 or write transmit data buffer 6 5 R5T5 Read receive data buffer 5 or write transmit data buffer 5 4 R4T4 Read receive data buffer 4 or write transmit data buffer 4 3 R3T3 Read receive data buffer 3 or write transmit data buffer 3 2 R2T2 Read receive data buffer 2 or write transmit data buffer 2 1 R1T1 Read receive data buffer 1 or wri...

Page 283: ... this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed The MCU resynchronizes to bit boundaries on every high to low transition In the worst case there are no such transitions in the full 10 or 11 bit or 12 bittime character frame so any mismatch in baud rate is accumulated for the whole character time For...

Page 284: ...g to SCI_D to allow data to be transmitted If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin the transmitter sets the transmit complete flag and enters an idle mode with TxD high waiting for more characters to transmit Writing 0 to SCI_C2 TE does not immediately release the pin to be a general purpose I O pin Any transmit activity in progress mu...

Page 285: ... character is affected by the SCI_S2 BRK13 and SCI_C1 M as shown below Table 14 3 Break character length BRK13 M SBNS Break character length 0 0 0 10 bit times 0 0 1 11 bit times 0 1 0 11 bit times 0 1 1 12 bit times 1 0 0 13 bit times 1 0 1 14 bit times 1 1 0 14 bit times 1 1 1 15 bit times 14 4 3 Receiver functional description In this section the receiver block diagram is a guide for the overal...

Page 286: ...ud rate clock divides the bit time into 16 segments labeled SCI_D RT1 through SCI_D RT16 When a falling edge is located three more samples are taken at SCI_D RT3 SCI_D RT5 and SCI_D RT7 to make sure this was a real start bit and not merely noise If at least two of these three samples are 0 the receiver assumes it is synchronized to a receive character The receiver then samples each bit time includ...

Page 287: ...n time to look at the first character s of the next message 14 4 3 2 1 Idle line wakeup When wake is cleared the receiver is configured for idle line wakeup In this mode SCI_C2 RWU is cleared automatically when the receiver detects a full character time of the idle line level The SCI_C1 M control field selects 8 bit or 9 bit data mode and SCI_BDH SBNS selects 1 bit or 2 bit stop bit number that de...

Page 288: ...d by local interrupt enable masks The flags can be polled by software when the local masks are cleared to disable generation of hardware interrupt requests The SCI transmitter has two status flags that can optionally generate hardware interrupt requests Transmit data register empty SCI_S1 TDRE indicates when there is room in the transmit data buffer to write another transmit character to SCI_D If ...

Page 289: ...ed from the receive shifter to the receive data buffer the overrun SCI_S1 OR flag is set instead of the data along with any associated NF FE or PF condition is lost At any time an active edge on the RxD serial data input pin causes the SCI_S2 RXEDGIF flag to set The SCI_S2 RXEDGIF flag is cleared by writing a 1 to it This function depends on the receiver being enabled SCI_C2 RE 1 14 4 5 Baud rate ...

Page 290: ...4 For a 9 bit data or 2 stop bits character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in Figure 14 4 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles 3 RT cycles 163 RT cycles The maximum percent difference between the receiver cou...

Page 291: ... bits character data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character shown in the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles 176 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit or 2 st...

Page 292: ...hifter The 9 bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit or it is used with address mark wake up so the ninth data bit can serve as the wakeup bit In custom protocols the ninth bit can also serve as a software controlled marker 14 4 6 2 Stop mode operation During all stop modes clocks to the SCI module are halted No SCI module registers ...

Page 293: ...uplex serial connection The receiver is internally connected to the transmitter output and to the TxD pin The RxD pin is not used and reverts to a general purpose port I O pin In single wire mode the SCI_C3 TXDIR bit controls the direction of serial data on the TxD pin When SCI_C3 TXDIR is cleared the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the ...

Page 294: ...Functional description MC9S08PA4 Reference Manual Rev 5 08 2017 294 NXP Semiconductors ...

Page 295: ...rences Output formatted in 8 10 or 12 bit right justified unsigned format Single or Continuous Conversion automatic return to idle after single conversion Support up to eight result FIFO with selectable FIFO depth Configurable sample time and conversion speed power Conversion complete flag and interrupt Input clock selectable from up to four sources Operation in Wait or Stop3 modes for lower noise...

Page 296: ... to CPU Input Channel FIFO Fulfilled AD0 AD1 AD2 AD6 AD7 AD8 AD21 AD20 AD22 AD23 AD29 AD30 AD31 AD32 Compare Value 2 ANALOG MUX CLK MUX AD CHANNEL FIFO AD RESULT FIFO 12 bit AD result 12 bit AD result 12 bit AD result 12 bit AD result 12 bit AD result 12 bit AD result 12 bit AD result 12 bit AD result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 5 bit ch 5 bit ch 5 bit ch 5 bit ch 5 bit ch 5 bit ch 5 bit ch 5 ...

Page 297: ...ally to VSS If externally available connect the VSSA pin to the same voltage potential as VSS 15 2 3 Voltage Reference High VREFH VREFH is the high reference voltage for the converter In some packages VREFH is connected internally to VDDA If externally available VREFH may be connected to the same potential as VDDA or may be driven by an external source between the minimum VDDA specified in the dat...

Page 298: ...00h 15 3 8 305 30AC Pin Control 1 Register ADC_APCTL1 8 R W 00h 15 3 9 306 15 3 1 Status and Control Register 1 ADC_SC1 This section describes the function of the ADC status and control register ADC_SC1 Writing ADC_SC1 aborts the current conversion and initiates a new conversion if the ADCH bits are equal to a value other than all 1s When FIFO is enabled the analog input channel FIFO is written vi...

Page 299: ... Continuous Conversion Enable ADCO enables continuous conversions 0 One conversion following a write to the ADC_SC1 when software triggered operation is selected or one conversion following assertion of ADHWT when hardware triggered operation is selected When the FIFO function is enabled AFDEP 0 a set of conversions are triggered 1 Continuous conversions are initiated following a write to ADC_SC1 ...

Page 300: ...e trigger is selected a conversion is initiated following the assertion of the ADHWT input 0 Software trigger selected 1 Hardware trigger selected 5 ACFE Compare Function Enable Enables the compare function 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable Configures the compare function to trigger when the result of the conversion of the input bei...

Page 301: ...ration The power is reduced at the expense of maximum clock speed 6 5 ADIV Clock Divide Select ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK 00 Divide ration 1 and clock rate Input clock 01 Divide ration 2 and clock rate Input clock 2 10 Divide ration 3 and clock rate Input clock 4 11 Divide ration 4 and clock rate Input clock 8 4 ADLSMP Long Sample Time Configu...

Page 302: ...IFO always use the first dummied FIFO channels when it is enabled When this bit is set and FIFO function is enabled ADC will repeat using the first FIFO channel as the conversion channel until the result FIFO is fulfilled In continuous mode ADCO 1 ADC will start next conversion with the same channel when COCO is set 0 FIFO scan mode disabled 1 FIFO scan mode enabled 5 ACFSEL Compare function selec...

Page 303: ...abled 111 8 level FIFO is enabled 15 3 5 Conversion Result High Register ADC_RH In 12 bit operation ADC_RH contains the upper four bits of the result of a 12 bit conversion ADC_RH is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met Reading ADC_RH prevents the ADC from transferring subsequent conversion results into the result re...

Page 304: ..._RL is read If ADC_RL is not read until the next conversion is completed the intermediate conversion results are lost In 8 bit mode there is no interlocking with ADC_RH If the MODE bits are changed any data in ADC_RL becomes invalid When FIFO is enabled the result FIFO is read via ADC_RH ADC_RL The ADC conversion completes when the input channel FIFO is fulfilled at the depth indicated by the AFDE...

Page 305: ...ion 7 4 Reserved This field is reserved This read only field is reserved and always has the value 0 CV Conversion Result 15 8 15 3 8 Compare Value Low Register ADC_CVL This register holds the lower 8 bits of the 12 bit compare value Bits CV7 CV0 are compared to the lower 8 bits of the result following a conversion in 12 bit mode Address 10h base 7h offset 17h Bit 7 6 5 4 3 2 1 0 Read CV Write Rese...

Page 306: ...rols the pin associated with channel AD6 0 AD6 pin I O control enabled 1 AD6 pin I O control disabled 5 ADPC5 ADC Pin Control 5 ADPC5 controls the pin associated with channel AD5 0 AD5 pin I O control enabled 1 AD5 pin I O control disabled 4 ADPC4 ADC Pin Control 4 ADPC4 controls the pin associated with channel AD4 0 AD4 pin I O control enabled 1 AD4 pin I O control disabled 3 ADPC3 ADC Pin Contro...

Page 307: ...it mode the selected channel voltage is converted by a successive approximation algorithm into a 10 bit digital result In 8 bit mode the selected channel voltage is converted by a successive approximation algorithm into a 8 bit digital result When the conversion is completed the result is placed in the data registers ADC_RH and ADC_RL In 10 bit mode the result is rounded to 10 bits and placed in t...

Page 308: ...it or Stop3 mode and allows conversions in these modes for lower noise operation Whichever clock is selected its frequency must fall within the specified frequency range for ADCK If the available clocks are too slow the ADC does not perform according to specifications If the available clocks are too fast the clock must be divided to the appropriate frequency This divider is specified by the ADC_SC...

Page 309: ...by a software or hardware trigger In addition the ADC module can be configured for low power operation long sample time continuous conversion and an automatic compare of the conversion result to a software determined compare value 15 4 4 1 Initiating conversions A conversion initiates under the following conditions A write to ADC_SC1 or a set of write to ADC_SC1 in FIFO mode with ADCH bits not all...

Page 310: ...echanism could result in several discarded conversions and excess power consumption To avoid this issue the data registers must not be read after initiating a single conversion until the conversion completes In fifo mode a blocking mechanism will keep current channel conversion and no channel fifo and result fifo switching until a block mechanism is released 15 4 4 3 Aborting conversions Any conve...

Page 311: ...and a successive approximation algorithm is performed to determine the digital value of the analog signal The result of the conversion is transferred to ADC_RH and ADC_RL upon completion of the conversion algorithm If the bus frequency is less than the fADCK frequency precise sample time for continuous conversions cannot be guaranteed when short sample is enabled ADC_SC3 ADLSMP 0 If the bus freque...

Page 312: ...le by the ADC_SC3 ADICLK bits and the divide ratio is specified by the ADC_SC3 ADIV bits For example in 10 bit mode with the bus clock selected as the input clock source the input clock divide by 1 ratio selected and a bus frequency of 8 MHz then the conversion time for a single conversion as given below The number of bus cycles at 8 MHz is Note The ADCK frequency must be between fADCK minimum and...

Page 313: ... met Note The compare function can not work in continuous conversion mode when FIFO enabled 15 4 6 FIFO operation The ADC module supports FIFO operation to minimize the interrupts to CPU in order to reduce CPU loading in ADC interrupt service routines This module contains two FIFOs to buffer analog input channels and analog results respectively The FIFO function is enabled when the ADC_SC4 AFDEP b...

Page 314: ... Result FIFO write pointer Channel FIFO read pointer FIFO conversion start FIFO Read Write Logic FIFO Work Logic COMPARE LOGIC COMPARE LOGIC Result FIFO Fulfilled Channel FIFO Fulfilled COCO CK D Q BUS CLK CK D Q 16 bit AD result 16 bit AD result 16 bit AD result 16 bit AD result 16 bit AD result 16 bit AD result 16 bit AD result 16 bit AD result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 5 bit ch 5 bit ch 5...

Page 315: ... of input channel FIFO When the ADC_SC4 ASCANE bit is set in FIFO mode the FIFO will always use the first dummied channel in spite of the value in the input channel FIFO The ADC conversion start to work in FIFO mode as soon as the first channel is dummied The following write operation to the input channel FIFO will cover the first channel element in this FIFO In scan FIFO mode the ADC_SC1 COCO bit...

Page 316: ...gger occurs Hardware Triggered Continuous Conversion COCO 1 Conversions Completed max Only need one hardware trigger If new trigger occurs the new set conversions will be generated max AFDEP max 0 n max AFDEP 0 n max 0 0 n 0 n n max 0 n max max AFDEP when last hardware trigger occurs max max AFDEP 0 n The nth AD channel fetch The nth AD channel fetch The nth AD channel fetch when n hardware trigge...

Page 317: ...ed 15 4 8 1 Stop3 mode with ADACK disabled If the asynchronous clock ADACK is not selected as the conversion clock executing a STOP instruction aborts the current conversion and places the ADC in its idle state The contents of ADC_RH and ADC_RL are unaffected by Stop3 mode After exiting from Stop3 mode a software or hardware trigger is required to resume conversions 15 4 8 2 Stop3 mode with ADACK ...

Page 318: ...ontinuous conversion and a polled or interrupt approach among many other options Refer to ADC_SC3 register for information used in this example Note Hexadecimal values prefixed by a 0x binary values prefixed by a and decimal values have no preceding character 15 5 1 ADC module initialization example Before the ADC module can be used to complete conversions it must be initialized Given below is a m...

Page 319: ...C1 ADC_SC1_AIEN_MASK ADC_SC1_ADCH0_MASK 15 5 2 ADC FIFO module initialization example Before the ADC module can be used to start FIFOed conversions an initialization procedure must be performed A typical sequence is as follows 1 Update the configuration register ADC_SC3 to select the input clock source and the divide ratio used to generate the internal clock ADCK This register is also used to sele...

Page 320: ...SK setting hardware trigger ADC_SC2 ADC_SC2_ADTRG_MASK 4 Level FIFO ADC_SC4 ADC_SC4_AFDEP1_MASK ADC_SC4_AFDEP0_MASK dummy the 1st channel ADC_SC1 ADC_SC1_ADCH0_MASK dummy the 2nd channel ADC_SC1 ADC_SC1_ADCH1_MASK ADC_SC1_ADCH0_MASK dummy the 3rd channel ADC_SC1 ADC_SC1_ADCH2_MASK ADC_SC1_ADCH0_MASK dummy the 4th channel and ADC starts conversion ADC_SC1 ADC_SC1_AIEN_MASK ADC_SC1_ADCH2_MASK ADC_SC...

Page 321: ...A and VDDA are shared with the MCU digital supply pins In these cases there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained When available on a separate pin both VDDA and VSSA must be connected to the same voltage potential as their corresponding MCU digital supply VDD and VSS a...

Page 322: ...h must be minimum parasitic only 15 6 1 3 Analog input pins The external analog inputs are typically shared with digital I O pins on MCU devices The pin I O control is disabled by setting the appropriate control bit in one of the pin control registers Conversions can be performed on inputs without the associated pin control register bit set It is recommended that the pin control register bit alway...

Page 323: ...ately 5 5 pF sampling to within 1 4 LSB at 12 bit resolution can be achieved within the minimum sample window 3 5 cycles at 8 MHz maximum ADCK frequency provided the resistance of the external analog source RAS is kept below 2 kΩ Higher source resistances or higher accuracy sampling is possible by setting ADC_SC3 ADLSMP to increase the sample window to 23 5 cycles or decreasing ADCK frequency to i...

Page 324: ...hing input or output on the MCU during the conversion There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC In these situations or when the MCU cannot be placed in wait or Stop3 or I O activity cannot be halted these recommended actions may reduce the effect of noise on the accuracy Place a 0 01 µF capac...

Page 325: ... 1 lsb to 0 lsb and the code width of each step is 1 lsb 15 6 2 5 Linearity errors The ADC may also exhibit non linearity of several forms Every effort has been made to reduce these errors but the system must be aware of them because they affect overall accuracy These errors are Zero scale error EZS sometimes called offset This error is defined as the difference between the actual code width of th...

Page 326: ...epeatedly Ideally when the input voltage is infinitesimally smaller than the transition voltage the converter yields the lower code and vice versa However even small amounts of system noise can cause the converter to be indeterminate between two codes for a range of input voltages around the transition voltage This range is normally around 1 2 lsb in 8 bit or 10 bit mode or around 2 lsb in 12 bit ...

Page 327: ...e for applications where voltage reference is needed The 64 tap resistor ladder network divides the supply reference Vin into 64 voltage level A 6 bit digital signal input selects output voltage level which varies from Vin to Vin 64 Vin can be selected from two voltage sources 16 1 1 Features ACMP features include Operational over the whole supply range of 2 7 V to 5 5 V On chip 6 bit resolution D...

Page 328: ...d to wake the MCU up from Stop3 mode If the Stop3 is exited by an interrupt the ACMP setting remains before entering the Stop mode If Stop3 is exited with a reset the ACMP goes into its reset The user must turn off the DAC if the output is not used as a reference input of ACMP to save power because the DAC consumes additional power 16 1 2 3 Operation in Debug mode When the MCU is in Debug mode the...

Page 329: ... to an external pin ACMP_CS ACOPE controls the pin to enable disable the ACMP output function 16 3 Memory map and register definition ACMP memory map Absolute address hex Register name Width in bits Access Reset value Section page 2C ACMP Control and Status Register ACMP_CS 8 R W 00h 16 3 1 330 2D ACMP Control Register 0 ACMP_C0 8 R W 00h 16 3 2 331 2E ACMP Control Register 1 ACMP_C1 8 R W 00h 16 ...

Page 330: ...ing a 1 to this bit has no effect 4 ACIE ACMP Interrupt Enable Enables an ACMP CPU interrupt 0 Disable the ACMP Interrupt 1 Enable the ACMP Interrupt 3 ACO ACMP Output Reading ACO will return the current value of the analog comparator output ACO is reset to a 0 and will read as a 0 when the ACMP is disabled ACE 0 2 ACOPE ACMP Output Pin Enable ACOPE enables the pad logic so that the output can be ...

Page 331: ... reserved and always has the value 0 5 4 ACPSEL ACMP Positive Input Select 00 External reference 0 01 External reference 1 10 Reserved 11 DAC output 3 2 Reserved This field is reserved This read only field is reserved and always has the value 0 ACNSEL ACMP Negative Input Select 00 External reference 0 01 External reference 1 10 Reserved 11 DAC output 16 3 3 ACMP Control Register 1 ACMP_C1 Address ...

Page 332: ...ription 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 ACIPE ACMP Input Pin Enable This 3 bit field controls if the corresponding ACMP external pin can be driven by an analog input 0 The corresponding external analog input is not allowed 1 The corresponding external analog input is allowed 16 4 Functional description The ACMP module is functionally ...

Page 333: ...he falling edge on ACMP output is valid When ACMP_CS ACMOD 01b only rising edge on ACMP output is valid When ACMP_CS ACMOD 11b both the rising edge and falling edge on the ACMP output are valid The ACMP output is synchronized by the bus clock to generate ACMP_CS ACO so that the CPU can read the comparison In stop3 mode if the output of ACMP is changed ACMPO cannot be updated in time The output can...

Page 334: ...ets During a reset the ACMP is configured in the default mode Both CMP and DAC are disabled 16 7 Interrupts If the bus clock is available when a valid edge defined in ACMP_CS ACMOD occurs the ACMP_CS ACF is asserted If ACMP_CS ACIE is set a ACMP interrupt event occurs The ACMP_CS ACF bit remains asserted until the ACMP interrupt is cleared by software When in stop3 mode a valid edge on ACMP output...

Page 335: ... Features Features of the WDOG module include Configurable clock source inputs independent from the bus clock Internal 32 kHz RC oscillator Internal 1 kHz RC oscillator External clock source Programmable timeout period Programmable 16 bit timeout value Optional fixed 256 clock prescaler when longer timeout periods are needed Robust write sequence for counter refresh Refresh sequence of writing 0xA...

Page 336: ...or allowing updates to write once configuration bits Software must make updates within 128 bus clocks after unlocking and before WDOG closing unlock window 17 1 2 Block diagram The following figure provides a block diagram of the WDOG module MUX MUX MUX 32K CLK EXT CLK UPDATE EN CLK PRES WIN INT 1K CLK BUS CLK 256 16 bit Window Register 0xD928 0xC520 Control Status 128 Bus Cycle Disable Protect Bi...

Page 337: ...dog Control and Status Register 1 WDOG_CS1 This section describes the function of Watchdog Control and Status Register 1 NOTE TST is cleared 0 0 on POR only Any other reset does not affect the value of this field Address 3030h base 0h offset 3030h Bit 7 6 5 4 3 2 1 0 Read EN INT UPDATE TST DBG WAIT STOP Write Reset 1 0 0 0 0 0 0 0 WDOG_CS1 field descriptions Field Description 7 EN Watchdog Enable ...

Page 338: ... the value of this field 00 Watchdog test mode disabled 01 Watchdog user mode enabled Watchdog test mode disabled After testing the watchdog software should use this setting to indicate that the watchdog is functioning normally in user mode 10 Watchdog test mode enabled only the low byte is used WDOG_CNTL is compared with WDOG_TOVALL 11 Watchdog test mode enabled only the high byte is used WDOG_CN...

Page 339: ...pt occurred 1 An interrupt occurred 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 PRES Watchdog Prescalar This write once bit enables a fixed 256 pre scaling of watchdog counter reference clock The block diagram shows this clock divider option 0 256 prescalar disabled 1 256 prescalar enabled 3 2 Reserved This field is reserved This read only field ...

Page 340: ... section 2 The unlock sequence allows the watchdog to be reconfigured without forcing a reset when WDOG_CS1 UPDATE 1 See the Example code Reconfiguring the Watchdog section NOTE All other writes to these registers are illegal and force a reset Address 3030h base 2h offset 3032h Bit 7 6 5 4 3 2 1 0 Read CNTHIGH Write Reset 0 0 0 0 0 0 0 0 WDOG_CNTH field descriptions Field Description CNTHIGH High ...

Page 341: ...ounter reaches the timeout value the watchdog forces a reset NOTE Do not write 0 to the Watchdog Timeout Value Register otherwise the watchdog always generates a reset Address 3030h base 4h offset 3034h Bit 7 6 5 4 3 2 1 0 Read TOVALHIGH Write Reset 0 0 0 0 1 0 0 1 WDOG_TOVALH field descriptions Field Description TOVALHIGH High byte of the timeout value 17 2 6 Watchdog Timeout Value Register Low W...

Page 342: ... WDOG_WINH and WDOG_WINL must be less than WDOG_TOVALH and WDOG_TOVALL Address 3030h base 6h offset 3036h Bit 7 6 5 4 3 2 1 0 Read WINHIGH Write Reset 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field Description WINHIGH High byte of Watchdog Window 17 2 8 Watchdog Window Register Low WDOG_WINL See the description of the WDOG_WINH register Address 3030h base 7h offset 3037h Bit 7 6 5 4 3 2 1 0 Re...

Page 343: ... all programmable but must be configured within 128 bus clocks after a reset 17 3 1 Watchdog refresh mechanism The watchdog resets the MCU if the watchdog counter is not refreshed A robust refresh mechanism makes it very unlikely that the watchdog can be refreshed by runaway code To refresh the watchdog counter software must execute a refresh write sequence before the timeout period expires In add...

Page 344: ...s are early When Window mode is enabled the watchdog must be refreshed after the counter has reached a minimum expected time value otherwise the watchdog resets the MCU The minimum expected time value is specified in the WDOG_WINH L registers Setting CS1 WIN enables Window mode 17 3 1 2 Refreshing the Watchdog The refresh write sequence is a write of 0xA602 followed by a write of 0xB480 to the WDO...

Page 345: ...s timeout value and window value are write once after reset This means that after a write has occurred they cannot be changed unless a reset occurs This provides a robust mechanism to configure the watchdog and ensure that a runaway condition cannot mistakenly disable or modify the watchdog configuration after configured This is guaranteed by the user configuring the window and timeout value first...

Page 346: ...atchdog within 128 bus clocks otherwise the watchdog forces a reset to the MCU NOTE Due to 128 bus clocks requirement for reconfiguring the watchdog some delays must be inserted before executing STOP or WAIT instructions after reconfiguring the watchdog This ensures that the watchdog s new configuration takes effect before MCU enters low power mode Otherwise the MCU may not be waken up from low po...

Page 347: ...mmarizes the different watchdog timeout periods available Table 17 1 Watchdog timeout availability Reference clock Prescaler Watchdog time out availability Internal 1 kHz LPO Pass through 1 ms 65 5 s1 256 256 ms 16 777 s Internal 32 kHz Pass through 31 25 µs 2 048 s 256 8 ms 524 3 s 1 MHz from bus or external Pass through 1 µs 65 54 ms 256 256 µs 16 777 s 20 MHz from bus or external Pass through 5...

Page 348: ...t in case the main WDOG logic loses its clock the bus clock and can no longer monitor the counter If the watchdog counter overflows twice in succession without an intervening reset the backup reset function takes effect and generates a reset 17 3 6 Functionality in debug and low power modes By default the watchdog is not functional in Active Background mode Wait mode or Stop3 mode However the watc...

Page 349: ...nnection from the low byte to the high byte is tested Using this test feature reduces the test time to 512 clocks not including overhead such as user configuration and reset vector fetches To further speed testing use a faster clock such as the bus clock for the counter reference On a power on reset the POR bit in the system reset register is set indicating the user should perform the WDOG fast te...

Page 350: ...3 7 2 Entering user mode After successfully testing the low and high bytes of the watchdog counter the user can configure WDOG_CS1 TST to 01b to indicate the watchdog is ready for use in application user mode Thus if a reset occurs again software can recognize the reset trigger as a real watchdog reset caused by runaway or faulty application code As an ongoing test when using the default 1 kHz clo...

Page 351: ... background command that writes a one to the BDFR bit in the SBDFR register Other causes of reset including an external pin reset or an internally generated error reset ignore the state of the BKGD pin and reset into normal user mode If no debug pod is connected to the BKGD pin the MCU will always reset into normal operating mode 18 1 2 Features Features of the BDC module include Single pin for mo...

Page 352: ...hat supports in circuit programming of on chip nonvolatile memory and sophisticated non intrusive debug capabilities Unlike debug interfaces on earlier 8 bit MCUs this system does not interfere with normal application resources It does not use any user memory or locations in the memory map and does not share any on chip peripherals BDC commands are divided into two groups Active background mode co...

Page 353: ...8 2 1 BKGD pin description BKGD is the single wire background debug interface pin The primary function of this pin is for bidirectional serial communication of active background mode commands and data During reset this pin is used to select between starting in active background mode or starting the user s application program This pin is also used to request a timed sync response pulse to allow a h...

Page 354: ... an external controller or by the MCU Data is transferred MSB first at 16 BDC clock cycles per bit nominal speed The interface times out if 512 BDC clock cycles occur between falling edges from the host Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system The custom serial protocol requires the debug pod to...

Page 355: ...t generated falling edge on BKGD to the perceived start of the bit time in the target MCU The host holds the BKGD pin low long enough for the target to recognize it at least two target BDC cycles The host must release the low drive before the target MCU drives a brief active high speedup pulse seven cycles after the perceived start of the bit time The host should sample the bit level about 10 cycl...

Page 356: ... PU LSE SPEED U P PU LSE EAR LIEST STAR T O F NEXT BIT H O ST SAM PLES BKG D PIN Figure 18 4 BDM target to host serial bit timing logic 0 18 2 3 BDC commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU All commands and data are sent MSB first using a custom BDC communications protocol Active background mode commands require that the target MCU is cur...

Page 357: ...ledge protocol Refer to NXP document order no HCS08RMv1 D ACK_DISABLE Non intrusive D6 d Disable acknowledge protocol Refer to NXP document order no HCS08RMv1 D BACKGROUND Non intrusive 90 d Enter active background mode if enabled ignore if ENBDM bit equals 0 READ_STATUS Non intrusive E4 SS Read BDC status from BDCSCR WRITE_CONTROL Non intrusive C4 CC Write BDC controls in BDCSCR READ_BYTE Non int...

Page 358: ...air H X WRITE_SP Active BDM 4F WD16 d Write stack pointer SP WRITE_NEXT Active BDM 50 WD d Increment H X by one then write memory byte located at H X WRITE_NEXT_WS Active BDM 51 WD d SS Increment H X by one then write memory byte located at H X Also report status 1 The SYNC command is a special operation that does not have a command code The SYNC command is unlike other BDC commands because the ho...

Page 359: ...ss The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue This implies that tagged breakpoints can be placed only at the address of an instruction opcode while forced breakpoints can be set at any address The breakpoint...

Page 360: ...ed address is actually executed as opposed to only being read from memory into the instruction queue The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes Comparators are disabled temporarily during all BDC accesses The A comparator is always associated with the 16 bit CPU address The B comparator compares to the CPU address or the 8 ...

Page 361: ... of the FIFO by simply reading DBGFL Each time DBGFL is read the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL In trigger modes where the FIFO is storing change of flow addresses there is a delay between CPU addresses and the input side of the FIFO Because of this delay if the trigger event itself is a change of flow address or a change of flow address app...

Page 362: ...e any change of flow from a jump branch subroutine call or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed A force type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request The usual action in response to a breakpoint is to go to active background mode rather than continuing to...

Page 363: ...y trigger modes and all such debug runs are begin type traces When TRGSEL 1 to select opcode fetch triggers it is not necessary to use R W in comparisons because opcode tags would apply only to opcode fetches that are always read cycles It would also be unusual to specify TRGSEL 1 while using a full mode trigger because the opcode value is normally known at a particular address The following trigg...

Page 364: ...h time the address matches the value in comparator B Trigger events cause the data to be captured into the FIFO The debug run ends when the FIFO becomes full A Then Event Only B Store Data After the address has matched the value in comparator A a trigger event occurs each time the address matches the value in comparator B Trigger events cause the data to be captured into the FIFO The debug run end...

Page 365: ...d equate or header file is used to translate these names into the appropriate absolute addresses BDC memory map Absolute address hex Register name Width in bits Access Reset value Section page 0 BDC Status and Control Register BDC_SCR 8 R W 00h 18 4 1 365 1 BDC Breakpoint Match Register High BDC_BKPTH 8 R W 00h 18 4 2 367 2 BDC Breakpoint Register Low BDC_BKPTL 8 R W 00h 18 4 3 368 3 System Backgr...

Page 366: ...e BDCBKPT match register When FTS 0 a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged If this tagged opcode ever reaches the end of the instruction queue the CPU enters active background mode rather than executing the tagged opcode 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Brea...

Page 367: ...iled because the CPU entered wait or stop mode 0 DVF Data Valid Failure Status 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 18 4 2 BDC Breakpoint Match Register High BDC_BKPTH This register together with BDC_BKPTL holds the address for the hardware breakpoint in the BDC The BKPTEN and FTS control bi...

Page 368: ... 4 3 2 1 0 Read A 7 0 Write Reset 0 0 0 0 0 0 0 0 BDC_BKPTL field descriptions Field Description A 7 0 Low 8 bit of hardware breakpoint address 18 4 4 System Background Debug Force Reset Register BDC_SBDFR This register contains a single write only control bit A serial background mode command such as WRITE_BYTE must be used to write to SBDFR Attempts to write this register from a user program are ...

Page 369: ...ound mode command such as WRITE_BYTE allows an external debug host to force a target system reset Writing 1 to this bit forces an MCU reset This bit cannot be written from a user program Chapter 18 Development support MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semiconductors 369 ...

Page 370: ...Memory map and register description MC9S08PA4 Reference Manual Rev 5 08 2017 370 NXP Semiconductors ...

Page 371: ...ators A B and C with ability to match addresses in 64 KB space Dual mode Comparators A and B used to compare addresses Full mode Comparator A compares address and Comparator B compares data Can be used as triggers and or breakpoints Comparator C can be used as a normal hardware breakpoint Loop1 capture mode Comparator C is used to track most recent COF event captured into FIFO Tag and Force type b...

Page 372: ...rigger modes Ability to End trace until reset and begin trace from reset 19 1 2 Modes of operation The on chip ICE system can be enabled in all MCU functional modes The DBG module is disabled if the MCU is secure The DBG module comparators are disabled when executing a Background Debug Mode BDM command 19 1 3 Block diagram The following figure shows the structure of the DBG module Introduction MC9...

Page 373: ...ite Data Bus Trigger Break Control Logic c o n t r o FIFO Data DBG Read Data Bus DBG Module Enable addr 16 0 1 m u x Write Data Bus Read Data Bus Read Write l Comparator C match_C MCU reset core_cof 1 0 Read DBGFX Figure 19 1 DBG block diagram 19 2 Signal description The DBG module contains no external signals 19 3 Memory map and registers This section provides a detailed description of all DBG re...

Page 374: ..._CCX 8 R W 00h 19 3 11 382 301B Debug FIFO Extended Information Register DBG_FX 8 R 00h 19 3 12 383 301C Debug Control Register DBG_C 8 R W C0h 19 3 13 383 301D Debug Trigger Register DBG_T 8 R W 40h 19 3 14 384 301E Debug Status Register DBG_S 8 R 01h 19 3 15 386 301F Debug Count Status Register DBG_CNT 8 R 00h 19 3 16 387 19 3 1 Debug Comparator A High Register DBG_CAH NOTE All the bits in this ...

Page 375: ...ere DBGEN 1 and BEGIN 0 the bits in this register do not change after reset Address 3010h base 1h offset 3011h Bit 7 6 5 4 3 2 1 0 Read CA 7 0 Write Reset 1 1 1 1 1 1 1 0 DBG_CAL field descriptions Field Description CA 7 0 Comparator A Low The Comparator A Low compare bits control whether Comparator A will compare the address bus bits 7 0 to a logic 1 or logic 0 0 Compare corresponding address bit...

Page 376: ...mpare bits control whether Comparator B will compare the address bus bits 15 8 to a logic 1 or logic 0 Not used in full mode 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 19 3 4 Debug Comparator B Low Register DBG_CBL NOTE All the bits in this register reset to 0 in POR or non end run reset The bits are undefined in end run reset In the case of a...

Page 377: ...ined in end run reset In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset Address 3010h base 4h offset 3014h Bit 7 6 5 4 3 2 1 0 Read CC 15 8 Write Reset 0 0 0 0 0 0 0 0 DBG_CCH field descriptions Field Description CC 15 8 Comparator C High Compare Bits The Comparator C High compare bits control whether Comparator C will compare the ad...

Page 378: ... Low compare bits control whether Comparator C will compare the address bus bits 7 0 to a logic 1 or logic 0 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 19 3 7 Debug FIFO High Register DBG_FH NOTE All the bits in this register reset to 0 in POR or non end run reset The bits are undefined in end run reset In the case of an end trace to reset whe...

Page 379: ... in this register do not change after reset Address 3010h base 7h offset 3017h Bit 7 6 5 4 3 2 1 0 Read F 7 0 Write Reset 0 0 0 0 0 0 0 0 DBG_FL field descriptions Field Description F 7 0 FIFO Low Data Bits The FIFO Low data bits contain the least significant byte of data in the FIFO When reading FIFO words read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the FIFO pointers to...

Page 380: ...ield Description 7 RWAEN Read Write Comparator A Enable Bit The RWAEN bit controls whether read or write comparison is enabled for Comparator A 0 Read Write is not used in comparison 1 Read Write is used in comparison 6 RWA Read Write Comparator A Value Bit The RWA bit controls whether read or write is used in compare for Comparator A The RWA bit is not used if RWAEN 0 0 Write cycle will be matche...

Page 381: ...her read or write comparison is enabled for Comparator B In full modes RWAEN and RWA are used to control comparison of R W and RWBEN is ignored 0 Read Write is not used in comparison 1 Read Write is used in comparison 6 RWB Read Write Comparator B Value Bit The RWB bit controls whether read or write is used in compare for Comparator B The RWB bit is not used if RWBEN 0 In full modes RWAEN and RWA ...

Page 382: ...Field Description 7 RWCEN Read Write Comparator C Enable Bit The RWCEN bit controls whether read or write comparison is enabled for Comparator C 0 Read Write is not used in comparison 1 Read Write is used in comparison 6 RWC Read Write Comparator C Value Bit The RWC bit controls whether read or write is used in compare for Comparator C The RWC bit is not used if RWCEN 0 0 Write cycle will be match...

Page 383: ...ated by the internal signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism 0 The information in the corresponding FIFO word is event only data or an unpaged 17 bit CPU address with bit 16 0 1 The information in the corresponding FIFO word is a 17 bit flash address with PPAGE 2 0 in the three most significant bits and CPU address 13 0 in the 14 least significant bits 6 1 Re...

Page 384: ...is reserved This read only field is reserved and always has the value 0 0 LOOP1 Select LOOP1 Capture Mode This bit selects either normal capture mode or LOOP1 capture mode LOOP1 is not used in event only modes 0 Normal operation capture COF events into the capture buffer FIFO 1 LOOP1 capture mode enabled When the conditions are met to store a COF value into the FIFO compare the current COF address...

Page 385: ...egin End Trigger Bit The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO 0 Trigger at end of stored data 1 Trigger before storing data 5 4 Reserved This field is reserved This read only field is reserved and always has the value 0 TRG Trigger Mode Bits The TRG bits select the trigger mode of the DBG module 0000 A only 0001 A or B 0010 A then B 0011 Event only B 0100 A...

Page 386: ...Comparator A did not match 1 Comparator A match 6 BF Trigger B Match Bit The BF bit indicates if Trigger B match condition was met since arming 0 Comparator B did not match 1 Comparator B match 5 CF Trigger C Match Bit The CF bit indicates if Trigger C match condition was met since arming 0 Comparator C did not match 1 Comparator C match 4 1 Reserved This field is reserved This read only field is ...

Page 387: ...able 1 20 shows the correlation between the CNT bits and the amount of valid data in FIFO The CNT will stop after a count to eight even if more data is being stored in the FIFO The CNT bits are cleared when the DBG module is armed and the count is incremented each time a new word is captured into the FIFO The host development system is responsible for checking the value in CNT 3 0 and reading the ...

Page 388: ...control TBC block 19 4 1 1 RWA and RWAEN in full modes In full modes A And B and A And Not B DBG_CAX RWAEN and DBG_CAX RWA are used to select read or write comparisons for both comparators A and B To select write comparisons and the write data bus in Full Modes set DBG_CAX RWAEN 1 and DBG_CAX RWA 0 otherwise read comparisons and the read data bus will be selected The DBG_CBX RWBEN and DBG_CBX RWB ...

Page 389: ...rs A or B are desired set DBG_T BEGIN 0 to select an end trace run and set the trigger mode to either 0x0 A only or 0x1 A OR B mode There are two types of breakpoint requests supported by the DBG module tag type and force type Tagged breakpoints are associated with opcode addresses and allow breaking just before a specific instruction executes Force breakpoints are not associated with opcode addre...

Page 390: ...main controller for the DBG module Its function is to decide whether data should be stored in the FIFO based on the trigger mode and the match signals from the comparator The TBC also determines whether a request to break the CPU should occur The DBG_C TAG bit controls whether CPU breakpoints are treated as tag type or force type breakpoints The DBG_T TRGSEL bit controls whether a comparator A or ...

Page 391: ...BG_C BRKEN 1 is triggered when the FIFO becomes full Since this FIFO full condition does not correspond to the execution of a tagged instruction it would not make sense to use DBG_C TAG 1 for a begin type trace run 19 4 4 1 Begin and end trigger The definition of begin and end trigger as used in the DBG module are as follows Begin trigger storage in FIFO occurs after the trigger and continues unti...

Page 392: ...t the corresponding flag s in the DBG_S register are set 19 4 4 3 3 A then B In the A then B trigger mode the match condition for A must be met before the match condition for B is compared When the match condition for A or B is met the corresponding flag in the DBG_S register is set 19 4 4 3 4 Event only B In the event only B trigger mode if the match condition for B is met the DBG_S BF flag is se...

Page 393: ...ot B trigger mode if the match condition for A and not B happen on the same bus cycle both the DBG_S AF and DBG_S BF flags are set If a match condition on only A or only not B occur no flags are set For breakpoint tagging operation with an end trigger type trace only matches from comparator A will be used to determine if the breakpoint conditions are met and comparator B matches will be ignored 19...

Page 394: ...er address then force CPU breakpoint 0 0 1 1 Do not use 0 1 0 x Fill FIFO until trigger opcode about to execute no CPU breakpoint keep running 0 1 1 0 0 1 1 1 Fill FIFO until trigger opcode about to execute trigger causes CPU breakpoint 1 0 0 x Start FIFO at trigger address No CPU breakpoint keep running 1 0 1 0 Start FIFO at trigger address force CPU breakpoint when FIFO full 1 0 1 1 1 1 0 x Star...

Page 395: ...rmed in the begin trigger mode data is not stored in the FIFO until the trigger condition is met Once the trigger condition is met the DBG module will remain armed until 8 words are stored in the FIFO If the core_cof 1 signal becomes asserted the current address is stored in the FIFO If the core_cof 0 signal becomes asserted the address registered during the previous last cycle is decremented by t...

Page 396: ...is called profile mode 19 4 6 Interrupt priority When DBG_T TRGSEL is set and the DBG module is armed to trigger on begin or end trigger types a trigger is not detected in the condition where a pending interrupt occurs at the same time that a target address reaches the top of the instruction pipe In these conditions the pending interrupt has higher priority and code execution switches to the inter...

Page 397: ...n on most DBG control and status bits is overridden so a host development system can read out the results of the trace run after the MCU has been reset In all other cases including POR the DBG module controls are initialized to start a begin trace run starting from when the reset vector is fetched The conditions for the default begin trace run are DBG_CAX 0x00 DBG_CAH 0xFF DBG_CAL 0xFE so comparat...

Page 398: ...Resets MC9S08PA4 Reference Manual Rev 5 08 2017 398 NXP Semiconductors ...

Page 399: ...Changes between revision 5 and 4 Table A 1 Changes between revision 5 and 4 Chapter Description Through out the book Added a new package of 8 pin DFN MC9S08PA4 Reference Manual Rev 5 08 2017 NXP Semiconductors 399 ...

Page 400: ...MC9S08PA4 Reference Manual Rev 5 08 2017 400 NXP Semiconductors ...

Page 401: ...bility including without limitation consequential or incidental damages Typical parameters that may be provided in NXP data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customerʼs technical experts NXP does not convey any license under i...

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