NXP Semiconductors MC9S08PA4, Reference Manual

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19.3.16 Debug Count Status Register (DBG_CNT)
NOTE
All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the
CNT[3:0] bits do not change after reset.
Address: 3010h base + Fh offset = 301Fh
Bit 7 6 5 4 3 2 1 0
Read 0 CNT
Write
Reset 0 0 0 0 0 0 0 0
DBG_CNT field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CNT FIFO Valid Count Bits
The CNT bits indicate the amount of valid data stored in the FIFO. Table 1-20 shows the correlation
between the CNT bits and the amount of valid data in FIFO. The CNT will stop after a count to eight even
if more data is being stored in the FIFO. The CNT bits are cleared when the DBG module is armed, and
the count is incremented each time a new word is captured into the FIFO. The host development system is
responsible for checking the value in CNT[3:0] and reading the correct number of words from the FIFO
because the count does not decrement as data is read out of the FIFO at the end of a trace run.
0000 No data valid.
0001 1 word valid.
0010 2 words valid.
0011 3 words valid.
0100 4 words valid.
0101 5 words valid.
0110 6 words valid.
0111 7 words valid.
1000 8 words valid.
Chapter 19 Debug module (DBG)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 387