NXP Semiconductors MC9S08PA4, Reference Manual

Page: 298 / 401

15.2.5 Analog Channel Inputs (ADx)
The ADC module supports up to 24 separate analog inputs. An input is selected for
conversion through the ADCH channel select bits.
ADC Control Registers
ADC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
10 Status and Control Register 1 (ADC_SC1) 8 R/W 1Fh 15.3.1/298
11 Status and Control Register 2 (ADC_SC2) 8 R/W 08h 15.3.2/300
12 Status and Control Register 3 (ADC_SC3) 8 R/W 00h 15.3.3/301
13 Status and Control Register 4 (ADC_SC4) 8 R/W 00h 15.3.4/302
14 Conversion Result High Register (ADC_RH) 8 R 00h 15.3.5/303
15 Conversion Result Low Register (ADC_RL) 8 R 00h 15.3.6/304
16 Compare Value High Register (ADC_CVH) 8 R/W 00h 15.3.7/305
17 Compare Value Low Register (ADC_CVL) 8 R/W 00h 15.3.8/305
30AC Pin Control 1 Register (ADC_APCTL1) 8 R/W 00h 15.3.9/306
15.3.1 Status and Control Register 1 (ADC_SC1)
This section describes the function of the ADC status and control register (ADC_SC1).
Writing ADC_SC1 aborts the current conversion and initiates a new conversion (if the
ADCH bits are equal to a value other than all 1s).
When FIFO is enabled, the analog input channel FIFO is written via ADCH. The analog
input channel queue must be written to ADCH continuously. The resulting FIFO follows
the order in which the analog input channel is written. The ADC will start conversion
when the input channel FIFO is fulfilled at the depth indicated by the
ADC_SC4[AFDEP]. Any write 0x1F to these bits will reset the FIFO and stop the
conversion if it is active.
Address: 10h base + 0h offset = 10h
Bit 7 6 5 4 3 2 1 0
Read COCO
AIEN ADCO ADCH
Write
Reset
0 0 0 1 1 1 1 1
15.3
ADC Control Registers
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
298 NXP Semiconductors