NXP Semiconductors MC9S08PA4, Reference Manual

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Table 15-2. Total conversion time vs. control conditions (continued)
Conversion type ADICLK ADLSMP Max total conversion time
Single or first continuous 10-bit or 12-bit 11 0 5 µs + 23 ADCK + 5 bus clock cycles
Single or first continuous 8-bit 11 1 5 µs + 40 ADCK + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit 11 1 5 µs + 43 ADCK + 5 bus clock cycles
Subsequent continuous 8-bit;
f
BUS
> f
ADCK
xx 0 17 ADCK cycles
Subsequent continuous 10-bit or 12-bit;
f
BUS
> f
ADCK
xx 0 20 ADCK cycles
Subsequent continuous 8-bit;
f
BUS
> f
ADCK
/11
xx 1 37 ADCK cycles
Subsequent continuous 10-bit or 12-bit;
f
BUS
> f
ADCK
/11
xx 1 40 ADCK cycles
The maximum total conversion time is determined by the selected clock source and the
divide ratio. The clock source is selectable by the ADC_SC3[ADICLK] bits, and the
divide ratio is specified by the ADC_SC3[ADIV] bits. For example, in 10-bit mode, with
the bus clock selected as the input clock source, the input clock divide-by-1 ratio
selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion
as given below:
The number of bus cycles at 8 MHz is:
Note
The ADCK frequency must be between f
ADCK
minimum and
f
ADCK
maximum to meet ADC specifications.
15.4.5 Automatic compare function
The compare function can be configured to check for an upper or lower limit. After the
input is sampled and converted, the result is added to the two's complement of the
compare value (ADC_CVH and ADC_CVL). When comparing to an upper limit
(ADC_SC2[ACFGT] = 1), if the result is greater-than or equal-to the compare value,
ADC_SC1[COCO] is set. When comparing to a lower limit (ADC_SC2[ACFGT] = 0), if
Functional description
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
312 NXP Semiconductors