NXP Semiconductors MC9S08PA4, Reference Manual

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17.3.3 Clock source
The watchdog counter has four clock source options selected by programming
CS2[CLK]:
• bus clock
• internal Low-Power Oscillator (LPO) running at approximately 1 kHz (This is the
default source.)
• internal 32 kHz clock
• external clock
The options allow software to select a clock source independent of the bus clock for
applications that need to meet more robust safety requirements. Using a clock source
other than the bus clock ensures that the watchdog counter continues to run if the bus
clock is somehow halted; see
Backup reset .
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
CS2[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog
counter.
The following table summarizes the different watchdog timeout periods available.
Table 17-1. Watchdog timeout availability
Reference clock Prescaler Watchdog time-out availability
Internal ~1 kHz (LPO)
Pass through ~1 ms–65.5 s
1
÷256 ~256 ms–16,777 s
Internal ~32 kHz
Pass through ~31.25 µs–2.048 s
÷256 ~8 ms–524.3 s
1 MHz (from bus or external)
Pass through 1 µs–65.54 ms
÷256 256 µs–16.777 s
20 MHz (from bus or external)
Pass through 50 ns–3.277 ms
÷256 12.8 µs–838.8 ms
1. The default timeout value after reset is approximately 4 ms.
NOTE
When the programmer switches clock sources during
reconfiguration, the watchdog hardware holds the counter at
zero for 2.5 periods of the previous clock source and 2.5
periods of the new clock source after the configuration time
period (128 bus clocks) ends. This delay ensures a smooth
transition before restarting the counter with the new
configuration.
Chapter 17 Watchdog (WDOG)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 347