NXP Semiconductors MC9S08PA4, Reference Manual

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If hardware trigger mode is enabled, the next analog is fetched from analog input channel
FIFO only when this conversion completes, its result is stored in the result FIFO, and the
next hardware trigger is fed to ADC module. When all conversions set in the analog input
channel FIFO completes, the ADC_SC1[COCO] bit is set and an interrupt request will be
submitted to CPU if the ADC_SC1[AIEN] bit is set.
In single conversion in which ADC_SC1[ADCO] bit is clear, the ADC stops conversions
when ADC_SC1[COCO] bit is set until the channel FIFO is fulfilled again or new
hardware trigger occur.
The FIFO also provides scan mode to simplify the dummy work of input channel FIFO.
When the ADC_SC4[ASCANE] bit is set in FIFO mode, the FIFO will always use the
first dummied channel in spite of the value in the input channel FIFO. The ADC
conversion start to work in FIFO mode as soon as the first channel is dummied. The
following write operation to the input channel FIFO will cover the first channel element
in this FIFO. In scan FIFO mode, the ADC_SC1[COCO] bit is set when the result FIFO
is fulfilled according to the depth indicated by the ADC_SC4[AFDEP] bits.
In continuous conversion in which the ADC_SC1[ADCO] bit is set, the ADC starts next
conversion immediately when all conversions are completed. ADC module will fetch the
analog input channel from the beginning of analog input channel FIFO.
Chapter 15 Analog-to-digital converter (ADC)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 315