Connector Pin Assignments A-11
IDE INTERFACE CONNECTORS
All signal levels in the IDE interface are TTL compatible. A logic 1 is a signal whose
voltage level is between 2.0 and 5.0 V. A logic 0 is a signal measuring between 0.00 V and
0.70 V.
The two system board IDE connectors (J2 and J3) are physically identical. Electrically the
primary PCI/IDE bus IDE connector is faster and the secondary PCI/IDE connector is
slower. Table A-10 provides the IDE pin assignments. All signals on the Host interface have
the prefix HOST. All negatively active signals are further prefixed with a “-” designation.
All positively active signals are prefixed with a “+” designation.
Table A-10 PCI/IDE Connector Pin Assignments
Pin
Signal
Pin
Signal
01
HOST RESET
02
GND
03
HOST DATA 7
04
HOST DATA 8
05
HOST DATA 6
06
HOST DATA 9
07
HOST DATA 5
08
HOST DATA 10
09
HOST DATA 4
10
HOST DATA 11
11
HOST DATA 3
12
HOST DATA 12
13
HOST DATA 2
14
HOST DATA 13
15
HOST DATA 1
16
HOST DATA 14
17
HOST DATA 0
18
HOST DATA 15
19
GND
20
KEY
21
No connection
22
GND
23
HOST IOW
24
GND
25
HOST IOR
26
GND
27
HDCHRDY
28
BALE
29
No connection
30
GND
31*
IRQ
32
I/OCS16
33
ADDRESS1
34
No connection
35
ADDRESS0
36
ADDRESS2
37
CHIP-SELECTO
38
CHIP-SELECT1
39
DISK ACTIVE
40
GND
*The Primary PCI/IDE connector uses IRQ14.
