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410

CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (

PD78078Y Subseries)

(3) Slave wait release (slave reception)

The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify

When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to

SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot

start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0

(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the program

as shown in Figure 18-26 to receive data correctly.

For these timings, see Figure 18-22.

Figure 18-26. Slave Wait Release (Reception)

(4) Reception completion of slave

During processing of reception completion by a slave device, confirm the statuses of CMDD and COI (if

CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of

data is sent from the master device, the slave device cannot determine whether the start condition signal or

the data will be sent from the master. This may disable use of the wake-up function.

Writing

data

to SIO0

Setting

CSIIF0

Setting
ACKD

Serial transmission

ACK

P27

output
latch 1

Setting

CSIIF0

ACK

output

Serial reception

Write

FFH

to SIO0

P27

output
latch 0

Wait

release

Software operation

Hardware operation

SCL

Software operation

Hardware operation

Transfer line

Master device operation

Slave device operation

SDA0 (SDA1)

Summary of Contents for PD78076

Page 1: ...78078 µPD78P078 µPD78076Y µPD78078Y µPD78P078Y µPD78078 78078Y Subseries 8 bit Single chip Microcontrollers Document No U10641EJ4V0UM00 4th edition Date Published December 1997 N 1994 User s Manual Printed in Japan ...

Page 2: ...2 MEMO ...

Page 3: ...ng bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause o...

Page 4: ...r intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in ...

Page 5: ...etherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary from countr...

Page 6: ... been added to 17 1 18 1 Serial Interface Channel 0 Functions p 323 374 Precautions have been added to 17 3 2 18 3 2 Serial Operating Mode Register 0 CSIM0 p 372 Note about the BSYE flag in Figure 17 5 Serial Bus Interface Control Register Format has been changed p 336 Precautions have been added to 17 4 3 2 a Bus release signal REL b Command signal CMD p 449 19 4 3 3 d Busy control option e Busy ...

Page 7: ...Manual This manual Instructions Pin functions CPU functions Internal block functions Instruction set Interrupt Explanation of each instruction Other on chip peripheral functions How to Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontroller When you want to understand the functions in general Read this manual in the order of ...

Page 8: ...pter 9 8 Bit Timer Event Counters 1 and 2 Chapter 10 8 Bit Timer Event Counters 5 and 6 Chapter 11 Watch Timer Chapter 12 Watchdog Timer Chapter 13 Clock Output Control Circuit Chapter 14 Buzzer Output Control Circuit Chapter 15 A D Converter Chapter 16 D A Converter Chapter 17 Serial Interface Channel 0 µPD78078 Subseries Chapter 18 Serial Interface Channel 0 µPD78078Y Subseries Chapter 19 Serial...

Page 9: ...mal xxxxH Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Related documents for this subseries Document name Document No English Japanese µPD78078 78078Y Subseries User s Manual This manual U10641J µPD78076 78078 Data Sheet U10167E U10167J µPD78P078 Data Sheet U10168E U10168J µPD78076Y 78078Y...

Page 10: ...er PC 9800 Series MS DOSTM Based EEU 1291 EEU 704 PG 1500 Controller IBM PC Series PC DOSTM Based U10540E EEU 5008 IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 78K0 R EX1 To be prepared To be prepared IE 78078 NS EM1 To be prepared To be prepared IE 78078 R EM U10775E U10775J EP 78064 EEU 1469 EEU 934 SM78K0 System Simulator WindowsTM Based Reference U1018...

Page 11: ...r Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability Quality Control System U10983E U10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E C11892J Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcomputer Product Series Guide U11416J Caution Th...

Page 12: ...12 MEMO ...

Page 13: ...58 2 7 Block Diagram 60 2 8 Outline of Function 61 2 9 Mask Options 63 2 10 Differences with µPD78054Y Subseries 63 CHAPTER 3 PIN FUNCTION µPD78078 SUBSERIES 65 3 1 Pin Function List 65 3 1 1 Normal operating mode pins 65 3 1 2 PROM programming mode pins µPD78P078 only 69 3 2 Description of Pin Functions 70 3 2 1 P00 to P07 Port 0 70 3 2 2 P10 to P17 Port 1 70 3 2 3 P20 to P27 Port 2 71 3 2 4 P30 ...

Page 14: ...rt 4 90 4 2 6 P50 to P57 Port 5 91 4 2 7 P60 to P67 Port 6 91 4 2 8 P70 to P72 Port 7 92 4 2 9 P80 to P87 Port 8 92 4 2 10 P90 to P96 Port 9 93 4 2 11 P100 to P103 Port 10 93 4 2 12 P120 to P127 Port 12 93 4 2 13 P130 and P131 Port 13 94 4 2 14 AVREF0 94 4 2 15 AVREF1 94 4 2 16 AVDD 94 4 2 17 AVSS 94 4 2 18 RESET 94 4 2 19 X1 and X2 94 4 2 20 XT1 and XT2 94 4 2 21 VDD 95 4 2 22 VSS 95 4 2 23 VPP µ...

Page 15: ...ister indirect addressing 127 5 4 7 Based addressing 128 5 4 8 Based indexed addressing 129 5 4 9 Stack addressing 129 CHAPTER 6 PORT FUNCTIONS 131 6 1 Port Functions 131 6 2 Port Configuration 136 6 2 1 Port 0 136 6 2 2 Port 1 138 6 2 3 Port 2 µPD78078 Subseries 139 6 2 4 Port 2 µPD78078Y Subseries 141 6 2 5 Port 3 143 6 2 6 Port 4 144 6 2 7 Port 5 145 6 2 8 Port 6 146 6 2 9 Port 7 148 6 2 10 Por...

Page 16: ...8 3 16 Bit Timer Event Counter Configuration 185 8 4 16 Bit Timer Event Counter Control Registers 190 8 5 16 Bit Timer Event Counter Operations 198 8 5 1 Interval timer operations 198 8 5 2 PWM output operations 200 8 5 3 PPG output operations 203 8 5 4 Pulse width measurement operations 204 8 5 5 External event counter operation 211 8 5 6 Square wave output operation 213 8 5 7 One shot pulse outp...

Page 17: ...2 1 Watchdog Timer Functions 275 12 2 Watchdog Timer Configuration 277 12 3 Watchdog Timer Control Registers 278 12 4 Watchdog Timer Operations 281 12 4 1 Watchdog timer operation 281 12 4 2 Interval timer operation 282 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 283 13 1 Clock Output Control Circuit Functions 283 13 2 Clock Output Control Circuit Configuration 284 13 3 Clock Output Function Control R...

Page 18: ...l 0 Operations 380 18 4 1 Operation stop mode 380 18 4 2 3 wire serial I O mode operation 381 18 4 3 2 wire serial I O mode operation 385 18 4 4 I2 C bus mode operation 390 18 4 5 Cautions on use of I2 C bus mode 408 18 4 6 Restrictions in I2 C bus mode 411 18 4 7 SCK0 SCL P27 pin output manipulation 413 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 415 19 1 Serial Interface Channel 1 Functions 415 19 2 S...

Page 19: ... 523 22 5 2 Test input signal acknowledge operation 525 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 527 23 1 External Device Expansion Functions 527 23 2 External Device Expansion Function Control Register 531 23 3 External Device Expansion Function Timing 534 23 3 1 Timings in multiplexed bus mode 534 23 3 2 Timings in separate bus mode 539 CHAPTER 24 STANDBY FUNCTION 545 24 1 Standby Function ...

Page 20: ...rs and description methods 582 28 1 2 Description of operation column 583 28 1 3 Description of flag operation column 583 28 2 Operation List 584 28 3 Instructions Listed by Addressing Type 592 APPENDIX A DIFFERENCES BETWEEN µPD78078 78075B SUBSERIES AND µPD78070A 597 APPENDIX B DEVELOPMENT TOOLS 599 B 1 Language Processing Software 602 B 2 PROM Writing Tools 604 B 2 1 Hardware 604 B 2 2 Software ...

Page 21: ... of P10 to P17 138 6 5 Block Diagram of P20 P21 P23 to P26 139 6 6 Block Diagram of P22 and P27 140 6 7 Block Diagram of P20 P21 P23 to P26 141 6 8 Block Diagram of P22 and P27 142 6 9 Block Diagram of P30 to P37 143 6 10 Block Diagram of P40 to P47 144 6 11 Block Diagram of Falling Edge Detection Circuit 144 6 12 Block Diagram of P50 to P57 145 6 13 Block Diagram of P60 to P63 147 6 14 Block Diag...

Page 22: ...rval Timer Configuration Diagram 199 8 12 Interval Timer Operation Timings 199 8 13 Control Register Settings for PWM Output Operation 201 8 14 Example of D A Converter Configuration with PWM Output 202 8 15 TV Tuner Application Circuit Example 202 8 16 Control Register Settings for PPG Output Operation 203 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and On...

Page 23: ...imer Mode Control Register 1 Format 233 9 6 8 Bit Timer Output Control Register Format 234 9 7 Port Mode Register 3 Format 235 9 8 Interval Timer Operation Timing 236 9 9 External Event Counter Operation Timings with Rising Edge Specified 239 9 10 Timing of Square Wave Output Operation 241 9 11 Interval Timer Operation Timing 242 9 12 External Event Counter Operation Timings with Rising Edge Speci...

Page 24: ...mote Controlled Output Application Example 283 13 2 Clock Output Control Circuit Block Diagram 284 13 3 Timer Clock Select Register 0 Format 286 13 4 Port Mode Register 3 Format 287 14 1 Buzzer Output Control Circuit Block Diagram 289 14 2 Timer Clock Select Register 2 Format 291 14 3 Port Mode Register 3 Format 292 15 1 A D Converter Block Diagram 294 15 2 A D Converter Mode Register Format 297 1...

Page 25: ... and CMDD Operations Slave 344 17 22 ACKT Operation 345 17 23 ACKE Operations 346 17 24 ACKD Operations 347 17 25 BSYE Operation 347 17 26 Pin Configuration 350 17 27 Address Transmission from Master Device to Slave Device WUP 1 352 17 28 Command Transmission from Master Device to Slave Device 353 17 29 Data Transmission from Master Device to Slave Device 354 17 30 Data Transmission from Slave Dev...

Page 26: ...face Channel 1 Block Diagram 416 19 2 Timer Clock Select Register 3 Format 418 19 3 Serial Operation Mode Register 1 Format 419 19 4 Automatic Data Transmit Receive Control Register Format 420 19 5 Automatic Data Transmit Receive Interval Specify Register Format 421 19 6 3 Wire Serial I O Mode Timings 427 19 7 Circuit of Switching in Transfer Bit Order 428 19 8 Basic Transmission Reception Mode Op...

Page 27: ...B When Receive Operation is Stopped and Whether Interrupt Request INTSR is Generated or Not 483 20 12 3 Wire Serial I O Mode Timing 489 20 13 Circuit of Switching in Transfer Bit Order 490 20 14 Receive Completion Interrupt Request Generation Timing ISRM 1 491 20 15 Period that Reading Receive Buffer Register is Prohibited 492 21 1 Real time Output Port Block Diagram 495 21 2 Real time Output Buff...

Page 28: ...etch from External Memory in Separate Bus Mode 540 23 10 External Memory Read Timing in Separate Bus Mode 541 23 11 External Memory Write Timing in Separate Bus Mode 542 23 12 External Memory Read Modify Write Timing in Separate Bus Mode 543 24 1 Oscillation Stabilization Time Select Register Format 546 24 2 HALT Mode Released by Interrupt Request Generation 548 24 3 HALT Mode Released by RESET In...

Page 29: ...27 3 Page Program Mode Flowchart 574 27 4 Page Program Mode Timing 575 27 5 Byte Program Mode Flowchart 576 27 6 Byte Program Mode Timing 577 27 7 PROM Read Timing 578 B 1 Development Tool Configuration 600 B 2 TGC 100SDW Drawing For Reference Only 610 B 3 EV 9200GF 100 Drawing For Reference Only 611 B 4 EV 9200GF 100 Recommended Footprints For Reference Only 612 ...

Page 30: ...PU Clock and Minimum Instruction Execution Time 169 7 3 Maximum Time Required for CPU Clock Switchover 178 8 1 Timer Event Counter Operations 182 8 2 16 Bit Timer Event Counter Interval Times 183 8 3 16 Bit Timer Event Counter Square Wave Output Ranges 184 8 4 16 Bit Timer Event Counter Configuration 185 8 5 INTP0 TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge 188 8 6 16 Bit Timer Event C...

Page 31: ...imes 276 12 3 Watchdog Timer Configuration 277 12 4 Watchdog Timer Runaway Detection Time 281 12 5 Interval Timer Interval Time 282 13 1 Clock Output Control Circuit Configuration 284 14 1 Buzzer Output Control Circuit Configuration 289 15 1 A D Converter Configuration 293 16 1 D A Converter Configuration 310 17 1 Differences between Channels 0 1 and 2 315 17 2 Serial Interface Channel 0 Configura...

Page 32: ... 523 22 6 Flags Corresponding to Test Input Signals 523 23 1 Pin Functions in External Memory Expansion Mode 527 23 2 State of Port 4 to Port 6 Pins in External Memory Expansion Mode 527 23 3 Pin Functions in Separate Bus Mode 528 23 4 State of Port 4 to Port 6 and Port 8 Pins in Separate Bus Mode 528 23 5 Values when the Internal Memory Size Switching Register is Reset 532 24 1 HALT Mode Operatin...

Page 33: ...rated 88 I O port pins including eight N ch open drain port pins 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface Three channels 3 wire serial I O SBI 2 wire serial I O mode 1 channel 3 wire serial I O mode automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer Seven channels 16 bit timer event counter 1 channel...

Page 34: ...e pitch 14 x 14 mm resin thickness 1 45 mm Mask ROM µPD78078GC xxx 8EUNote 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm Mask ROM µPD78078GF xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Mask ROM µPD78P078GC 7EA 100 pin plastic QFP Fine pitch 14 x 14 mm resin thickness 1 45 mm One time PROM µPD78P078GC 8EUNote 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thi...

Page 35: ...D78P078GC 7EA 100 pin plastic QFP Fine pitch 14 x 14 mm resin thickness 1 45 mm Standard µPD78P078GC 8EUNote 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm Standard µPD78P078GF 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Standard µPD78P078KL T 100 pin ceramic WQFN 14 x 20 mm Not assured for function evaluation only Note Under development Caution Of the above member...

Page 36: ...perating mode 100 pin plastic QFP Fine pitch 14 x 14 mm resin thickness 1 45 mm µPD78076GC xxx 7EA 78078GC xxx 7EA µPD78P078GC 7EA 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm µPD78076GC xxx 8EUNote 78078GC xxx 8EUNote µPD78P078GC 8EUNote Note Under development ...

Page 37: ... P14 ANI4 P15 ANI5 P16 ANI6 P17 ANI7 AVSS P130 ANO0 P131 ANO1 AVREF1 P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK VSS P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P80 A0 P81 A1 P82 A2 P83 A3 P84 A4 99 98 97 96 95 94 93 92 90 89 8887 86 85 84 83 82 81 8079 78 77 76 91 P12 ANI2 P11 ANI1 P10 ANI0 AV REF0 AV DD P06 INTP6 P05 INTP5 P04 INTP4 P03 INTP3 P02 INTP2 P01 INTP1 TI01 P00...

Page 38: ... P42 AD2 P41 AD1 P40 AD0 P87 A7 P63 P62 P47 AD7 P86 A6 P85 A5 P84 A4 P83 A3 P82 A2 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 93 94 96 98 100 87 90 97 99 81 95 85 P120 RTP0 P121 RTP1 P122 RTP2 P125 RTP5 P126 RTP6 P127 RTP7 IC VPP X2 X1 VDD XT2 XT1 P07 RESET P00 INTP0 TI00 P02 INTP2 P03 INTP3 P04 INTP4 P05 INTP5 P06 INT...

Page 39: ...t 2 P30 to P37 Port 3 P40 to P47 Port 4 P50 to P57 Port 5 P60 to P67 Port 6 P70 to P72 Port 7 P80 to P87 Port 8 P90 to P96 Port 9 P100 to P103 Port 10 P120 to P127 Port 12 P130 P131 Port 13 PCL Programmable Clock RD Read Strobe RESET Reset RTP0 to RTP7 Real time Output Port RxD Receive Data SB0 SB1 Serial Bus SCK0 to SCK2 Serial Clock SI0 to SI2 Serial Input SO0 to SO2 Serial Output STB Strobe TI0...

Page 40: ...nnect to the ground 3 RESET Set to the low level 4 Open Leave open 1 76 L VDD V SS V DD PGM 77 78 79 80 82 83 84 85 86 88 89 91 92 93 94 95 96 98 100 81 87 90 97 99 L L L A9 RESET L Open V DD L Open V PP L 50 49 48 47 46 44 43 42 41 40 38 37 35 34 33 32 31 30 28 26 45 39 36 29 27 A7 A8 A16 A10 A11 A12 A13 V SS A14 A15 OE L A2 A3 A4 A5 A6 A0 A1 L 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ...

Page 41: ...a Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 L 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 L CE OE A15 A14 VSS A13 A12 A11 A10 A16 A8 A6 A5 A4 A3 A2 A1 A0 A7 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 9...

Page 42: ...18FY µPD78014Y 64 pin 64 pin 64 pin Low voltage 1 8 V version of µPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to µPD78002 Added A D to µPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V Enhanced I O and FIP C D of µPD78044F 53 display outputs Enhanced I O and FIP C D of µPD78044H 48 display outputs µPD780964 µPD780924 64 ...

Page 43: ...o 32 K 2 7 V µPD780001 8 K 1 ch 39 µPD78002 8 K to 16 K 1 ch 53 µPD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter µPD780988 32 K to 60 K 3 ch Note 1 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control µPD780964 8 K to 32 K Note 2 2 ch UART 2 ch 2 7 V µPD780924 8 ch FIP µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V driving µPD780228 48 K to 60 K 3 ch 1 ch 72 4 5 V µPD78044H 32 K to 48 K 2 ch 1 c...

Page 44: ...70 to P72 Port 8 P80 to P87 Port 9 P90 to P96 Port 10 P100 to P103 Port 12 P120 to P127 Port 13 P130 P131 Real Time Output Port RTP0 P120 to RTP7 P127 System Control AD0 P40 to AD7 P47 A0 P80 to A7 P87 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 VDD VSS IC VPP RAM 78K 0 CPU Core ROM 8 bit TIMER Event Counter 5 8 bit TIMER Event Counter 6 Watch Timer Serial Interface 2...

Page 45: ...ire serial I O mode selection possible 1 channel 3 wire serial I O mode Maximum 32 byte on chip automatic transmit receive function 1 channel 3 wire serial I O UART mode selection possible 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 4 channels Watch timer 1 channel Watchdog timer 1 channel Timer output 5 outputs 14 bit PWM output enable 1 8 bit PWM output enable ...

Page 46: ... 1 Test input Internal 1 External 1 Power supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Package 100 pin plastic QFP Fine pitch 14 x 14 mm resin thickness 1 45 mm 100 pin plastic LQFPNote Fine pitch 14 x 14 mm resin thickness 1 4 mm 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm 100 pin ceramic WQFN 14 x 20 mm µPD78P078 only Note Under development ...

Page 47: ...8078 Subseries is upward compatible with the µPD78054 Subseries The differences between the two subseries are shown in the table below The functions and specifications other than those shown in this table are common to these two series Table 1 2 Differences between µPD78078 Subseries and µPD78054 Subseries Subseries µPD78054 Subseries µPD78078 Subseries Item No of I O ports 69 88 8 bit timer event...

Page 48: ...48 MEMO ...

Page 49: ...ssible in all address spaces Multiply and divide instructions incorporated 88 I O port pins including eight N ch open drain port pins 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface Three channels 3 wire serial I O 2 wire serial I O I2 C bus mode 1 channel 3 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UAR...

Page 50: ...076YGF xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Mask ROM µPD78078YGC xxx 8EUNote 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm Mask ROM µPD78078YGF xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Mask ROM µPD78P078YGC 8EUNote 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm One time PROM µPD78P078YGF 3BA 100 pin plastic QFP 14...

Page 51: ...ch 14 x 14 mm resin thickness 1 4 mm Standard µPD78P078YGF 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Standard µPD78P078YKL T 100 pin ceramic WQFN 14 x 20 mm Not assured for function evaluation only Note Under development Caution Of the above members the following device with the suffix KL T should be used only for experiment or function evaluation because it is not intended for use...

Page 52: ...78078Y SUBSERIES 2 5 Pin Configuration Top View 1 Normal operating mode 100 pin plastic LQFP Fine pitch 14 x 14 mm resin thickness 1 4 mm µPD78076YGC xxx 8EUNote 78078YGC xxx 8EUNote µPD78P078YGC 8EUNote Note Under development ...

Page 53: ...1 SDA1 P27 SCK0 SCL P80 A0 P81 A1 P82 A2 P83 A3 P84 A4 99 98 97 96 95 94 93 92 90 89 8887 86 85 84 83 82 81 8079 78 77 76 91 P12 ANI2 P11 ANI1 P10 ANI0 AV REF0 AV DD P06 INTP6 P05 INTP5 P04 INTP4 P03 INTP3 P02 INTP2 P01 INTP1 TI01 P00 INTP0 TI00 RESET XT1 P07 XT2 V DD X1 X2 IC V PP P127 RTP7 P126 RTP6 P125 RTP5 P124 RTP4 P123 RTP3 26 27 28 29 30 31 32 33 34 36 37 3839 40 41 42 43 44 45 4647 48 49 ...

Page 54: ...X2 X1 VDD XT2 XT1 P07 RESET P00 INTP0 TI00 P02 INTP2 P03 INTP3 P04 INTP4 P05 INTP5 P06 INTP6 AVDD AVREF0 P10 ANI0 P123 RTP3 P124 RTP4 P01 INTP1 TI01 P11 ANI1 P12 ANI2 P13 ANI3 P14 ANI4 P15 ANI5 P17 ANI7 AV SS P130 ANO0 P131 ANO1 AV REF1 P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK V SS P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P80 A0 P81 A1 P96 P95 P94 P93 P...

Page 55: ... 3 P40 to P47 Port 4 P50 to P57 Port 5 P60 to P67 Port 6 P70 to P72 Port 7 P80 to P87 Port 8 P90 to P96 Port 9 P100 to P103 Port 10 P120 to P127 Port 12 P130 P131 Port 13 PCL Programmable Clock RD Read Strobe RESET Reset RTP0 to RTP7 Real time Output Port RxD Receive Data SB0 SB1 Serial Bus SCK0 to SCK2 Serial Clock SCL Serial Clock SDA0 SDA1 Serial Data SI0 to SI2 Serial Input SO0 to SO2 Serial O...

Page 56: ...Connect to the ground 3 RESET Set to the low level 4 Open Leave open 1 76 L VDD V SS V DD PGM 77 78 79 80 82 83 84 85 86 88 89 91 92 93 94 95 96 98 100 81 87 90 97 99 L L L A9 RESET L Open V DD L Open V PP L 50 49 48 47 46 44 43 42 41 40 38 37 35 34 33 32 31 30 28 26 45 39 36 29 27 A7 A8 A16 A10 A11 A12 A13 V SS A14 A15 OE L A2 A3 A4 A5 A6 A0 A1 L 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2...

Page 57: ... Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 L 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 L CE OE A15 A14 VSS A13 A12 A11 A10 A16 A8 A6 A5 A4 A3 A2 A1 A0 A7 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 ...

Page 58: ...8FY µPD78014Y 64 pin 64 pin 64 pin Low voltage 1 8 V version of µPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to µPD78002 Added A D to µPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V Enhanced I O and FIP C D of µPD78044F 53 display outputs Enhanced I O and FIP C D of µPD78044H 48 display outputs µPD780964 µPD780924 64 p...

Page 59: ...ire time division UART 1 ch µPD78058FY 48K to 60K 3 wire 2 wire I2 C 1 ch 69 2 7 V µPD78054Y 16K to 60K 3 wire with automatic transmit receive function 1 ch 2 0 V 3 wire UART 1 ch µPD780034Y 8K to 32K UART 1 ch 51 1 8 V 3 wire 1 ch µPD780024Y I2 C bus supports multi master 1 ch µPD78018FY 8K to 60K 3 wire 2 wire I2 C 1 ch 53 3 wire with automatic transmit receive function 1 ch µPD78014Y 8K to 32K ...

Page 60: ...P72 Port 8 P80 to P87 Port 9 P90 to P96 Port 10 P100 to P103 Port 12 P120 to P127 Port 13 P130 P131 Real Time Output Port RTP0 P120 to RTP7 P127 System Control AD0 P40 to AD7 P47 A0 P80 to A7 P87 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 VDD VSS IC VPP RAM 78K 0 CPU Core ROM 8 bit TIMER Event Counter 5 8 bit TIMER Event Counter 6 Watch Timer Serial Interface 2 D A C...

Page 61: ... bus mode selection 1 channel possible 3 wire serial I O mode maximum 32 byte on chip automatic transmit receive function 1 channel 3 wire serial I O UART mode selection possible 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 4 channels Watch timer 1 channel Watchdog timer 1 channel Timer output 5 outputs 14 bit PWM output enable 1 8 bit PWM output enable 2 Clock ou...

Page 62: ...skable Internal 1 Software Internal 1 Test input Internal 1 External 1 Power supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Package 100 pin plastic LQFPNote Fine pitch 14 x 14 mm resin thickness 1 4 mm 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm 100 pin ceramic WQFN 14 x 20 mm µPD78P078Y only Note Under development ...

Page 63: ...th µPD78054Y Subseries The µPD78078Y Subseries is upward compatible with the µPD78054Y Subseries The differences between the two subseries are shown in the table below The functions and specifications other than those shown in this table are common to these two series Table 2 2 Differences between µPD78078Y Subseries and µPD78054Y Subseries Subseries µPD78054Y Subseries µPD78078Y Subseries Item No...

Page 64: ...64 MEMO ...

Page 65: ...put output mode can be specified bit wise Input ANI0 to ANI7 If used as input port an on chip pull up resistor can be connected by softwareNote 2 P20 SI1 P21 SO1 P22 Port 2 SCK1 P23 Input 8 bit input output port STB P24 output Input output mode can be specified bit wise BUSY P25 If used as an input port an on chip pull up resistor can be connected by SI0 SB0 P26 software SO0 SB1 P27 SCK0 Notes 1 W...

Page 66: ... bit wise If used as an input port an on chip pull up resistor can be connected by software P61 P62 Port 6 P63 Input 8 bit input output port P64 output Input output mode can be If used as an input port an on chip Input RD P65 specified bit wise pull up resistor can be connected WR P66 by software WAIT P67 ASTB Port 7 Input 3 bit input output port output Input output mode can be specified bit wise ...

Page 67: ...be connected P96 by software Port 10 Input 4 bit input output port output Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software Port 12 Input 8 bit input output port output Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software Port 13 Input 2 bit input out...

Page 68: ... interface serial data input Input P70 SI2 TxD Output Asynchronous serial interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 External count clock input to 16 bit timer TM0 P00 INTP0 TI01 Capture trigger signal input to capture register CR00 P01 INTP1 TI1 External count clock input to 8 bit timer TM1 P33 TI2 External count cloc...

Page 69: ...nput AVDD A D converter analog power supply Connect to VDD AVSS A D converter D A converter ground potential Connect to VSS RESET Input System reset input X1 Input X2 XT1 Input Input P07 XT2 VDD Positive power supply High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Connect directly to VSS 3 1 2 PROM prog...

Page 70: ... INTP6 INTP0 to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTP0 or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TI00 Pin for external count clock input to 16 bit timer event counter c TI01 Pin for capture trigger signal to capture register CR00 of ...

Page 71: ...ull up resistor option register L PUOL 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions a SI0 SI1 SO0 SO1 Serial interface serial data input output pins b SCK0 and SCK1 Serial interface serial clock input output pins c SB0 and SB1 NEC standard serial bus interface input output pins d BUSY ...

Page 72: ... bit timer event counter b TO0 to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 3 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These ports function ...

Page 73: ...67 Port 6 These are 8 bit input output ports Besides serving as input output ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 PM6 P60 to P63 are N ch...

Page 74: ...al interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting refer to the operation mode setting list in Table 20 2 Serial Interface Channel 2 3 2 9 P80 to P87 Port 8 These are 8 bit input output por...

Page 75: ...as input or output ports with port mode register 10 PM10 When they are used as input ports on chip pull up resistors can be connected by defining the pull up resistor option register H PUOH 2 Control mode These ports function as timer input output a TI5 and TI6 Pins for external count clock input to 8 bit timer event counter b TO5 to TO6 Pins for timer output 3 2 12 P120 to P127 Port 12 These are ...

Page 76: ...in to VSS Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 3 2 14 AVREF0 A D converter reference voltage input pin When A D converter is not used connect this pin to VSS 3 2 15 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to VDD 3 2 16 AVDD Analog power supply pin of A D c...

Page 77: ...ask ROM version only The IC Internally Connected pin is provided to set the test mode to check the µPD78078 at delivery Connect it directly to the VSS with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program ma...

Page 78: ...ommended Connection of Unused Pins Circuit Type P00 INTP0 TI00 2 Input Connect to VSS P01 INTP1 TI01 8 A Input Output Connect independently via a resistor P02 INTP2 to VSS P03 INTP3 P04 INTP4 P05 INTP5 P06 INTP6 P07 XT1 16 Input Connect to VDD P10 ANI0 to P17 ANI7 11 Input Output Connect independently via a P20 SI1 8 A resistor to VDD or VSS P21 SO1 5 A P22 SCK1 8 A P23 STB 5 A P24 BUSY 8 A P25 SI...

Page 79: ...via a resistor P65 WR to VDD or VSS P66 WAIT P67 ASTB P70 SI2 RxD 8 A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P80 A0 to P87 A7 5 A P90 to P93 Mask ROM version 13 B Input output Connect independently via a resistor P90 to P93 µPD78P078 13 D to VDD P94 to P96 5 A Input output Connect independently via a resistor P100 TI5 TO5 8 A to VDD or VSS P101 TI6 TO6 P102 P103 5 A P120 RTP0 to P127 RTP7 5 A P130 ANO0...

Page 80: ...gered Input with Hysteresis Characteristics Type 5 E Type 11 Type 10 A Type 8 A pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT open drain output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch P ch comparator N ch input enable VREF Threshold volt...

Page 81: ...pe 13 D output disable VDD N ch IN OUT RD medium breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable VDD VDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch input enable P ch N ch analog output voltage ...

Page 82: ...82 MEMO ...

Page 83: ...tput mode can be specified bit wise Input ANI0 to ANI7 If used as input port an on chip pull up resistor can be connected by softwareNote 2 P20 SI1 P21 SO1 P22 Port 2 SCK1 P23 Input 8 bit input output port STB P24 output Input output mode can be specified bit wise BUSY P25 If used as an input port an on chip pull up resistor can be connected by SI0 SB0 SDA0 P26 software SO0 SB1 SDA1 P27 SCK0 SCL N...

Page 84: ... Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software P61 P62 Port 6 P63 Input 8 bit input output port P64 output Input output mode can be If used as an input port an on chip Input RD P65 specified bit wise pull up resistor can be connected WR P66 by software WAIT P67 ASTB Port 7 Input 3 bit input output port output Input out...

Page 85: ...connected P96 by software Port 10 Input 4 bit input output port output Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software Port 12 Input 8 bit input output port output Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software Port 13 Input 2 bit input output...

Page 86: ...interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 External count clock input to 16 bit timer TM0 P00 INTP0 TI01 Capture trigger signal input to capture register CR00 P01 INTP1 TI1 External count clock input to 8 bit timer TM1 P33 TI2 External count clock input to 8 bit timer TM2 P34 TI5 External count clock input to 8 bit tim...

Page 87: ...ge input AVDD A D converter analog power supply Connect to VDD AVSS A D converter D A converter ground potential Connect to VSS RESET Input System reset input X1 Input X2 XT1 Input Input P07 XT2 VDD Positive power supply High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Connect directly to VSS 4 1 2 PROM ...

Page 88: ...6 INTP0 to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTP0 or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TI00 Pin for external count clock input to 16 bit timer event counter c TI01 Pin for capture trigger signal to capture register CR00 of 16 bi...

Page 89: ...o them by defining the pull up resistor option register L PUOL 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions a SI0 SI1 SO0 SO1 SB0 SB1 SDA0 SDA1 Serial interface serial data input output pins b SCK0 SCK1 SCL Serial interface serial clock input output pins c BUSY Serial interface automat...

Page 90: ...the 8 bit timer event counter b TO0 to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 4 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These ports func...

Page 91: ...P67 Port 6 These are 8 bit input output ports Besides serving as input output ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 PM6 P60 to P63 are N c...

Page 92: ...al interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting refer to the operation mode setting list in Table 20 2 Serial Interface Channel 2 4 2 9 P80 to P87 Port 8 These are 8 bit input output por...

Page 93: ...se as input or output ports with port mode register 10 PM10 When they are used as input ports on chip pull up resistors can be connected by defining the pull up resistor option register H PUOH 2 Control mode These ports function as timer input output a TI5 and TI6 Pins for external clock input to 8 bit timer event counter b TO5 to TO6 Pins for timer output 4 2 12 P120 to P127 Port 12 These are 8 b...

Page 94: ...in to VSS Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 4 2 14 AVREF0 A D converter reference voltage input pin When A D converter is not used connect this pin to VSS 4 2 15 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to VDD 4 2 16 AVDD Analog power supply pin of A D c...

Page 95: ...Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the µPD78078Y at delivery Connect it directly to the VSS with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program ...

Page 96: ...d Connection of Unused Pins Circuit Type P00 INTP0 TI00 2 Input Connect to VSS P01 INTP1 TI01 8 A Input Output Connect independently via a resistor P02 INTP2 to VSS P03 INTP3 P04 INTP4 P05 INTP5 P06 INTP6 P07 XT1 16 Input Connect to VDD P10 ANI0 to P17 ANI7 11 Input Output Connect independently via a P20 SI1 8 A resistor to VDD or VSS P21 SO1 5 A P22 SCK1 8 A P23 STB 5 A P24 BUSY 8 A P25 SI0 SB0 S...

Page 97: ...via a resistor P65 WR to VDD or VSS P66 WAIT P67 ASTB P70 SI2 RxD 8 A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P80 A0 to P87 A7 5 A P90 to P93 Mask ROM version 13 B Input output Connect independently via a resistor P90 to P93 µPD78P078Y 13 D to VDD P94 to P96 5 A Input output Connect independently via a resistor P100 TI5 TO5 8 A to VDD or VSS P101 TI6 TO6 P102 P103 5 A P120 RTP0 to P127 RTP7 5 A P130 ANO...

Page 98: ...ggered Input with Hysteresis Characteristics Type 5 E Type 11 Type 10 A Type 8 A pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT open drain output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch P ch comparator N ch input enable VREF Threshold vol...

Page 99: ...pe 13 D output disable VDD N ch IN OUT RD medium breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable VDD VDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch input enable P ch N ch analog output voltage ...

Page 100: ...100 MEMO ...

Page 101: ...13312 x 8 bits Reserved Program memory space C000H BFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 x 8 bits Special Function Registers SFRs 256 x 8 bits Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved FB00H FAFFH CHAPTER 5 CPU ARCHITECTURE 5 1 Memory Spaces The µPD78078 and 78078Y Subseries allow access to a memory space of 64 Kbytes F...

Page 102: ...space F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 x 8 bits Special Function Registers SFRs 256 x 8 bits Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved FB00H FAFFH Reserved Figure 5 2 Memory Map µPD78078 78078Y Note When internal ROM size is 60 Kbytes the area F000H to F3FFH cannot be used F000H to F3FFH can be used as extern...

Page 103: ...F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 x 8 bits Special Function Registers SFRs 256 x 8 bits Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved FB00H FAFFH ReservedNote Figure 5 3 Memory Map µPD78P078 µPD78P078Y Note When internal PROM size is 60 Kbytes the area F000H to F3FFH cannot be used F000H to F3FFH can be used as ex...

Page 104: ...ubseries have various size of internal ROMs or PROM as shown below Table 5 1 Internal ROM Capacities Part number Internal ROM Type Capacity µPD78076 78076Y Mask ROM 49152 x 8 bits µPD78078 78078Y 61440 x 8 bits µPD78P078 78P078Y PROM The internal program memory is divided into three areas vector table area CALLT instruction table area and CALLF instruction table area These areas are described on t...

Page 105: ...Table Address Interrupt Request 0000H RESET input 0004H INTWDT 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTP4 0010H INTP5 0012H INTP6 0014H INTCSI0 0016H INTCSI1 0018H INTSER 001AH INTSR INTCSI2 001CH INTST 001EH INTTM3 0020H INTTM00 0022H INTTM01 0024H INTTM1 0026H INTTM2 0028H INTAD 002AH INTTM5 002CH INTTM6 003EH BRK 2 CALLT instruction table area The 64 byte area 0040H to 007FH ca...

Page 106: ... 3 wire serial I O mode with automatic transmit receive function When not used in the 3 wire serial I O mode with automatic transmit receive function internal buffer RAM can also be used as normal RAM 3 Internal expansion RAM Internal expansion RAM is allocated to the 1024 byte area from F400H to F7FFH 5 1 3 Special function register SFR area An on chip peripheral hardware special function registe...

Page 107: ... to specify the instruction address to be executed next and the register and memory address to be manipulated when instructions are executed The instruction address to be executed next is addressed by the program counter PC for details refer to 5 3 Instruction Address Addressing For the addressing of the memory to be manipulated when instructions are executed the µPD78078 and 78078Y Subseries are ...

Page 108: ... Function Registers SFRs 256 x 8 bits Internal Expansion RAM 1024 x 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ReservedNote Figure 5 5 Data Memory Addressing µPD78078 78078Y Note When internal ROM size is 60 Kbytes the area F000H to F3FFH cannot be used F000H to F3FFH can be used as exte...

Page 109: ...unction Registers SFRs 256 x 8 bits Internal Expansion RAM 1024 x 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ReservedNote Figure 5 6 Data Memory Addressing µPD78P078 78P078Y Note When internal PROM size is 60 Kbytes the area F000H to F3FFH cannot be used F000H to F3FFH can be used as ext...

Page 110: ...be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 5 7 Program Counter Configuration 2 Program status word PSW The program statu...

Page 111: ...e of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored int...

Page 112: ...es 5 10 and 5 11 Caution Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution Figure 5 10 Data to be Saved to Stack Memory Figure 5 11 Data to be Reset from Stack Memory Interrupt and BRK Instruction PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register Pair Lower SP SP _ 2 SP _ 2 Register Pair Upper CALL CALLF and CALLT Instruction PUSH rp Instruct...

Page 113: ...te names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Figure 5 12 General Register Configuration a Absolute Name b Function Name BANK0 BANK...

Page 114: ...16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 5 3 gives a list of special function registers The meaning of items in the table is as follows Symbol This column shows the addresses of the special function registers They have been defined as reserved words in the RA78K 0 a...

Page 115: ...ed FF17H Compare register 20 CR20 FF18H 8 bit timer register 1 TMS TM1 R 00H FF19H 8 bit timer register 2 TM2 FF1AH Serial I O shift register 0 SIO0 R W Undefined FF1BH Serial I O shift register 1 SIO1 FF1FH A D conversion result register ADCR R FF20H Port mode register 0 PM0 R W FFH FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode regist...

Page 116: ...ol register 0 CRC0 04H FF4EH 16 bit timer output control register TOC0 00H FF4FH 8 bit timer output control register TOC1 FF50H Compare register 50 CR50 FF51H 8 bit timer register 5 TM5 R FF52H Timer clock selection register 5 TCL5 R W FF53H 8 bit timer mode control register 5 TMC5 FF54H Compare register 60 CR60 FF55H 8 bit timer register 6 TM6 R FF56H Timer clock selection register 6 TCL6 R W FF5...

Page 117: ...t mode register 0 INTM0 00H FFEDH External interrupt mode register 1 INTM1 FFF0H Internal memory size switching register IMS Note 2 FFF2H Oscillation mode selection register OSMS W 00H FFF3H Pull up resistor option register H PUOH R W FFF4H Internal expansion RAM size IXS W 0AHNote 3 switching register FFF6H Key return mode register KRM R W 02H FFF7H Pull up resistor option register L PUOL 00H FFF...

Page 118: ...tion information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 USER S MANUAL Instructions U12326E 5 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displ...

Page 119: ...dr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the memory space CALLF addr11 instruction branches to the area from 0800H to 0FFFH Illustration In the case of CALL addr16 and BR addr16 instructions In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr 15 0 PC 8 7 7 0 fa10 8 11 10 0 0 0 0 1 6 4 3 CALL...

Page 120: ...ansferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective Address 1 Effective Address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 ...

Page 121: ...ddressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 7 0 rp 0 7 A X 15 0 PC 8 7 ...

Page 122: ... to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employ...

Page 123: ...arried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description ex...

Page 124: ...struction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration 7 0 OP code addr16 higher Memory addr16 lower ...

Page 125: ...ture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Refer to Illustration below Operand format Identifier Description saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH imme...

Page 126: ...rd This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 ...

Page 127: ...ank select flag RBS0 and RBS1 and the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E Memory The contents of addressed memory are transferred Memory address specified by r...

Page 128: ...be accessed is in the register bank specified with the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 ...

Page 129: ... 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 5 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH...

Page 130: ...130 MEMO ...

Page 131: ...ble of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types Port 6 Port 0 Port 8 Port 9 Port 7 8 Port 1 Port 2 P00 P60 P67 P70 P72 P80 P103 P10 P07 P17 P20 P27 Port 13 Port 3 Port 4 Port 5 P87 P90 P96 P100 P120 P127 P130 Port 10 Port 12 P131 P30 P37 P40 to P...

Page 132: ...nput port an on chip pull up resistor can be connected by software SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 TO0 P31 TO1 P32 Port 3 TO2 P33 8 bit input output port TI1 P34 Input output mode can be specified bit wise TI2 P35 If used as an input port an on chip pull up resistor can be connected by software PCL P36 BUZ P37 Port 4 8 bit input output port P40 to P47 Input output mode can be specified bit wise A...

Page 133: ...output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be connected by software P90 N ch open drain input output port P91 On chip pull up resistor can be specified by P92 Port 9 mask option Mask ROM version only P93 7 bit input output port LEDs can be driven directly P94 Input output mode can be specified bit wise If used as an input port a...

Page 134: ...t output mode can be specified bit wise BUSY P25 If used as an input port an on chip pull up resistor can be connected by software SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 P31 TO1 P32 Port 3 TO2 P33 8 bit input output port TI1 P34 Input output mode can be specified bit wise TI2 P35 If used as an input port an on chip pull up resistor can be connected by software PCL P36 BUZ P37 Port 4 8 ...

Page 135: ...nected by software P90 N ch open drain input output port P91 On chip pull up resistor can be specified by P92 Port 9 mask option Mask ROM version only P93 7 bit input output port LEDs can be driven directly P94 Input output mode can be specified bit wise If used as an input port an on chip pull P95 up resistor can be connected by software P96 Port 10 4 bit input output port Input output mode can b...

Page 136: ...ith output latch P01 to P06 pins can specify the input mode output mode in 1 bit units with the port mode register 0 PM0 P00 and P07 pins are input only ports When P01 to P06 pins are used as input ports an on chip pull up resistor can be used in 6 bit units with a pull up resistor option register L PUOL Dual functions include external interrupt request input external count clock input to the time...

Page 137: ...ram of P01 to P06 PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P00 INTP0 TI00 P07 XT1 RD Internal bus P ch WRPM WRPORT RD WRPUO VDD P01 INTP1 TI01 P02 INTP2 to P06 INTP6 Selector PUO0 Output Latch P01 to P06 PM01 to PM06 Internal bus ...

Page 138: ...esistor option register L PUOL Dual functions include an A D converter analog input RESET input sets port 1 to input mode Figure 6 4 shows a block diagram of port 1 Caution An on chip pull up resistor cannot be used for pins used as A D converter analog input Figure 6 4 Block Diagram of P10 to P17 PUO Pull up resistor option register PM Port mode register RD Port 1 read signal WR Port 1 write sign...

Page 139: ...functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 5 and 6 6 show a block diagram of port 2 Cautions 1 When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Figure 17 4 Serial Operating Mode Register ...

Page 140: ...tch P20 P21 P23 to P26 PM20 PM21 PM23 to PM26 Internal bus Dual Function P20 SI1 P21 SO1 P23 STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 Figure 6 6 Block Diagram of P22 and P27 PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 141: ...onnected to them in 8 bit units with a pull up resistor option register L PUOL Dual functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 7 and 6 8 show a block diagram of port 2 Caution When used as a serial interface set the input output and output latch according to its func...

Page 142: ...D WRPUO VDD Selector PUO2 Output Latch P22 P27 PM22 PM27 Internal bus Dual Function P22 SCK1 P27 SCK0 SCL Figure 6 8 Block Diagram of P22 and P27 PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 143: ... mode in 1 bit units with the port mode register 3 PM3 When P30 to P37 pins are used as input ports an on chip pull up resistor can be connected to them in 8 bit units with a pull up resistor option register L PUOL Dual functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 9 shows a block diagram of port 3 Figure 6 9 Block Diagram of P30...

Page 144: ...ns include address data bus function in external memory expansion mode RESET input sets port 4 to input mode Figures 6 10 and 6 11 show a block diagram of port 4 and block diagram of falling edge detection circuit respectively Figure 6 10 Block Diagram of P40 to P47 PUO Pull up resistor option register MM Memory expansion mode register RD Port 4 read signal WR Port 4 write signal Figure 6 11 Block...

Page 145: ... bit units with a pull up resistor option register L PUOL Port 5 can drive LEDs directly Dual functions include address bus function in external memory expansion mode RESET input sets port 5 to input mode Figure 6 12 shows a block diagram of port 5 Figure 6 12 Block Diagram of P50 to P57 PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal P ch WR...

Page 146: ...nal output function in external memory expansion mode RESET input sets port 6 to input mode Figures 6 13 and 6 14 show block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output port 2 When the low level is input to the P60 to P63 pins the leakage current that flows through each of these pins depends on the following cond...

Page 147: ...stor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal WRPM WRPORT RD VDD Selector Output Latch P60 to P63 PM60 to PM63 Internal bus P60 to P63 Mask Option Resistor Mask ROM versions only PD78P078 and 78P078Y have no pull up resistor µ P ch WRPM WRPORT RD WRPUO VDD Selector PUO6 Output Latch P64 to P67 PM64 to PM67 Internal bus P64 RD P65 WR P66 WAIT P67 ASTB ...

Page 148: ...terface channel 2 data input output and clock input output RESET input sets the input mode Port 7 block diagrams are shown in Figures 6 15 and 6 16 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Table 20 2 Serial Interface Channel 2 Operating Mode Setting Figure 6 15 Block Diagram of P70 PUO Pull up resistor ...

Page 149: ...RPUO VDD Selector PUO7 Output Latch P71 P72 PM71 PM72 Internal bus Dual Function P71 SO2 TxD P72 SCK2 ASCK Figure 6 16 Block Diagram of P71 and P72 PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal ...

Page 150: ...ted to them in 8 bit units with a pull up resistor option register H PUOH Dual functions include the address bus function in external memory expansion mode RESET input sets port 8 to input mode Figure 6 17 shows block diagram of port 8 Figure 6 17 Block Diagram of P80 to P87 PUO Pull up resistor option register PM Port mode register RD Port 8 read signal WR Port 8 write signal P ch WRPM WRPORT RD ...

Page 151: ...ve LEDs directly Dual functions include the control signal output function in external memory expansion mode RESET input sets port 6 to input mode Figures 6 18 and 6 19 show block diagrams of port 9 Caution When the low level is input to the P90 to P93 pins the leakage current that flows through each of these pins depends on the following conditions Mask ROM version When a pull up resistor is conn...

Page 152: ...ll up resistor option register PM Port mode register RD Port 9 read signal WR Port 9 write signal Mask Option Resistor WRPM WRPORT RD VDD Selector Output Latch P90 to P93 PM90 to PM93 Internal bus P90 to P93 Mask ROM versions only PD78P078 and 78P078Y have no pull up resistor µ P ch WRPM WRPORT RD WRPUO VDD Selector PUO9 Output Latch P94 to P96 PM94 to PM96 Internal bus P94 to P96 ...

Page 153: ... bit units with the port mode register 10 PM10 When pins P100 to P103 are used as input ports an on chip pull up resistor can be connected to them in 4 bit units with a pull up resistor option register H PUOH Dual functions include the timer input output RESET input sets port 10 to input mode Figures 6 20 and 6 21 show block diagrams of port 10 Figure 6 20 Block Diagram of P100 and P101 PUO Pull u...

Page 154: ...21 Block Diagram of P102 and P103 PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO10 Output Latch P102 P103 PM102 PM103 Internal bus P102 P103 ...

Page 155: ...cted in 8 bit units with a pull up resistor option register H PUOH These pins are dual function pin and serve as real time outputs RESET input sets the input mode The port 12 block diagram is shown in Figure 6 22 Figure 6 22 Block Diagram of P120 to P127 PUO Pull up resistor option register PM Port mode register RD Port 12 read signal WR Port 12 write signal P ch WRPM WRPORT RD WRPUO VDD Selector ...

Page 156: ...lock diagram is shown in Figure 6 23 Caution When only either one of the D A converter channels is used with AVREF1 VDD the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to VSS Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from...

Page 157: ...3 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to Table 6 6 Cautions 1 Pins P00 and P07 are input only pins 2 As port 0 has an alternate function as external interrupt request input when the port function output mode is specified ...

Page 158: ...ate Function Pxx PMxx Input Output Pin Name Name Notes 1 If these ports are read out when these pins are used in the alternative function mode undefined values are read 2 When the P40 to P47 pins P50 to P57 pins and P64 to P67 pins are used for alternate functions set the function with the memory extension mode register MM 3 When the P80 to P87 pins are used for alternate functions set the functio...

Page 159: ... PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM6 PM7 PM8 FF26H FF27H FF28H FFH FFH FFH R W R W R W PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 1 1 1 1 1 PM72 PM71 PM70 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 PM05 PM04 PM9 FF29H FFH R W 1 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM10 PM12 PM13 PMmn Pmn Pin Input Output Mode Selection m 0 to 3 5 to 10 12 13 n 0 to 7 0 1 Output mode output buffer ON Input mode output b...

Page 160: ...to 00H Cautions 1 P00 and P07 pins do not incorporate a pull up resistor 2 When ports 1 4 5 and P64 to P67 pins or port 8 pins are used as dual function pins an on chip pull up resistor cannot be used even if 1 is set in PUOm bit of PUOH and PUOL m 1 4 to 6 or 8 3 Pins P60 to P63 and P90 to P93 can be incorporated with pull up resistor by mask option only for mask ROM version Figure 6 25 Pull Up R...

Page 161: ... and memory expansion mode 2 Besides setting port 4 input output MM also sets the wait count and external expansion area 0 0 PW1 0 MM FFF8H 10H R W 7 6 5 4 3 2 Symbol Address After Reset R W 1 PW0 MM2 MM1 MM0 0 MM2 MM1 MM0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 1 Other than above Setting prohibited Single chip Memory Expansion Mode Selection Single chip mode 256 byte mode 4 Kbyte mode 16 Kbyte mode Ful...

Page 162: ...ts KRM to 02H Figure 6 27 Key Return Mode Register Format Caution When falling edge detection of port4 is used KRIF should be cleared to 0 not cleared to 0 automatically KRIF Key Return Signal Detection Flag 0 1 Not Detected Detected Falling edge detection of port 4 0 0 0 0 KRM FFF6H 7 6 5 4 3 2 Symbol 1 0 KRMK KRIF 0 0 KRMK Standby Mode Control by Key Return Signal 0 1 Standby mode release enable...

Page 163: ...latch contents for pins specified as input are undefined except for the manipulated bit 6 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 6 4 3 Operations on input output port 1 Output mode An ope...

Page 164: ...k ROM version The µPD78P078 and 78P078Y have no mask option Table 6 7 Comparison between Mask ROM Version and the µPD78P078 and 78P078Y Pin Name Mask ROM Version µPD78P078 and 78P078Y Mask option for pins P60 to P63 and Bitwise selectable on chip pull up No on chip pull up resistor P90 to P93 resistors ...

Page 165: ...llates at frequencies of 1 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register PCC 2 Subsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistance can be set by the processor clock control registe...

Page 166: ...ch Timer Clock Output Function fXX CPU Clock fCPU Wait Control Circuit Divider Selector fX fXT 2 fX MCS Processor Clock Control Register 1 2 2 fXT PCC0 3 Selector 7 2 Clock Generator Configuration The clock generator consists of the following hardware Table 7 1 Clock Generator Configuration Item Configuration Control register Processor clock control register PCC Oscillation mode selection register...

Page 167: ...sor clock control register PCC The PCC selects a CPU clock and the division ratio determines whether to make the main system clock oscillator operate or stop and enables or desables the subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Subsystem Clock Feedback Resistor FRC P ch Feedb...

Page 168: ... Resistor Selection MCC 0 1 Oscillation possible Oscillation stopped Main System Clock Oscillation ControlNote 2 R W R W R W R fX fX 2 fX 22 fXT 2 fX 23 fX 24 fX 22 fX 2 fX 23 fX 24 fX 25 MCS 1 MCS 0 0 1 Figure 7 3 Processor Clock Control Register Format Notes 1 Bit 5 is a read only bit 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation ...

Page 169: ...minimum instruction execution time is shown in Table 7 2 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock fCPU Minimum Instruction Execution Time 2 fCPU fX 0 4 µs fX 2 0 8 µs fX 22 1 6 µs fX 23 3 2 µs fX 24 6 4 µs fX 25 12 8 µs fXT 2 122 µs fX 5 0 MHz fXT 32 768 kHz fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency ...

Page 170: ...ral hardware which operates with the main system clock a temporary error occurs in the count clock cycle of timer etc In addition because the oscillation mode is changed by this register the clocks for peripheral hardware as well as that for the CPU are switched Therefore writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts...

Page 171: ...k signal to the X2 pin Figure 7 6 shows an external circuit of the main system clock oscillator Figure 7 6 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock Caution Do not execute the STOP instruction nor set MCC bit 7 of the processor clock control register PCC to 1 while an external clock is input This is because the operation of main system cloc...

Page 172: ...gth Do not allow wiring to intersect with other signal conductors Do not allow wiring to come near abruptly changing high current Set the potential of the grounding position of the oscillator capacitor to that of VSS Do not ground to any ground pattern where high current is present Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circu...

Page 173: ...Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 In Figure 7 8 f XT2 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with XT2 resulting in malfunctioning To prevent that from occurring it is recommended to wire XT2 and X1 so that they are not in parallel and to connect the IC pin...

Page 174: ...perations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD XT2 Open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To minimize leakage current set bit 6 FRC of the processor clock control register PCC so that the above internal feedback resistor is not used In this case...

Page 175: ...a system which is not using the subsystem clock the current consumption in the STOP mode can be reduced further by setting bit 6 FRC of the PCC so as not to use the on chip feedback resistor d The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 µs when operated at 32 768 kHz e With the subsystem clock selected main system clock oscillation c...

Page 176: ... set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 7 9 Figure 7 9 Main System Clock Stop Function 1 2 a Operation when MCC is set after setting CSS with main system clock operation b Oper...

Page 177: ...CLS of the processor clock control register PCC set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 µs when operated at 32 768 kHz irrespective of bits 0 to 2 PCC0 to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation MCC CSS CLS Main System Clock Oscillati...

Page 178: ...instructions 1 instruction 1 instruction 0 1 0 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 0 1 1 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 1 1 X X X fX 2fXT instruction fX 4fXT instruction fX 8fXT instruction fX 16fXT instruction fX 32fXT instruction 77 ins...

Page 179: ...ection register OSMS are rewritten and the maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system clock is switched to the subsystem clock which must be in an oscillation stable state 4 Upon detection of VDD voltage reset due to an interrupt request signal 0 is set to bit 7 MCC of PCC and oscillation of the main s...

Page 180: ...180 MEMO ...

Page 181: ... TIMER EVENT COUNTERS 1 AND 2 3 8 bit timer event counters 5 and 6 TM5 and TM6 TM5 and TM6 can be used to serve as an interval timer and external event counter and to output any frecuency square waves These cannot be used as 16 bit timer event counters See CHAPTER 10 8 BIT TIMER EVENT COUNTER 5 AND 6 4 Watch timer TM3 This timer can set a flag every 0 5 sec and simultaneously generates interrupt r...

Page 182: ...uare wave output One shot pulse output Interrupt request Test input Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 The watchdog timer can perform either the watchdog timer function or the interval timer function 3 When capture compare registers CR00 CR01 are specified as compare registers 16 bit timer 8 bit timer event 8 bit timer event Watch t...

Page 183: ...1 fX 1 fX 400 ns 13 1 ms 200 ns 2 x 1 fX 22 x 1 fX 216 x 1 fX 217 x 1 fX 1 fX 2 x 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fX 23 x 1 fX 217 x 1 fX 218 x 1 fX 2 x 1 fX 22 x 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fX 24 x 1 fX 218 x 1 fX 219 x 1 fX 22 x 1 fX 23 x 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 x watch timer output cycle 216 x watch timer output cyc...

Page 184: ...X 1 fX 2 x 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fX 23 x 1 fX 217 x 1 fX 218 x 1 fX 2 x 1 fX 22 x 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fX 24 x 1 fX 218 x 1 fX 219 x 1 fX 22 x 1 fX 23 x 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Remarks 1 fX Main system clock oscilla...

Page 185: ...16 bits x 1 TM0 Register Capture compare register 16 bits x 2 CR00 CR01 Timer output 1 TO0 Timer clock select register 0 TCL0 16 bit timer mode control register TMC0 Capture compare control register 0 CRC0 Control register 16 bit timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register 0 INTM0 Sampling clock select register SCS Note Note Refer to Figure 22 1 Bas...

Page 186: ...X 22 TI00 P00 INTP0 Selector 3 TCL06 TCL05 TCL04 Timer Clock Selection Register 0 CRC02 16 Bit Capture Compare Control Register CR01 Internal Bus 16 Bit Capture Compare Control Register CR00 16 Bit Timer Register TM0 Clear Match Clear Circuit TMC03 TMC02 TMC01 OVF0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 16 Bit Timer Mode Control Register 16 Bit Timer Output Control Register 2 PWM Pulse Output Contro...

Page 187: ...tput Control Circuit Edge Detection Circuit 2 ES11 ES10 TI00 P00 INTP0 External Interrupt Mode Register 0 OSPT 16 Bit Timer Output Control Register OSPE TOC04 LVS0 LVR0 TOC01 TOE0 16 Bit Timer Mode Control Register TMC03 TMC02 TMC01 P30 Output Latch PM30 Port Mode Register 3 TO0 P30 Selector INV S R Q 3 Level Inversion CRC02 INTTM01 CRC00 INTTM00 One Shot Pulse Output Control Circuit Internal Bus ...

Page 188: ...it memory manipulation instruction After RESET input the value of CR00 is undefined Cautions 1 Set the PWM data 14 bits to the higher 14 bits of CR00 and set 00 to the lower 2 bits 2 Set values other than 0000H to CR00 Therefore when used as an event counter 1 pulse count operation cannot be executed 3 When the value after CR00 is changed is smaller than the 16 bit timer register TM0 value TM0 con...

Page 189: ...er which counts the count pulses TM0 is read by a 16 bit memory manipulation instruction When TM0 is read capture compare register CR01 should first be set as a capture register RESET input sets TM0 to 0000H Caution As the value of TM0 is read via CR01 the previously set value of CR01 is lost ...

Page 190: ...C0 16 bit timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register 0 INTM0 Sampling clock select register SCS 1 Timer clock select register 0 TCL0 This register is used to set the count clock of the 16 bit timer register TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 value to 00H Remark TCL0 has the function of setting th...

Page 191: ...0 0 0 fXT 32 768 kHz 0 1 0 1 fXX fX 5 0 MHz fX 2 2 5 MHz 0 1 1 0 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 0 1 1 1 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 1 0 0 0 fXX 2 3 fX 2 3 625 kHz fX 2 4 313 kHz 1 0 0 1 fXX 2 4 fX 2 4 313 kHz fX 2 5 156 kHz 1 0 1 0 fXX 2 5 fX 2 5 156 kHz fX 2 6 78 1 kHz 1 0 1 1 fXX 2 6 fX 2 6 78 1 kHz fX 2 7 39 1 kHz 1 1 0 0 fXX 2 7 fX 2 7 39 1 kHz fX 2 8 19 5 kHz MCS 1 PCL Output C...

Page 192: ... TMC03 respectively Set 0 0 0 in TMC01 to TMC03 to stop the operation Figure 8 4 16 Bit Timer Mode Control Register Format 0 0 0 0 TMC03 TMC02 TMC01 OVF0 7 6 5 4 3 2 1 0 Symbol TMC0 FF48H 00H R W Address After Reset R W OVF0 16 Bit Timer Register Overflow Detection 0 Overflow not detected 1 Overflow detected TMC03 TMC02 TMC01 Operating Mode and Clear Mode TO0 Output Timing Interrupt Generation 0 0...

Page 193: ...ter 00 CR01 Compare register 01 3 Capture compare control register 0 CRC0 This register controls the operation of the capture compare registers CR00 CR01 CRC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CRC0 value to 04H Figure 8 5 Capture Compare Control Register 0 Format Cautions 1 Timer operation must be stopped before setting CRC0 2 When clear start mode on a ...

Page 194: ... will be 0 3 OSPT is cleared automatically after data setting and will therefore be 0 if read 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 7 6 5 4 3 2 1 0 Symbol TOC0 FF4EH 00H R W Address After Reset R W TOE0 16 Bit Timer Event Counter Output Control 0 Output disabled Port mode 1 Output enabled TOC01 0 1 In PWM Mode In Other Modes Active level selection Timer output F F control by match of CR00 and TM0...

Page 195: ... output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Format PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 7 6 5 4 3 2 1 0 Symbol PM3 FF23H FFH R W Address After Reset R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 196: ... register TMC0 and stop the timer operation before setting the valid edges of INTP0 TI00 P00 pins ES31 ES30 ES21 ES20 ES11 ES10 0 0 7 6 5 4 3 2 1 0 Symbol INTM0 FFECH 00H R W Address After Reset R W ES11 INTP0 Valid Edge Selection ES10 0 Falling edge 0 0 Rising edge 1 1 Setting prohibited 0 1 Both falling and rising edges 1 ES21 INTP1 Valid Edge Selection ES20 0 Falling edge 0 0 Rising edge 1 1 Se...

Page 197: ...6 and fXX 27 are clocks supplied to peripheral hardware fXX 2N is stopped in HALT mode Remarks 1 N Value set in bits 0 to 2 PCC0 to PCC2 of the processor clock control register PCC N 0 to 4 2 fXX Main system clock frequency fX or fX 2 3 fX Main system clock oscillation frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Figures in parentheses apply to operation with fX 5 0 MHz 0 0 ...

Page 198: ... INTTM00 is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TCL04 to TCL06 of the timer clock select register 0 TCL0 For the operation in the case the value of the compare register is changed during the timer count operation refer to 8 6 16 Bit Timer Event Counter Precautions 3 Figure 8 10 Control Register Settings for Interval Timer Operation a 16 bit time...

Page 199: ... Start Clear Clear N N N N Interrupt Request Acknowledge Interrupt Request Acknowledge Figure 8 11 Interval Timer Configuration Diagram Figure 8 12 Interval Timer Operation Timings Remark Interval time N 1 x t N 0001H to FFFFH 16 Bit Capture Compare Register 00 CR00 16 Bit Timer Register TM0 Selector fXX 2 2 fXX 2 fXX 2fXX INTTM3 TI00 P00 INTP0 OVF0 Clear Circuit INTTM00 ...

Page 200: ...ation with fX 5 0 MHz 8 5 2 PWM output operations Setting the 16 bit timer mode control register TMC0 capture compare control register 0 CRC0 and the 16 bit timer output control register TOC0 as shown in Figure 8 13 allows operation as PWM output Pulses with the duty rate determined by the value set in 16 bit capture compare register 00 CR00 beforehand are output from the TO0 P30 pin Set the activ...

Page 201: ...ol register TOC0 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with PWM output See the description of the respective control registers for details x Don t care TMC0 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode CRC00 CRC01 CRC02 CRC0 0 0 1 0 1 0 0 0 0 0 CR00 set as compare register TOE0 TOC01 LVR0 LVS0 TOC04 OSPE OSPT TOC0 1 0 1 x x x x x 0 TO0 Output Enabled Specif...

Page 202: ...rnal switching circuit reference voltage Figure 8 14 Example of D A Converter Configuration with PWM Output capture compare register 00 CR00 value Figure 8 15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner Figure 8 15 TV Tuner Application Circuit Example Switching Circuit TO0 P30 PWM signal VREF Low Pass Filter Analog Output V...

Page 203: ...re 8 16 Control Register Settings for PPG Output Operation a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register TOC0 Caution Values in the following range should be set in CR00 and CR01 0000H CR01 CR00 FFFFH Remark x Don t care TMC0 0 0 1 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear start on match of TM0 and CR00 CRC0 0 x 0 0 0 0 0 0 ...

Page 204: ...external interrupt request signal INTP0 is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 3 EX10 and ES11 of INTM0 For valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise...

Page 205: ...ion by Free Running Counter and One Capture Register with Both Edges Specified Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D1 FFFF 0000 D2 D3 D0 D1 D2 D3 D1 D0 x t 10000H D1 D2 x t D3 D2 x t t Selector fXX 2 2 fXX 2 fXX 2fXX INTTM3 16 Bit Timer Register TM0 16 Bit Capture Compare Register 01 CR01 OVF0 INTP0 Internal Bus TI00 P00 INTP00 ...

Page 206: ...ions can be selected rising falling or both edges as the valid edges for the TI00 P00 pin and the TI01 P01 pin by means of bits 2 and 3 ES10 and ES11 and bits 4 and 5 ES20 and ES21 of INTM0 respectively For TI00 P00 pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid lev...

Page 207: ...ent Operation with Free Running Counter with Both Edges Specified Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 D1 D0 x t 10000H D1 D2 x t 10000H D1 D2 1 x t D3 D2 x t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 ...

Page 208: ...d 3 ES10 and ES11 of INTM0 For TI00 P00 pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TI00 P00 is specified to be both rising and falling edge capture compare regis...

Page 209: ... Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 D1 D0 x t 10000H D1 D2 x t D3 D2 x t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t ...

Page 210: ...iminated Caution If the valid edge of TI00 P00 is specified to be both rising and falling edge capture compare register 00 CR00 cannot perform the capture operation Figure 8 24 Control Register Settings for Pulse Width Measurement by Means of Restart a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 Remark 0 1 Setting 0 or 1 allows another function to be used simu...

Page 211: ...g edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTM0 Because operation is carried out only after the valid edge is detected twice by sampling at the cycle selected with the sampling clock select register SCS noise with short pulse widths can be removed Figure 8 26 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register...

Page 212: ...sing Edge Specified Caution When reading the external event counter count value TM0 should be read 16 Bit Capture Compare Register 00 CR00 Clear INTTM00 INTP0 16 Bit Timer Register TM0 16 Bit Capture Compare Register 01 CR01 Internal Bus TI00 Valid Edge OVF0 TI00 Pin Input TM0 Count Value CR00 INTTM0 N 0000 0001 0002 0003 0004 0005 N 1 N 0000 0001 0002 0003 ...

Page 213: ...Settings in Square Wave Output Mode a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 TMC0 0 0 1 1 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear start on match of TM0 and CR00 CRC0 0 0 1 0 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register c 16 bit timer output control register TOC0 TOC0 1 1 0 1 0 1 0 0 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output Enabled ...

Page 214: ...800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fX 23 x 1 fX 217 x 1 fX 218 x 1 fX 2 x 1 fX 22 x 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fX 24 x 1 fX 218 x 1 fX 219 x 1 fX 22 x 1 fX 23 x 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Remarks 1 fX Main system clock oscillation frequency 2 MCS Bi...

Page 215: ...n When outputting one shot pulse do not set 1 in OSPT When outputting one shot pulse again execute after the INTTM00 or interrupt match signal with CR00 is generated Figure 8 31 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register TOC0 Caution V...

Page 216: ...he 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 OSPT INTTM00 TO0 Pin Output 0000 0001 N N 1 0000 N 1 N M 1 M 0000 0001 0002 N M N M N M N M Set 0CH to TMC0 TM0 count start ...

Page 217: ...bit capture compare register 00 CR00 Caution When outputting one shot pulses external trigger is ignored if generated again Figure 8 33 Control Register Settings for One Shot Pulse Output Operation Using External Trigger a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register TOC0 Caution Values in the following range should be set...

Page 218: ...Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 TI00 Pin Input INTTM00 TO0 Pin Output 0000 0001 0000 N N 1 N 2 M 2 M 1 M M 1 M 2 M 3 N M N M N M N M Set 08H to TMC0 TM0 count start ...

Page 219: ...ure compare register as event counter one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit capture compare register CR00 is changed is smaller than that of the 16 bit timer register TM0 TM0 continues counting overflows and then restarts counting from 0 Thus if the value M after CR00 change is smaller th...

Page 220: ...ister TMC0 to 0 0 and 0 respectively and then stopping timer operation Valid edge setting is carried out with bits 2 and 3 ES10 and ES11 of the external interrupt mode register 0 INTM0 6 Re trigger of one shot pulse a One shot pulse output using software When outputting one shot pulse do not set 1 in OSPT When outputting one shot pulse again execute it after the INTTM00 which is the match interrup...

Page 221: ... flag is set to 1 in the following case The clear start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH When TM0 is counted up from FFFFH to 0000H Figure 8 38 Operation Timing of OVF0 Flag Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H ...

Page 222: ...222 MEMO ...

Page 223: ...l 8 bit timer event counters to be used separately the 8 bit timer event counter mode and the other is a mode for the 8 bit timer event counter to be used as 16 bit timer event counter the 16 bit timer event counter mode 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions Interval timer External event counter Square wave output ...

Page 224: ... µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 x 1 fX 29 x 1 fX 216 x 1 fX 217 x ...

Page 225: ...1 fX 213 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs...

Page 226: ... x 1 fX 221 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 221 x 1 fX 222 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 222 x 1 fX 223 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 223 x 1 fX 224 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µ...

Page 227: ...24 x 1 fX 25 x 1 fX 220 x 1 fX 221 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 221 x 1 fX 222 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 222 x 1 fX 223 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 223 x 1 fX 224 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 ...

Page 228: ... Counters 1 and 2 Block Diagram Note Refer to Figures 9 2 and 9 3 for details of 8 bit timer event counter output control circuits 1 and 2 respectively Control register Internal Bus 8 Bit Compare Register CR10 Match 8 Bit Timer Register 1 TM1 Selector Clear Selector Selector TI1 P33 fXX 2 to fXX 29 fXX 2 to fXX 29 fXX 211 fXX 211 TI2 P34 4 4 8 Bit Timer Mode Control Register TMC12 TCE2 TCE1 Intern...

Page 229: ...n output control circuit Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Remarks 1 The section in the broken line is an output control circuit 2 fSCK Serial clock frequency LVR1 LVS1 TOC11 INTTM1 R S INV Q P31 Output Latch TOE1 PM31 TO1 P31 Level F F LV1 LVR2 LVS2 TOC15 INTTM2 R S INV Level F F LV2 fSCK P32 Output Latch PM32 TOE2 TO2 P32 Q ...

Page 230: ...sed as 8 bit timer event counter the 00H to FFH values can be set When the compare register is used as 16 bit timer event counter the 0000H to FFFFH values can be set RESET input makes CR10 and CR20 undefined Caution When using the compare register as 16 bit timer event counter be sure to set data after stopping timer operation 2 8 bit timer registers 1 2 TM1 TM2 These are 8 bit registers to count...

Page 231: ...ol the 8 bit timer event counter Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 1 Timer clock select register 1 TCL1 This register sets count clocks of 8 bit timer registers 1 and 2 TCL1 is set with an 8 bit memory manipulation instruction RESET input sets TCL1 to 00H ...

Page 232: ...4 0 0 0 0 TI2 falling edge 0 0 0 1 TI2 rising edge 0 1 1 0 0 1 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 1 0 0 1 fXX 2 3 fX 2 3 625 kHz fX 2 4 313 kHz 1 0 1 0 fXX 2 4 fX 2 4 313 kHz fX 2 5 156 kHz 1 0 1 1 fXX 2 5 fX 2 5 156 kHz fX 2 6 78 1 kHz 1 1 0 0 fXX 2 6 fX 2 6 78 1 kHz fX 2 7 39 1 kHz 1 1 0 1 fXX 2 7 fX 2 7 39 1 kHz fX 2 8 19 5 kHz 1 1 1 0 fXX 2 8 ...

Page 233: ...t Cautions 1 Stop the timer operation before switching the operating mode 2 When used as 16 bit timer register TCE1 should be used for operation enable stop 0 1 2 3 4 5 6 7 Symbol TCE1 FF49H 00H R W Address After Reset R W TCE2 TMC12 0 0 0 0 0 TMC1 TCE1 8 Bit Timer Register 1 Operation Control 0 Operation stop TM1 clear to 0 1 Operation enable TCE2 8 Bit Timer Register 2 Operation Control Operatio...

Page 234: ...E1 TOC11 LVR1 LVS1 TOE2 TOC15 LVR2 LVS2 TOC1 FF4FH 00H R W Address After Reset R W TOE1 8 Bit Timer Event Counter 1 Outptut Control 0 Output disable port mode 1 Output enable TOC11 8 Bit Timer Event Counter 1 Timer Output F F Control 0 Inverted operation disable 1 Inverted operation enable LVS1 LVR1 8 Bit Timer Event Counter 1 Timer Output F F Status Set 0 0 Unchanged 0 1 Timer output F F reset 0 ...

Page 235: ...31 PM32 and output latches of P31 and P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format 0 1 2 3 4 5 6 7 Symbol PM30 FF23H FFH R W Address After Reset R W PM31 PM32 PM33 PM34 PM35 PM36 PM37 PM3 PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 236: ... interrupt request signals INTTM1 and INTTM2 are generated Count clock of the TM1 can be selected with bits 0 to 3 TCL10 to TCL13 of the timer clock select register 1 TCL1 Count clock of the TM2 can be selected with bits 4 to 7 TCL14 to TCL17 of the timer clock select register 1 TCL1 For the operation in the case the value of the compare register is changed during the timer count operation refer t...

Page 237: ...fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 x 1 fX 29 x 1 fX 216 x 1 fX 217 x 1 fX 28 x 1 fX 29 x 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 x 1 fX...

Page 238: ...1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 x 1 fX 29 x 1 fX 216 x 1 fX 217 x 1 fX 28 x 1 fX 29 x 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 x 1 ...

Page 239: ...valid edge specified with the timer clock select register TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 External Event Counter Operation Timings with Rising Edge Specified Remark N 0...

Page 240: ...6 µs 800 ns 1 6 µs 23 x 1 fX 24 x 1 fX 211 x 1 fX 212 x 1 fX 23 x 1 fX 24 x 1 fX 1 6 µs 3 2 µs 409 6 µs 819 2 µs 1 6 µs 3 2 µs 24 x 1 fX 25 x 1 fX 212 x 1 fX 213 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1...

Page 241: ...0 Timing of Square Wave Output Operation Note The initial value of the TO1 output can be set by bits 2 and 3 LVS1 and LVR1 of the 8 bit timer output control register TOC1 Count Clock TM1 Count Value 01 02 00 N 1 N 00 01 02 N 1 N 00 Count Start CR10 N N TO1Note ...

Page 242: ...tting a count value assign the value of the high order 8 bits to CR20 and the value of the low order 8 bits to CR10 For the count values that can be set interval time refer to Table 9 9 When the value of 8 bit timer register 1 TM1 coincides with the value of CR10 and the value of 8 bit timer register 2 TM1 coincides with the value of CR20 the values of TM1 and TM2 are cleared to 0 and at the same ...

Page 243: ...6 x 1 fX 221 x 1 fX 222 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 222 x 1 fX 223 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 223 x 1 fX 224 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51 2 µs 28 x 1 fX 29 x 1 fX 224 x 1 fX 225 x 1 fX 28 x 1 fX 29 x 1 fX 51 2 µs 102 4 µs 3 4 s 6...

Page 244: ...M2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit 1 is inverted Thus when using 8 bit t...

Page 245: ... x 1 fX 218 x 1 fX 219 x 1 fX 22 x 1 fX 23 x 1 fX 800 ns 1 6 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 23 x 1 fX 24 x 1 fX 219 x 1 fX 220 x 1 fX 23 x 1 fX 24 x 1 fX 1 6 µs 3 2 µs 104 9 ms 209 7 ms 1 6 µs 3 2 µs 24 x 1 fX 25 x 1 fX 220 x 1 fX 221 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 221 x 1 fX 222 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 419 4 ms 838...

Page 246: ...pare register 10 and 20 setting The 8 bit compare registers 10 and 20 CR10 and CR20 can be set to 00H Thus when these 8 bit compare registers are used as event counters one pulse count operation can be carried out When the 8 bit compare register is used as 16 bit timer event counter write data to CR10 and CR20 after setting bit 0 TCE1 of the 8 bit timer mode control register 1 to 0 and stopping ti...

Page 247: ...se of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value M after CR10 and CR20 change is smaller than value N before the change it is necessary to restart the timer after changing CR10 and CR20 Figure 9 15 Timing after Compare Register Change during Timer Count Operation Remark N X M Count Pulse CR10 CR20 TM1 TM2 Count Value ...

Page 248: ...248 MEMO ...

Page 249: ...TIMER EVENT COUNTERS 5 AND 6 10 1 8 Bit Timer Event Counters 5 and 6 Functions The 8 bit timer event counters 5 and 6 TM5 TM6 have the following functions Interval timer External event counter Square wave output PWM output ...

Page 250: ... x 1 fX 25 x 1 fX 212 x 1 fX 213 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs...

Page 251: ...s 3 2 µs 24 x 1 fX 25 x 1 fX 212 x 1 fX 213 x 1 fX 24 x 1 fX 25 x 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6...

Page 252: ...sters 5 and 6 TMC5 TMC6 Port mode register 10 PM10 Note Note Refer to Figure 6 20 Block Diagram of P100 and P101 Figure 10 1 8 Bit Timer Event Counters 5 and 6 Block Diagram Note Refer to Figure 10 2 for details of configurations of 8 bit timer event counters 5 and 6 output control circuits Remark n 5 6 TI5 P100 TO5 TI6 P101 TO6 Internal Bus 8 Bit Compare Register CRn0 Match 8 Bit Timer Register n...

Page 253: ...espectively CR50 and CR60 are set with an 8 bit memory manipulation instruction They cannot be set with a 16 bit memory manipulation instruction The 00H to FFH values can be set RESET input sets CR50 and CR60 values to 00H Caution To use PWM mode set CRn0 value before setting TMCn n 5 6 to PWM mode 2 8 bit timer registers 5 and 6 TM5 TM6 These 8 bit registers count count pulses TM5 and TM6 are rea...

Page 254: ...ck oscillation frequency 3 TI5 8 bit timer register 5 input pin 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Figures in parentheses apply to operation with fX 5 0 MHz 0 0 0 0 TCL53 TCL52 TCL51 TCL50 7 6 5 4 3 2 1 0 Symbol TCL5 TCL53 TCL52 TCL51 TCL50 0 0 0 0 TI5 falling edgeNote 0 0 0 1 TI5 rising edgeNote 0 1 0 0 fXX fX Setting prohibited fX 2 2 5 MHz 0 1 0 1 fXX 2 fX 2 2 5 MHz fX 2 ...

Page 255: ...ses apply to operation with fX 5 0 MHz 0 0 0 0 TCL63 TCL62 TCL61 TCL60 7 6 5 4 3 2 1 0 Symbol TCL6 TCL63 TCL62 TCL61 TCL60 0 0 0 0 TI6 falling edgeNote 0 0 0 1 TI6 rising edgeNote 0 1 0 0 fXX fX Setting prohibited fX 2 2 5 MHz 0 1 0 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 0 1 1 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 0 1 1 1 fXX 2 3 fX 2 3 625 kHz fX 2 4 313 kHz 1 0 0 0 fXX 2 4 fX 2 4 313 kHz fX 2 5...

Page 256: ...n must be stopped before setting TMC5 2 If LVS5 and LVR5 are read after data are set they will be 0 3 Set bits 4 and 5 to 0 TCE5 TMC56 0 0 LVS5 LVR5 TMC51 TOE5 7 6 5 4 3 2 1 0 Symbol TMC5 FF53H 00H R W Address After Reset R W TOE5 8 Bit Timer Event Counter 5 Output Control 0 Output disabled Port mode 1 Output enabled TMC51 0 Active high 1 Active low In PWM Mode In Other Mode Active level selection...

Page 257: ... must be stopped before setting TMC6 2 If LVS6 and LVR6 are read after data are set they will be 0 3 Set bits 4 and 5 to 0 TCE6 TMC66 0 0 LVS6 LVR6 TMC61 TOE6 7 6 5 4 3 2 1 0 Symbol TMC6 FF57H 00H R W Address After Reset R W TOE6 8 Bit Timer Event Counter 6 Output Control 0 Output disabled Port mode 6 Output enabled TMC61 0 Active high 1 Active low In PWM Mode In Other Mode Active level selection ...

Page 258: ...et PM100 PM101 and output latches of P100 and P101 to 0 PM10 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM10 to FFH Figure 10 7 Port Mode Register 10 Format 1 7 1 6 1 1 4 PM103 3 2 1 0 FF2AH Address PM10 Symbol PM102 PM101 PM100 5 FFH After Reset R W R W PM10n 0 1 P10n Pin Input Output Mode Selection n 0 to 3 Output mode output buffer ON Input mode output buffer ...

Page 259: ...t clock of the 8 bit timer register 6 TM6 can be selected with the timer clock select register 6 TCL6 For the operation in the case the value of the compare register is changed during the timer count operation refer to 10 5 8 Bit Timer Event Counters 5 and 6 Precautions 3 Figure 10 8 8 Bit Timer Mode Control Register Settings for Interval Timer Operation Remarks 1 0 1 Setting 0 or 1 allows another...

Page 260: ...fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 x 1 fX 29 x 1 fX 216 ...

Page 261: ...en the TM5 and TM6 counted values match the values of 8 bit compare registers CR50 and CR60 TM5 and TM6 are cleared to 0 and the interrupt request signals INTTM5 and INTTM6 are generated Figure 10 10 8 Bit Timer Mode Control Register Setting for External Event Counter Operation Remarks 1 n 5 6 2 x Don t care Figure 10 11 External Event Counter Operation Timings with Rising Edge Specified Remarks 1...

Page 262: ...gure 10 12 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation Caution When TI5 P100 TO5 or TI6 P101 TO6 pin is used as the timer output set port mode register PM100 or PM101 and output latch P100 or P101 to 0 Remark n 5 6 Figure 10 13 Timing of Square Wave Output Operation Note The initial value of the TOn output can be set by bits 2 and 3 LVSn and LVRn of the 8 bit timer ...

Page 263: ...1 fX 25 x 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 x 1 fX 26 x 1 fX 213 x 1 fX 214 x 1 fX 25 x 1 fX 26 x 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 x 1 fX 27 x 1 fX 214 x 1 fX 215 x 1 fX 26 x 1 fX 27 x 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 x 1 fX 28 x 1 fX 215 x 1 fX 216 x 1 fX 27 x 1 fX 28 x 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 x 1 fX 29...

Page 264: ...ster 6 TMC6 This PWM pulse has an 8 bit resolution The pulse can be converted into an analog voltage by integrating it with an external low pass filter LPF Count clock of the 8 bit timer register 5 TM5 can be selected with the timer clock select register 5 TCL5 and count clock of the 8 bit timer register 6 TM6 can be selected with the timer clock select register 6 TCL6 PWM output enable disable ca...

Page 265: ...gs CRn0 00H Active High Setting Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 N N 1 N 2 N 3 00 OVFn M N N 00 Inactive Level CRn0 Changing Active Level Inactive Level Inactive Level M N Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn M 00 00 00 Inactive Level CRn0 Changing M 00 Inactive Level ...

Page 266: ...s changed during TMn operation the value changed is not reflected until TMn overflows Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn FF FF FF 00 Inactive Level Inactive Level Active Level Inactive Level Active Level Count Clock TMn Count Value CRn0 TCEn INTTMn TOn OVFn Active Level Inactive Level 00 FF N 2 N 1 N 02 01 00 FF 01 02 M 2 M 1 M M 3 00 Active Leve...

Page 267: ...rted asynchronously with the count pulse Figure 10 19 8 bit Timer Registers 5 and 6 Start Timings 2 Compare registers 50 and 60 sets The 8 bit compare registers CR50 and CR60 can be set to 00H Thus when an 8 bit compare register is used as an event counter one pulse count operation can be carried out Figure 10 20 External Event Counter Operation Timings Count Pulse TM5 TM6 Count Value 00H Timer St...

Page 268: ... compare registers CR50 and CR60 are changed are smaller than those of 8 bit timer registers TM5 and TM6 TM5 and TM6 continue counting overflow and then restarts counting from 0 Thus if the value M after CR50 and CR60 change is smaller than that N before change it is necessary to restart the timer after changing CR50 and CR60 Figure 10 21 Timings after Compare Register Change during Timer Count Op...

Page 269: ...in system clock You should switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals 2 Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 11 1 Interval Timer Interval Time When operated at When operated at When operated at fXX 5 0 MHz fXX 4 19 MHz fXT 32 768 kHz 24 x 1 fW 410 µs 488 µs 488 µs 25 x 1 fW 819 µs 977 µs 977 µs 26 x 1 fW 1 64 ms 1 9...

Page 270: ...h Timer Configuration The watch timer consists of the following hardware Table 11 2 Watch Timer Configuration Item Configuration Counter 5 bits x 1 Timer clock select register 2 TCL2 Watch timer mode control register TMC2 Control register ...

Page 271: ...y manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watch timer count clock TCL2 sets the watchdog timer count clock and buzzer output frequency Figure 11 1 Watch Timer Block Diagram Selector TMC21 Prescaler Selector Selector Selector INTWT 5 Bit Counter fW 214 fW 213 INTTM3 To 16 Bit Timer Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22...

Page 272: ... 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz fX 211 2 4 kHz MCS 0 fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz fX 210 4 9 kHz fX 212 1 2 kHz Watchdog Timer Count Clock Select...

Page 273: ... R W R W 0 1 TMC23 fXX 5 0 MHz Operation 214 fW 0 4 sec 213 fW 0 2 sec Watch Flag Set Time Selection 0 0 0 0 1 1 Other than above 0 0 1 1 0 0 0 1 0 1 0 1 TMC26 TMC25 TMC24 fXX 5 0 MHz Operation 24 fW 410 s 25 fW 819 s 26 fW 1 64 ms 27 fW 3 28 ms 28 fW 6 55 ms 29 fW 13 1 ms Setting prohibited fXX 4 19 MHz Operation 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms fXT ...

Page 274: ...z 11 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 TMC24 to TMC26 of the watch timer mode control register TMC2 Table 11 3 Interval Timer Interval Time TMC26 TMC25 TMC24 Interval Time When operated at When operated at When operated at f...

Page 275: ...e 12 1 Watchdog Timer Runaway Times Runaway Detection Time MCS 1 MCS 0 211 x 1 fXX 211 x 1 fX 410 µs 212 x 1 fX 819 µs 212 x 1 fXX 212 x 1 fX 819 µs 213 x 1 fX 1 64 ms 213 x 1 fXX 213 x 1 fX 1 64 ms 214 x 1 fX 3 28 ms 214 x 1 fXX 214 x 1 fX 3 28 ms 215 x 1 fX 6 55 ms 215 x 1 fXX 215 x 1 fX 6 55 ms 216 x 1 fX 13 1 ms 216 x 1 fXX 216 x 1 fX 13 1 ms 217 x 1 fX 26 2 ms 217 x 1 fXX 217 x 1 fX 26 2 ms 2...

Page 276: ...64 ms 214 x 1 fX 3 28 ms 214 x 1 fXX 214 x 1 fX 3 28 ms 215 x 1 fX 6 55 ms 215 x 1 fXX 215 x 1 fX 6 55 ms 216 x 1 fX 13 1 ms 216 x 1 fXX 216 x 1 fX 13 1 ms 217 x 1 fX 26 2 ms 217 x 1 fXX 217 x 1 fX 26 2 ms 218 x 1 fX 52 4 ms 219 x 1 fXX 219 x 1 fX 104 9 ms 220 x 1 fX 209 7 ms Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Bit 0 of oscillatio...

Page 277: ...WDTM4 RUN WDTM3 8 Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request RESET INTWDT Non Maskable Interrupt Request Control Circuit 12 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 12 3 Watchdog Timer Configuration Item Configuration Timer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 12 1 Watchdog Timer Block Diagram Con...

Page 278: ...lock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the watch timer count clock and buzzer output frequency ...

Page 279: ...0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 MCS 0 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Watchdog Timer Count Clock Selection 0 1 TCL24 fXX 27 fXT 32 768 kHz MCS 1 fX 27 39 1 kHz MCS 0 fX 28 19 5 kHz Watch Timer Count Clock Selection 0 1 1 1 1 x 0 0 1 1 x...

Page 280: ... up to 0 5 shorter than the time set by timer clock select register 2 TCL2 2 When using the watchdog timer modes 1 and 2 be sure that the interrupt request flag TMIF4 is 0 before setting WDTM4 to 1 If WDTM4 is set to 1 while TMIF4 is 1 a non maskable interrupt requests generated regardless of the contents of WDTM3 Remark x Don t care RUM 7 0 6 0 WDTM4 4 WDTM3 3 2 1 0 FFF9H Address WDTM Symbol 0 0 ...

Page 281: ...to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual runaway detection time may be shorter than the set time by a maximum of 0 5 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 12 4 Watchdog Timer Runaway Detection Time TCL22 TCL21 TCL20 Runaway Detection Time MCS 1 MCS 0 0 0 0 211...

Page 282: ...n Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 12 5 Interval Timer Interval Time TCL22 TCL2...

Page 283: ...the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 PM3 to 0 set to output mode 4 Set bit 7 CLOE of timer clock select register 0 TCL0 to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock output enable disable is switched the clock ...

Page 284: ...trol Circuit Configuration Item Configuration Timer clock select register 0 TCL0 Port mode register 3 PM3 Figure 13 2 Clock Output Control Circuit Block Diagram Control register Internal Bus fXX fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXT CLOE TCL03 TCL02 TCL01 TCL00 P35 Output Latch Synchronizing Circuit 4 PM35 Selector Timer Clock Select Register 0 Port Mode Register 3 PCL P35 ...

Page 285: ...ol the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 This register sets PCL output clock TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 to 00H Remark Besides setting PCL output clock TCL0 sets the 16 bit timer register count clock ...

Page 286: ...TCL01 TCL00 5 00H After Reset R W R W 0 0 0 0 1 1 1 1 1 Other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 TCL03 TCL02 TCL01 fXT 32 768 kHz fXX fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 Setting prohibited MCS 1 fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz MCS 0 fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 15...

Page 287: ...on with fX 5 0 MHz or fXT 32 768 kHz 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 4 Port Mode Register 3 Format PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Sy...

Page 288: ...288 MEMO ...

Page 289: ...e P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 14 2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consists of the following hardware Table 14 1 Buzzer Output Control Circuit Configuration Item Configuration Timer clock select register 2 TCL2 Port mod...

Page 290: ...t function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock ...

Page 291: ...R W R W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 MCS 0 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Watchdog Timer Count Clock Selection 0 1 TCL24 fXX 27 fXT 32 768 kHz MCS 1 fX 27 39 1 kHz MCS 0 fX 28 19 5 kHz Watch Timer Count Clock Selection 0 1 1 1 1 x 0...

Page 292: ... PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 14 3 Port Mode Register 3 Format PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R W R W PM3n 0 1 P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF ...

Page 293: ...input is selected from ANI0 to ANI7 and A D conversion is carried out In the case of hardware start A D conversion operation stops and an interrupt request INTAD is generated when an A D conversion operation ends In the case of software start the A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD is generated 15 2 A D Converter Configuration ...

Page 294: ...ltage Comparator Tap Selector INTAD INTP3 Successive Approximation Register SAR ADIS3 4 Internal Bus A D Converter Input Select Register ADIS2 ADIS1 ADIS0 Note 1 Note 2 INTP3 P03 TRG FR1 FR0 ADM3 ADM2 ADM1 A D Conversion Result Register ADCR AVREF0 AVSS Figure 15 1 A D Converter Block Diagram Notes 1 Selector to select the number of channels to be used for analog input 2 Selector to select the cha...

Page 295: ...to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as input output ports Cautions 1 Use ANI0 to ANI7 input voltages within the specified range If a voltage higher than AVREF0 or lower than AVSS is applied even if within th...

Page 296: ... VSS pin when not using the A D converter 9 AVDD pin This is an A D converter analog power supply pin Keep it at the same potential as the VSS pin when not using the A D converter 15 3 A D Converter Control Registers The following three types of registers are used to control the A D converter A D converter mode register ADM A D converter input select register ADIS External interrupt mode register ...

Page 297: ...3 3 2 1 0 FF80H Address ADM Symbol ADM2 ADM1 HSC 5 01H After Reset R W R W ADM3 0 0 0 0 1 1 1 1 ADM2 0 0 1 1 0 0 1 1 ADM1 0 1 0 1 0 1 0 1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TRG 0 1 External Trigger Selection No external trigger software starts Conversion started by external trigger hardware starts FR1 0 0 1 1 FR0 0 1 0 0 A D Conversion Time SelectionNote 1 fX 5 ...

Page 298: ...g input with ADIS 2 No on chip pull up resistor can be used for the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 15 3 A D Converter Input Select Register Format 0 7 0 6 0 0 4 ADIS3 3 2 1 0 FF84H Address ADIS Symbol ADIS2 ADIS1 ADIS0 5 00H After Reset R W R W ADIS3 0 0 0 0 0 0 0 0 1 Other than above Number of A...

Page 299: ...S41 ES40 5 00H After Reset R W R W ES41 0 0 1 1 ES40 0 1 0 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 0 1 1 ES50 0 1 0 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 0 0 1 1 ES60 0 1 0 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling a...

Page 300: ...voltage tap and analog input is compared with a voltage comparator If the analog input is greater than 1 2 AVREF0 the MSB of SAR remains set If the input is smaller than 1 2 AVREF0 the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 as descr...

Page 301: ... write to ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined SAR ADCR INTAD A D Converter Operation Sampling Time Sampling A D Conversion Conversion Time Undefined 80H C0H or 40H Conversion Result Conversion Result ...

Page 302: ...INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF0 AVREF0 pin voltage ADCR A D conversion result register ADCR Figure 15 6 shows the relation between the analog input voltage and the A D conversion result Figure 15 6 Relationships between Analog Input Voltage and A D Conversion Result VIN AVREF0 AVREF0 256 AVREF0 256 1 512 1 256 3 512 2 256 5 512 3 256...

Page 303: ...ed to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated another operation is not started until a new external trigger signal is input If data with CS set ...

Page 304: ...d terminated the next A D conversion operation starts immediately The A D conversion operation con tinues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A D conversion operation and starts A D conversion on the newly written data If data with CS set to 0 is written to ADM during A D conversion the A D co...

Page 305: ...be cut in order to minimize the overall system power dissipation In Figure 15 9 the power dissipation can be reduced by outputting a low level signal to the output port in standby mode However there is no precision to the actual AVREF0 voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 15 9 Example of Method of Reducing Current...

Page 306: ...5 10 in order to reduce noise Figure 15 10 Analog Input Pin Disposition 4 Pins ANI0 P10 to ANI7 P17 The analog input pins ANI0 to ANI7 also function as input output port PORT1 pins When A D conversion is performed with any of pins ANI0 to ANI7 selected be sure not to execute an input instruction to PORT 1 while conversion is in progress as this may reduce the conversion resolution Also if digital ...

Page 307: ...e ADM rewrite and when ADIF is read immediately after the ADM rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear the ADIF before it is resumed Figure 15 11 A D Conversion End Interrupt Request Generation Timing Remark n 0 1 7 m 0 1 7 7 AVDD pin The AVDD pin is the analog circuit p...

Page 308: ...308 MEMO ...

Page 309: ... A D conversion by setting the DACE0 and DACE1 of the D A converter mode register DAM There are two types of modes for the D A converter as follows 1 Normal mode Outputs an analog voltage signal immediately after the D A conversion 2 Real time output mode Outputs an analog voltage signal synchronously with the output trigger after the D A conversion Since a sine wave can be generated in the mode t...

Page 310: ... A conversion value set register 1 DACS1 Control register D A converter mode register DAM Figure 16 1 D A Converter Block Diagram Register Selector D A Conversion Value Set Register 1 DACS1 Internal Bus Internal Bus 2R 2R 2R 2R R R Selector 2R 2R 2R 2R R R DAM5 ANO1 P131 ANO0 P130 D A Converter Mode Register DACS1 Write INTTM2 DACS0 Write INTTM1 AVREF1 AVSS D A Conversion Value Set Register 0 DACS...

Page 311: ...ESET input sets these registers to 00H Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression ANOn output voltage AVREF1 x where n 0 1 Cautions 1 In the real time output mode when data that are set in DACS0 and DACS1 are read before an output trigger is generated the previous data are read rather than the set data 2 In the real time output mode data should be set...

Page 312: ...uld be disconnected 2 Always set bits 2 3 6 and 7 to 0 3 When D A conversion is stopped the output state is high impedance 4 The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1 respectively in the real time output mode 0 7 0 6 DAM5 DAM4 4 0 3 2 1 0 FF98H Address DAM Symbol 0 DACE1 DACE0 5 00H After Reset R W R W DAM5 0 1 D A Converter Channel 1 Operating Mode Normal mode Real tim...

Page 313: ... A conversion operations by setting DACE0 and DACE1 respectively of the DAM 4 In the normal mode the analog voltage signals are output to the ANO0 P130 and ANO1 P131 pins immediately after the D A conversion In the real time output mode the analog voltage signals are output synchronously with the output triggers 5 In the normal mode the analog voltage signals to be output are held until new data a...

Page 314: ...f Buffer Amplifier a Inverting amplifier b Voltage follower 2 Output voltage of D A converter Because the output voltage of the converter changes in steps use the D A converter output signals in general by connecting a low pass filter 3 AVREF1 pin When only either one of the D A converter channels is used with AVREF1 VDD the other pins that are not used as analog outputs must be set as follows Set...

Page 315: ...3 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output Channel 2 External clock baud rate generator output MSB LSB switchable as the start bit Serial transfer end interrupt request flag SRIF Clock selection Transfer end flag Transfer method 3 wire serial I O SBI serial bus interface 2 wire serial I O...

Page 316: ...orate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K Series 3 SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SB0 or SB1 SBI mode complies with the NEC serial bus format In the SBI mode transfer data is transmitted received as one of th...

Page 317: ...o lines of serial clock SCK0 and serial data bus SB0 or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in the increased number of available input output port pins Figure 17 1 Serial Bus Interface ...

Page 318: ...ontrol selects either CMOS output or N ch open drain output Register CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit Output Control Selector SI0 SB0 P25 PM25 Output Control SO0 SB1 P26 PM26 Output Control SCK0 P27 PM27 Selector P25 Output Latch P26 Output Latch CLD P27 Output Latch Internal Bus BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Internal ...

Page 319: ...ation instruction This register is not used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operatin...

Page 320: ...l generation It generates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks In the SBI mode When WUPNote is 0 Generates an interrupt request signal every eight serial clocks When WUPNote is 1 Generates an interrupt request signal when the serial I O shift register...

Page 321: ...erial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H ...

Page 322: ... MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz MCS 0 fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22...

Page 323: ...tion enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Caution Do not change the operation mode 3 wire serial I O 2 wire serial I O SBI while operation of the serial interface channel 0 is enabled Stop the serial operation before changing the operation mode ...

Page 324: ...put 1 1 1 x 0 x 0 0 x 0 x 0 0 1 1 Note 3 Note 3 Note 3 Note 3 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 CMOS input output Note 2 WUP 0 1 Wake up Function ControlNote 4 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches...

Page 325: ...Address After Reset R W CMDT Used for command signal output When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W R RELD Bus Release Detection Set Conditions RELD 1 Clear Conditions RELD 0 When bus release signal REL is detected When transfer start instruction is executed If SIO0 and SVA values do not match in address receptio...

Page 326: ...of SCK0 just after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output After completion of transfer 1 R W R ACKD Acknowledge Detection Clear Conditions ACKD 0 Falling edge of the SCK0 immediately after the busy mode is released while executing the transfer start instruction When CSIE0 0 When RESET input...

Page 327: ...t SIC to 0 3 When CSIE0 0 CLD becomes 0 Caution Set bits 0 to 3 to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt ...

Page 328: ...0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 P26 SO0 SB1 and P27 SCK0 pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CS...

Page 329: ...nput output 2 wire serial I O mode See 17 4 4 2 wire serial I O mode operation 1 1 Note 2 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R W 1 17 4 2 3 wire serial I O mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a convent...

Page 330: ...E0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when...

Page 331: ...lly and the interrupt request flag CSIIF0 is set Figure 17 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCK0 pin output level...

Page 332: ...rite to SIO0 The SIO0 shift order remains unchanged Thus switching between the MSB first and LSB first must be performed before writing data to the shift register 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock i...

Page 333: ...n simplifies application programs which control serial interface channel 0 The SBI function is incorporated into various devices including 75X XL Series and 78K Series Figure 17 10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used In SBI the SB0 SB1 serial data bus pin is an open drain output pin and therefore the serial da...

Page 334: ... SBI functions are described below a Address command data identify function Serial data is distinguished into addresses commands and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address reception chip select judgment with the wake up function which can be set reset by software When...

Page 335: ...llows Serial data to be transferred with SBI consists of three kinds of data address command and data Figure 17 11 shows the address command and data transfer timings Figure 17 11 SBI Transfer Timings Remark The broken lines indicate the READY state The bus release signal and the command signal are output by the master device BUSY is output by the slave signal ACK can be output by either the maste...

Page 336: ...ease signal even while data is being transmitted Care should be taken for the wiring b Command signal CMD The command signal is a signal with the SB0 SB1 line which has changed from the high level to the low level when the SCK0 line is at the high level without serial clock output This signal is output by the master device Figure 17 13 Command Signal The command signal indicates that the master de...

Page 337: ... hardware and whether or not 8 bit data matches the own specification number slave address is checked by hardware If the 8 bit data matches the slave address the slave device has been selected After that communication with the master device continues until a release instruction is received from the master device Figure 17 15 Slave Selection with Address SCK0 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8...

Page 338: ...e 17 16 Commands Figure 17 17 Data 8 bit data following a command signal is defined as command data 8 bit data without command signal is defined as data Command and data operation procedures are allowed to determine by user arbitrarily according to communications specifications SCK0 C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 SB0 SB1 Command Command Signal SCK0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 ...

Page 339: ... report to the master device that the slave device is preparing for data transmission reception The READY signal is intended to report to the master device that the slave device is ready for data transmission reception Figure 17 19 BUSY and READY Signals In SBI the slave device notifies the master device of the busy state by setting SB0 SB1 line to the low level The BUSY signal output follows the ...

Page 340: ...mer clock select register 3 TCL3 CSIM 04 0 1 CSIM00 x 0 1 FF60H 00H R WNote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 P25 Pin Function SO0 SB1 P26 Pin Function SCK0 P27 Pin Function x 1 0 x 0 x 0 0 x 0 x 0 0 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 ...

Page 341: ...cuted If SIO0 and SVA values do not match in address reception when WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 When transfer start instruction is executed When bus release signal REL is detected When CSIE0 0 When RESET input is applied Set Conditions CMDD 1 When command signal CMD is detected Acknowledge signal is output in synchronization with ...

Page 342: ...ng edge of SCK0 clock after completion of transfer BSYE Synchronizing Busy Signal Output Control 0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to 0 sets ready state R W Note 1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal Note Busy mode can be cleared by st...

Page 343: ... address register CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 t...

Page 344: ...us signals in SBI Figure 17 20 RELT CMDT RELD and CMDD Operations Master Figure 17 21 RELD and CMDD Operations Slave SCK0 SB0 SB1 RELT CMDT CMDD RELD SIO0 Slave address write to SIO0 Transfer Start Instruction Write FFH to SIO0 Transfer start instruction SIO0 SCK0 SB0 SB1 RELD CMDD Transfer start instruction A7 A6 A1 A0 1 2 7 8 9 READY A7 A6 A1 A0 ACK Slave address When addresses match When addres...

Page 345: ...EL 0 µPD78078 SUBSERIES Figure 17 22 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 6 SB0 SB1 ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output for a period of one clock just after setting ...

Page 346: ... D1 D0 ACK When ACKE 1 at this point ACK signal is output at 9th clock SCK0 SB0 SB1 ACKE 7 8 9 D1 D0 ACK 6 D2 If set during this period and ACKE 1 at the falling edge of the next SCK0 ACK signal is output for a period of one clock just after setting SCK0 SB0 SB1 ACKE 1 2 7 8 9 D7 D6 D2 D1 D0 When ACKE 0 at this point ACK signal is not output SCK0 SB0 SB1 ACKE If set and cleared during this period ...

Page 347: ...tructed in BUSY Figure 17 25 BSYE Operation SCK0 SB0 SB1 ACKD 7 8 9 D1 D0 ACK 6 D2 Transfer Start Instruction SIO0 Transfer Start SB0 SB1 ACKD ACK 9 SIO0 7 8 D1 6 D2 D0 Transfer Start Instruction Transfer Start SCK0 SCK0 SB0 SB1 ACKD ACK 9 Transfer Start Instruction SIO0 7 8 D1 6 D2 D0 D6 D7 BUSY SCK0 SB0 SB1 BSYE 7 8 9 ACK 6 When BSYE 1 at this point BUSY If reset during this period and BSYE 0 at...

Page 348: ...o be output to SB0 SB1 following Acknowledge signal 1 BSYE 0 2 Execution of instruction for data write to SIO0 transfer start instruction Master slave SB0 SB1 rising edge when SCK0 1 Master Bus release signal REL RELT set RELD set CMDD clear CMDD set CMDT set Master Command signal CMD SB0 SB1 falling edge when SCK0 1 Acknowledge signal ACK 1 ACKE 1 2 ACKT set ACKD set Completion of reception Slave...

Page 349: ...erred in synchronization with SCK0 after output of REL and CMD signals Master Commands C7 to C0 Instructions and messages to the slave device Master slave Data D7 to D0 8 bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals Table 17 3 Various Signals in SBI Mode 2 2 When CSIE0 1 execution of instruction for data write to SIO0 serial transfer start instructi...

Page 350: ...rain output an external pull up resistor is necessary Figure 17 26 Pin Configuration Caution Because the N ch open drain output must be high impedance state at time of data reception write FFH to the serial I O shift register 0 SIO0 in advance The N ch open drain can be high impedance state at any time of transfer However when the wake up function specify bit WUP 1 the N ch open drain output is al...

Page 351: ...s SB0 SB1 status being transmitted is fetched into the destination device that is the serial I O shift register 0 SIO0 Thus transmit errors can be detected in the following way a Method of comparing SIO0 data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Tra...

Page 352: ... Program Processing CMDD Set INTCSI0 Generation ACK Output Hardware Operation CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Clear CMDD Set RELD Set Serial Reception BUSY Output READY When SVA SIO0 Address BUSY Clear BUSY Clear Figure 17 27 Address Transmi...

Page 353: ...peration ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Set Serial Reception BUSY Output READY Command BUSY Clear BUSY Clear SIO0 Read Command analysis Figure 17 28 Command Transmission from Master...

Page 354: ...SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver Serial Reception BUSY Output READY Data BUSY Clear BUSY Clear SIO0 Read Figure 17 29 Data Transmission from Master Device to Slave Devi...

Page 355: ...Operation Program Processing INTCSI0 Generation ACKD Set Hardware Operation FFH Write to SIO0 Master Device Processing Receiver Transfer Line Slave Device processing Transmitter Serial Transmission BUSY Output READY Data BUSY Clear Write to SIO0 SCK0 Stop BUSY Clear 1 2 READY BUSY D7 D6 ACKT Set SIO0 Read Receive data processing FFH Write to SIO0 Write to SIO0 Figure 17 30 Data Transmission from S...

Page 356: ...e control register SBIC 3 Set 0 to the output latch of P25 and P26 to which 1 has been set 10 How to detect the busy state in a slave When device is in the master mode follow the procedure below to judge whether slave device is in the busy state or not 1 Detect acknowledge signal ACK or interrupt request signal generation 2 Set the port mode register PM25 or PM26 of the SB0 P25 or SB1 P26 pin into...

Page 357: ...ile the SCK0 line is at high level it is recognized as either a bus release signal or a command signal Therefore if the changing timing of bus fluctuates because of the wiring capacitance etc this may be wrongly interpreted as a bus release signal or a command signal even while data is being transmitted Care should be taken in the wiring 17 4 4 2 wire serial I O mode operation The 2 wire serial I ...

Page 358: ... 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 CMOS input output 3 wire Serial I O mode See 17 4 2 3 wire serial I O mode operation SBI mode See 17 4 3 SBI mode operation COI 0 Slave Address Comparison Result FlagNote 4 Slave address register SVA not equal to serial I O shift register 0 SIO0 data Slave address regist...

Page 359: ...E0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when...

Page 360: ... 3 to 0 Remark CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SIC 0 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface...

Page 361: ...de Timings The SB0 or SB1 pin specified for the serial data bus is an N ch open drain input output pin and thus it must be externally connected to a pull up resistor Because it is necessary to set the N ch open drain output to high impedance state for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO0 latch status and thus the SB0 or SB1 pin output status can be manip...

Page 362: ...omatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is the serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmission to that after transmission In this case if two da...

Page 363: ...so possible by software in addition to normal serial clock output P27 output latch manipulation enables setting any value to SCK0 by software SI0 SB0 and SO0 SB1 pin to be controlled with the RELT and CMDT bits of the serial bus interface control register SBIC SCK0 P27 pin output manipulating procedure is described below 1 Set the serial operating mode register 0 CSIM0 SCK0 pin enabled for serial ...

Page 364: ...364 MEMO ...

Page 365: ...XX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Serial transfer end interrupt request flag CSIIF0 Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Automatic transmit receive function Serial transfer end interrupt request flag CSIIF1 Channel 2 External clock baud rate genera...

Page 366: ...and serial input SI0 This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conventi...

Page 367: ...with the I2 C bus format In this mode the transmitter outputs three kinds of data onto the serial data bus start condition data and stop condition to be actually sent or received The receiver automatically distinguishes the received data into start condition data or stop condition by hardware Figure 18 1 Serial Bus Configuration Example Using I2 C Bus Master CPU SCL SDA0 SDA1 SCL SDA0 SDA1 Slave C...

Page 368: ...Configuration Item Configuration Serial I O shift register 0 SIO0 Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 7 Block Diagram of P20 P21 P23 to P26 and Figure 6 8 Block Diagram of P22 and P27...

Page 369: ...Output Latch P26 Output Latch CLD P27 Output Latch Internal Bus BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Internal Bus Stop Condition Start Condition Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CLR D SET Q Match Acknowledge Output Circuit Request Interrupt Signal Generator ACKD CMDD RELD WUP Selector Selector TCL33 TCL32 TCL31 TCL30 4 Timer Clock Select Register 3 fXX 2 to...

Page 370: ...in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 CSIM0 becomes 1 Address of...

Page 371: ...ting to coordinate receive time and processing systematically using software ACK information is generated by the receiving side thus ACKE should be set to 0 disable 1 1 0 An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK information is generated by the receiving side thus ACKE should be set to 0 disable Other than above Setting prohibited I2 C bus mode...

Page 372: ...nterface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT ...

Page 373: ... 1 Setting prohibited fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 MCS 1 Setting prohibited fX 22 1 25 MHz fX 23 6...

Page 374: ... enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Caution Do not change the operation mode 3 wire serial I O 2 wire serial I O I2 C bus while the operation of the serial interface channel 0 is enabled Stop the serial operation before changing the operation mode ...

Page 375: ...Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 SDA0 P25 Pin Function SO0 SB1 SDA1 P26 Pin Function SCK0 SCL P27 Pin Function x 1 MSB LSB 1 x 0 0 0 1 Note 3 3 wire serial l O mode SI0 Input SO0 CMOS output SCK0 CMOS input output Note 3 2 wire serial l O mode or I2 C bus mode 0 SCK0 SCL N ch open drain input output 1 1 1 x 0 x 0 0 x 0 x 0 0 1 ...

Page 376: ...en CSIE0 0 When RESET input is applied R CMDD Start Condition Detection Clear Conditions CMDD 0 When transfer start instruction is executed When stop condition signal is detected When CSIE0 0 When RESET input is applied Set Conditions CMDD 1 When start condition signal is detected ACKT Used to generate the ACK signal by software when 8 clock wait mode is selected Keeps SDA0 SDA1 low from set instr...

Page 377: ...utput with ACKT is enabled Used for reception when 8 clock wait mode is selected or for transmission Note 2 Enables acknowledge signal automatic output Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait mode selected...

Page 378: ... when the state is cancelled Used to cancel wait state by means of WAT0 and WAT1 CLC 0 1 Clock Level ControlNote 2 Used in I2 C bus mode Make output level of SCL pin low unless serial transfer is being performed R W 1 Wait Sate Cancellation Control R W WAT1 0 1 Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle keeping clock output in high impedan...

Page 379: ...terrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt Cause SelectionNote 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer CLD 0 1...

Page 380: ... 0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 and P27 SCK0 SCL pins can be used as general input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET...

Page 381: ... 0 0 1 Note 2 3 wire serial l O mode SI0 Input SO0 CMOS output SCK0 CMOS input output I2 C bus mode See 18 4 4 I2 C bus mode operation Note 2 Note 3 Note 2 CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R W 1 or 18 4 2 3 wire serial I O mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which i...

Page 382: ...red to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Remark CSIE0 Bit 7 of serial operating mode reg...

Page 383: ... and the interrupt request flag CSIIF0 is set Figure 18 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by setting the bit 0 RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCK0 pin output leve...

Page 384: ...er for data write to SIO0 The SIO0 shift order remains unchanged Thus MSB first and LSB first must be switched before writing data to the shift register 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock is stopped ...

Page 385: ... wire serial I O mode can cope with any communication format by program Communication is basically carried out with two lines of serial clock SCK0 and serial data input output SB0 or SB1 Figure 18 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode Master SCK0 Slave SB0 SB1 SCK0 SB0 SB1 VDD VDD ...

Page 386: ...utput 1 1 1 x 0 x 0 0 x 0 x 0 0 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 SDA0 N ch open drain input output SB1 SDA1 N ch open drain input output P26 CMOS input output 3 wire Serial I O mode See 18 4 2 3 wire serial I O mode operation Note 3 COI 0 Slave Address Comparison Result FlagNote 4 Slave address register SVA not equal to serial I O shift register 0 SIO0 data Slave addre...

Page 387: ... operating mode register 0 CSIM0 c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Notes 1 Bit 6 CLD is a read only bit 2 When CSIE0 0 CLD becomes 0 Caution Set bits 0 to 3 to 0 when the 2 wire serial I O mode is selected Remark CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operatin...

Page 388: ...pt request flag CSIIF0 is set Figure 18 11 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus is an N ch open drain input output and thus it must be externally connected to a pull up resistor Because it is necessary to set N ch open drain output to high impedance state for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO0 latch status...

Page 389: ...bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is the serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmission to that after tra...

Page 390: ...ification the master sends start condition data and stop condition signals to slave devices through the serial data bus while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This simplifies the application program to control I2 C bus An example of a serial bus configuration is shown in Figure 18 13 This system bel...

Page 391: ...2 C bus can operate independently during the serial communication d Acknowledge signal ACK control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function When a slave device is preparing for data transmission or reception and requires more waiting time the slave devic...

Page 392: ...vice on the bus line must therefore have a different address Therefore after a slave device detects the start condition it compares the 7 bit address data received and the data of the slave address register SVA After the comparison only the slave device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master de...

Page 393: ...nowledge signal which will be sent from the receiving side If the sending side device receives the acknowledge signal which means a successful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received by the slave device and therefore the master device outputs a stop condition signal to terminate subse...

Page 394: ...ng operation of slave devices refer to 18 4 5 Cautions on use of I2 C bus mode Figure 18 20 Wait Signal a Wait of 8 Clock Cycles b Wait of 9 Clock Cycles SCL of master device D2 D1 D0 ACK D7 Output by manipulating ACKT 6 7 8 9 1 3 2 4 D6 D5 D4 Set low because slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device starts...

Page 395: ...ote 3 serial I O or N ch open CMOS I O N ch open I2C bus mode drain I O drain I O R W WUP Wake up Function ControlNote 4 0 Interrupt request signal generation with each serial transfer in any mode 1 In I2C bus mode interrupt request signal is generated when the address data received after start condition detection when CMDD 1 matches data in slave address register SVA R COI Slave Address Compariso...

Page 396: ...oftware if the 8 clock wait mode is selected Cleared to 0 if CSIE 0 when a transfer by the serial interface is started R W ACKE Acknowledge Signal Automatic Output ControlNote 2 0 Disabled with ACKT enabled Used when receiving data in the 8 clock wait mode or when transmitting data Note 3 1 Enabled After completion of transfer acknowledge signal is output in synchronization with the 9th falling ed...

Page 397: ...eleased 1 Releases the wait state Automatically cleared to 0 after releasing the wait state This bit is used to release the wait state set by means of WAT0 and WAT1 R W CLC Clock level control 0 Used in I2C bus mode In cases other than serial transfer SCL pin output is driven low 1 Used in I2C bus mode In cases other than serial transfer SCL pin output is set to high impedance Clock line is held h...

Page 398: ...flag s CSIIF0 Also see Note 3 below Address A6 to A0 Definition 7 bit data synchronized with SCL immediately after start condition signal Function Indicates address value for specification of slave on serial bus Signaled by Master Signaled when See Note 2 below Affected flag s CSIIF0 Also see Note 3 below Transfer direction R W Definition 1 bit data output in synchronization with SCL after address...

Page 399: ...rs for both master and slave devices Note that pull up resistors are required to connect to both serial clock line and serial data bus line because open drain buffers are used for the serial clock pin SCL and the serial data bus pin SDA0 or SDA1 on the I2 C bus Figure 18 21 Pin Configuration Caution Because the N ch open drain output must be in the high impedance state during data reception set bi...

Page 400: ...l I O shift register 0 SIO0 of the transmitting device a Comparison of SIO0 data before and after transmission In this case a transmission error is judged to have occurred if the two data values are different b Using the slave address register SVA Transmit data is set in SIO0 and SVA before transmission is performed After transmission the COI bit match signal from the address comparator of serial ...

Page 401: ...L L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L SIO0 address SIO0 data H L L L L L L L H H H H SIO0 FFH SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Processing in master device Transfer line Processing in slave d...

Page 402: ...D3 D2 D1 D0 ACK D6 D7 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L L L SIO0 data SIO0 data H L L L L L L L H H H H SIO0 FFH SIO0 FFH SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Processing in master device Transfer line Processing in slave devi...

Page 403: ...ransfer line L L 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 5 6 7 8 A6 A5 A4 A3 1 2 3 4 9 L L L L SIO0 data SIO0 address H L L L L H H H SIO0 FFH SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 SIO0 FFH Processing in master device Processing in slave device ...

Page 404: ...ess L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 address SIO0 FFH H L L L L L L L H H SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 SIO0 data Processing in master device Transfer line Processing in slave devic...

Page 405: ...D1 D0 D2 D3 D4 D5 D6 D7 ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 FFH SIO0 FFH H L L L L L L L L L L H H SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 SIO0 data SIO0 data Processing in master device Transfer line Processing in slave devi...

Page 406: ...tion L L 1 D1 D0 D2 D3 D4 D5 D6 D7 NAK 2 3 4 5 6 7 8 A6 A5 A4 A3 1 2 3 4 9 L L SIO0 FFH Processing in master device Transfer line SIO0 address H L L L L L L H H SIO0 write COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 write COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Processing in slave device SIO0 data ...

Page 407: ...ause the N ch open drain output must be high impedance state during data reception set bit 7 BSYE of the serial bus interface control register SBIC to 1 before writing FFH to SIO0 However do not write FFH to the SIO0 during data reception when using the wake up function setting the bit 5 WUP of the serial operation mode register 0 CSIM0 N ch open drain output always enters the high impedance state...

Page 408: ...ut a start condition signal Set the bit 3 CLC of the interrupt timing specify register SINT to drive the SCL pin high After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output If it is the master device which outputs the start condition and stop condition signals confirm that CLD is set to 1 after setting CLC to 1 a slave device may have set SCL to l...

Page 409: ...At this time control the low level width a in Figure 18 25 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction In addition if the acknowledge signal from the master is not output if data transmission from the slave is completed set 1 in the WREL flag of SINT and release the wait For these timings see Figure 18 23 Figure 18...

Page 410: ...program as shown in Figure 18 26 to receive data correctly For these timings see Figure 18 22 Figure 18 26 Slave Wait Release Reception 4 Reception completion of slave During processing of reception completion by a slave device confirm the statuses of CMDD and COI if CMDD 1 This procedure is necessary to use the wake up function normally If an uncertain amount of data is sent from the master devic...

Page 411: ... executing the wake up function execute the following program that releases serial transfer status To execute the wake up function do not execute an instruction that writes SIO0 Even if such an instruction is not executed data can be received when the wake up function is executed This program releases the serial transfer status To release the serial transfer status the serial interface channel 0 m...

Page 412: ...d 3 Sets the P27 SCL pin in the input mode to prevent the SCL line from being affected when the port mode is set by the instruction in 4 The P27 pin is set in the input mode when the instruction in 3 is executed 4 Changes the mode from the I2 C bus mode to port mode 5 Restores the mode from the port mode to the I2 C bus mode 6 Prevents the instruction in 8 from causing the SDA0 pin to output a low...

Page 413: ...cribed below 1 In 3 wire serial I O mode and 2 wire serial I O mode The SCK0 SCL P27 pin output level is manipulated by the P27 output latch 1 Set serial operating mode register 0 CSIM0 SCK0 pin is set in the output mode and serial operation is enabled While serial transfer is suspended SCK0 is set to 1 2 Manipulate the content of the P27 output latch by executing the bit manipulation instruction ...

Page 414: ...xecuting the bit manipulation instruction Figure 18 28 SCK0 SCL P27 Pin Configuration Note The level of SCL signal follows the contents of logic circuit shown in Figure 18 29 Figure 18 29 Logic Circuit of SCL Signal Remarks 1 This figure shows the relationship of each signal and does not show the internal circuit 2 CLC Bit 3 of interrupt timing specify register SINT To Internal Circuit SCK0 SCL P2...

Page 415: ...he start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB connection is enabled with either start bit device The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K Series 3 3 wire serial I O mode with automatic transmit receive funct...

Page 416: ...26 and Figures 6 6 and 6 8 Block Diagram of P22 and P27 Figure 19 1 Serial Interface Channel 1 Block Diagram RE ARLD ERCE ERR TRF STRB BUSY 1 BUSY 0 Internal Bus Automatic Data Transmit Receive Control Register Serial Operating Mode Register 1 ADTI 7 ADTI 4 ADTI 3 ADTI 2 ADTI 1 ADTI 0 5 Bit Counter Serial I O Shift Register 1 SIO1 Hand shake Serial Clock Counter Selector Selector SO1 P21 PM21 P21 ...

Page 417: ...RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register stores the value number of transmit data bytes 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP is set with an 8 bit memory ...

Page 418: ...ct Register 3 Format Caution When rewriting other data to TCL3 stop the serial transfer operation beforehand Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fX 5 0 MHz Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0...

Page 419: ... P20 PM21 P21 PM22 Shift Register 1 Operation Serial Clock Counter Operation Control SI1 P20 Pin Function SCK1 P22 Pin Function x 1 0 1 0 x 0 0 1 x 1 Note 2 Note 2 Note 2 Note 2 Count operation SI1Note 3 input x x x x x Operation stop Clear P20 CMOS input output P22 CMOS input output ATE 0 1 Serial Interface Channel 1 Operating Mode Selection 3 wire serial I O mode 3 wire serial I O mode with auto...

Page 420: ...l ADTC RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H 00H R WNote 1 Address After Reset R W BUSY1 0 1 1 Busy Input Control Not using busy input Busy input enable active high Busy input enable active low BUSY0 x 0 1 STRB 0 1 Strobe Output Control Strobe output disable Strobe output enable TRF 1 Status in Automatic Transmit Receive FunctionNote 2 Detection of termination of automatic transmission recep...

Page 421: ...ystem clock frequency fX or fX 2 fX Main system clock oscillation frequency fSCK Serial clock frequency 26 28 0 5 fXX 26 36 1 5 fXX fXX fSCK fXX fSCK Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 18 4 s 0 5 fSCK 31 2 s 0 ...

Page 422: ...frequency 26 28 0 5 fXX fXX fSCK 26 36 1 5 fXX fXX fSCK Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 223 2 s 0 5 fSCK 236 0 s 0 5 fSCK 248 8 s 0 5 fSCK 261 6 s 0 5 fSCK 274 4 s 0 5 fSCK 287 2 s 0 5 fSCK 300 0 s 0 5 fSCK 31...

Page 423: ...X fXX 0 5 fSCK 1 5 fSCK Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 36 8 s 0 5 fSCK 62 4 s 0 5 fSCK 88 0 s 0 5 fSCK 113 6 s 0 5 fSCK 139 2 s 0 5 fSCK 164 8 s 0 5 fSCK 190 4 s 0 5 fSCK 216 0 s 0 5 fSCK 241 6 s 0 5 fSCK 2...

Page 424: ...a Transmit Receive Interval Specify Register Format 4 4 Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 446 4 s 0 5 fSCK 472 0 s 0 5 fSCK 497 6 s 0 5 fSCK 523 2 s 0 5 fSCK 548 8 s 0 5 fSCK 574 4 s 0 5 fSCK 600 0 s 0 5 fSCK 62...

Page 425: ...rating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Notes 1 Can be used freely as port function 2 Can be used as P20 CMOS input output when only transmitter is used set bit 7 RE of the automatic data transmit receive control register ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch Operation enable...

Page 426: ...ddress After Reset R W ATE 0 1 Serial Interface Channel 1 Operating Mode Selection 3 wire serial I O mode 3 wire serial I O mode with automatic transmit receive function DIR 0 1 Start Bit MSB LSB SI1 Pin Function SI1 P20 Input SO1 Pin Function SO1 CMOS output Operation enable SCK1 Input CSIE 1 0 CSIM 11 P20 PM21 P21 PM22 Shift Register 1 Operation Serial Clock Counter Operation Control SI1 P20 Pin...

Page 427: ...t transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 19 6 3 Wire Serial I O Mode Timings Caution SO1 pin becomes low level by SIO1 write 3 MSB LSB switching as the start bit The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 19 7 shows the configuration of the serial I O shift register 1 SIO1 and internal bus As sh...

Page 428: ...nsfer data to the serial I O shift register 1 SIO1 when the following two conditions are satisfied Serial interface channel 1 operation control bit CSIE1 1 Internal serial clock is stopped or SCK1 is a high level after 8 bit serial transfer Caution If CSIE1 is set to 1 after data write to SIO1 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the in...

Page 429: ...et to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is used set bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch Operation enable 6 5 4 3 2 1 0 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 CSIM11 0 1 Ser...

Page 430: ...bit is set to 1 when data is written to SIO1 R W R W R R ERR 0 1 Error Detection of Automatic Transmit Receive Function No error This bit is set to 0 when data is written to SIO1 Error occurred R W ARLD 0 1 Operating Mode Selection of Automatic Transmit Receive Function Single operating mode Repetitive operating mode R W RE 0 1 Receive Control of Automatic Transmit Receive Function Receive disable...

Page 431: ...n system clock oscillation frequency fSCK Serial clock frequency fXX fSCK 28 0 5 26 fXX fXX 26 fXX fSCK 36 1 5 MinimumNote 2 18 4 s 0 5 fSCK 31 2 s 0 5 fSCK 44 0 s 0 5 fSCK 56 8 s 0 5 fSCK 69 6 s 0 5 fSCK 82 4 s 0 5 fSCK 95 2 s 0 5 fSCK 108 0 s 0 5 fSCK 120 8 s 0 5 fSCK 133 6 s 0 5 fSCK 146 4 s 0 5 fSCK 159 2 s 0 5 fSCK 172 0 s 0 5 fSCK 184 8 s 0 5 fSCK 197 6 s 0 5 fSCK 210 4 s 0 5 fSCK MaximumNot...

Page 432: ...K 26 fXX 26 fXX MinimumNote 223 2 s 0 5 fSCK 236 0 s 0 5 fSCK 248 8 s 0 5 fSCK 261 6 s 0 5 fSCK 274 4 s 0 5 fSCK 287 2 s 0 5 fSCK 300 0 s 0 5 fSCK 312 8 s 0 5 fSCK 325 6 s 0 5 fSCK 338 4 s 0 5 fSCK 351 2 s 0 5 fSCK 364 0 s 0 5 fSCK 376 8 s 0 5 fSCK 389 6 s 0 5 fSCK 402 4 s 0 5 fSCK 415 2 s 0 5 fSCK MaximumNote 224 8 s 1 5 fSCK 237 6 s 1 5 fSCK 250 4 s 1 5 fSCK 263 2 s 1 5 fSCK 276 0 s 1 5 fSCK 288...

Page 433: ...8 s 0 5 fSCK 62 4 s 0 5 fSCK 88 0 s 0 5 fSCK 113 6 s 0 5 fSCK 139 2 s 0 5 fSCK 164 8 s 0 5 fSCK 190 4 s 0 5 fSCK 216 0 s 0 5 fSCK 241 6 s 0 5 fSCK 267 2 s 0 5 fSCK 292 8 s 0 5 fSCK 318 4 s 0 5 fSCK 344 0 s 0 5 fSCK 369 6 s 0 5 fSCK 395 2 s 0 5 fSCK 420 8 s 0 5 fSCK MaximumNote 2 40 0 s 1 5 fSCK 65 6 s 1 5 fSCK 91 2 s 1 5 fSCK 116 8 s 1 5 fSCK 142 4 s 1 5 fSCK 168 0 s 1 5 fSCK 193 6 s 1 5 fSCK 219 ...

Page 434: ...36 1 5 fXX fSCK MaximumNote 449 6 s 1 5 fSCK 475 2 s 1 5 fSCK 500 8 s 1 5 fSCK 526 4 s 1 5 fSCK 552 0 s 1 5 fSCK 577 6 µs 1 5 fSCK 603 2 s 1 5 fSCK 628 8 s 1 5 fSCK 654 4 s 1 5 fSCK 680 0 s 1 5 fSCK 705 6 s 1 5 fSCK 731 2 s 1 5 fSCK 756 8 s 1 5 fSCK 782 4 s 1 5 fSCK 808 0 s 1 5 fSCK 833 6 s 1 5 fSCK Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 ...

Page 435: ...tomatic data transmit receive interval specify register ADTI 4 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are carried out After the buffer RAM data specified with ADTP ...

Page 436: ...ication operation a Basic transmission reception mode This transmission reception mode is the same as the 3 wire serial I O mode in which specified number of data are transmitted received in 8 bit units Serial transfer is started when any data is written to the serial I O shift register 1 SIO1 while bit 7 CSIE1 of the serial operating mode register 1 CSIM1 is set to 1 Upon completion of transmissi...

Page 437: ... Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission reception operation Write receive data from SIO1 to buffer RAM Pointer value 0 No TRF 0 No End Yes Yes Decrement pointer value Software Execu...

Page 438: ...ission reception point refer to Figure 19 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the buffer RAM and ADTP is decremented iii Completion of transmission reception refer to Figure 19 10 c When transmission of the sixt...

Page 439: ...n reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H Receive data 4 R4 SIO1 0 CSIIF1 2 ADTP 1 Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP c Completion of transmission reception ...

Page 440: ... 11 shows the basic transmission mode operation timings and Figure 19 12 shows the operation flowchart Figure 19 13 shows an example of the buffer RAM operation in 6 byte transmission Figure 19 11 Basic Transmission Mode Operation Timings Cautions 1 Because in the basic transmission mode the automatic transmit receive function reads data from the buffer RAM after 1 byte transmission an interval is...

Page 441: ...transmit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No TRF 0 No End Yes Yes Decrement poi...

Page 442: ...nsferred from the buffer RAM to SIO1 ii 4th byte transmission point refer to Figure 19 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP is decremented iii Completion of transmission reception refer to Figure 19 13 c When transmission of the sixth byte is completed the interrupt ...

Page 443: ...point c Completion of transmission reception Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 2 ADTP 1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP ...

Page 444: ... not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary input output ports The repeat transmission mode operation timing is shown in Figure 19 14 and the operation flowchart in Figure 19 15 Figure 19 16 shows an example of the buffer RAM operation in 6 byte repeat transmission Figure 19 14 Repeat Transmission Mode Operation Timing Caution Since in the repeat transmission mode ...

Page 445: ...O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No Yes Decrement pointer value Software Execution Hardwar...

Page 446: ...o SIO1 ii Upon completion of transmission of 6 bytes refer to Figure 19 16 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The first pointer value is set to ADTP again iii 7th byte transmission point refer to Figure 19 16 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When transmission of the first byte is completed ADTP is dec...

Page 447: ...ssion of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP 1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP 1 ...

Page 448: ...t mode For restart of automatic transmission reception remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 If the HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set if during 8 bit data transfer When the HALT mode is cleared automatic transmission reception i...

Page 449: ...ice inputs the busy signal output by the slave device to pin BUSY P24 In sync with the fall of the serial clock the master device samples the input busy signal Even if the busy signal becomes active during sending or receiving of 8 bit data the wait does not apply If the busy signal becomes active at the rise of the serial clock 2 clock cycles after sending or receiving of 8 bit data ends the busy...

Page 450: ...with the serial clock so even if the slave side inactivates the busy signal it takes nearly 1 clock cycle at the most until it is sampled again Also it takes another 0 5 clock cycle after sampling until data transmission resumes Therefore in order to definitely cancel a wait state it is necessary for the slave side to keep the busy signal for at least 1 5 clock cycles Figure 19 20 shows the timing...

Page 451: ...ration mode register 1 CSIM1 at 1 Set bit 2 STRB of the automatic data transmit receive control register ADTC at 1 Normally busy control and strobe control are used simultaneously as handshake signals In this case together with output of the strobe signal from pin STB P23 pin BUSY P24 can be sampled and sending or receiving can wait while the busy signal is being input If strobe control is not car...

Page 452: ...ion When TRF is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF Bit 3 of the automatic data transmit receive control register ADTC SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TRF Busy Input Valid Busy Input Clear CSIIF1 ...

Page 453: ...hin 2 clock cycles The master device side samples the busy signal in sync with the fall of the serial clock s front side If no bit slippage is occurring the busy signal will be inactive in sampling for 8 clock cycles If the busy signal is found to be active in sampling it is regarded as an occurrence of bit slippage error processing is executed bit 4 ERR of the automatic data transmit receive cont...

Page 454: ... receive interval specification register ADTI and the CPU processing at the rising edge of the eighth serial clock Whether it depends on the ADTI or not can be selected by the setting of its bit 7 ADTI7 When it is set to 0 the interval depends only on the CPU processing When it is set to 1 the interval depends on the contents of the ADTI or CPU processing whichever is greater When the automatic tr...

Page 455: ...PU Processing when the Internal Clock is Operating CPU Processing Interval Time When using multiplication instruction Max 2 5TSCK 13TCPU When using division instruction Max 2 5TSCK 20TCPU External access 1 wait mode Max 2 5TSCK 9TCPU Other than above Max 2 5TSCK 7TCPU TSCK 1 fSCK fSCK Serial clock frequency TCPU 1 fCPU fCPU CPU clock set by bits 0 to 2 PCC0 to PCC2 of the processor clock control r...

Page 456: ...t the interval may be longer than the values shown as follows Table 19 3 Interval Timing through CPU Processing when the External Clock is Operating CPU Processing Interval Time When using multiplication instruction 13TCPU or longer When using division instruction 20TCPU or longer External access 1 wait mode 9TCPU or longer Other than above 7TCPU or longer TCPU 1 fCPU fCPU CPU clock set by the bit...

Page 457: ... be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 3 3 wire serial I O mode MSB first LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines SI2 SO2 In the 3 wire serial I O mode simultaneous transmission and reception ...

Page 458: ... Block Diagram of P71 and P72 Figure 20 1 Serial Interface Channel 2 Block Diagram Note See Figure 20 2 for the baud rate generator configuration Internal Bus RXE PS1 PS0 Asynchronous Serial Interface Mode Register CL SL ISRM TXE SCK PE FE OVE Asynchronous Serial Interface Status Register Direction Control Circuit Transmit Shift Register TXS SIO2 Receive Buffer Register RXB SIO2 Direction Control ...

Page 459: ...Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5 Bit Counter Selector Selector Decoder 1 2 Selector Terminal Clock 1 2 Selector Receive Clock Match Match MDL0 to MDL3 5 Bit Counter RXE Start Bit Detection Selector fxx to fxx 210 TPS0 to TPS3 SCK CSCK ASCK SCK2 P72 4 4 Start Bit Sampling Clock ...

Page 460: ...ive data Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB of RXB is always set to 0 RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution RXB and the transmit shif...

Page 461: ...ed in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Figure 20 3 Serial Operating Mode Register 2 Format Cautions 1 Ensure that bits 0 and 3 to 6 are set to 0 2 When UART mode is selected CSIM2 should be set to 00H 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 FF72H 00H R W Address After Reset R W CSCK 0 1 Clo...

Page 462: ...d TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No parity Even parity PS0 0 1 0 parity always added in transmission No parity test in reception parity error not generated 0 1 1 Odd parity 0 2 Asynchronous serial interface mode register ASIM This register is set when serial interface channel 2 is used in ...

Page 463: ...ut SCK2 output Other than above Setting prohibited Note 2 SI2 Note 2 SO2 CMOS output P72 SCK2 ASCK Pin Functions P71 SO2 TxD Pin Functions P70 SI2 RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM71 P71 PM72 P72 ASIM CSIM2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 x Note 1 x Note 1 0 1 1 1 x x LSB External clock Internal clock External clock Internal clock External clock Inte...

Page 464: ...W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read FE 0 1 Framing Error Flag Framing error not generated Framing error generatedNote 2 When stop bit is not detected PE 0 1 Parity Error Flag Parity error not generated Parity error generated When transmit data parity does not...

Page 465: ...mode Remarks 1 fSCK 5 bit counter source clock 2 k Value set in MDL0 to MDL3 0 k 14 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK 16 fSCK 17 fSCK 18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCKNo...

Page 466: ...XX 26 fX 26 78 1 kHz fX 27 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore BRGC must not ...

Page 467: ...0 to MDL3 0 k 14 Table 20 3 Relationship between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1 1...

Page 468: ...om the ASCK pin is obtained with the following expression Baud rate Hz fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 20 4 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 kH...

Page 469: ...1 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Operation stop mode is set using serial operating mode register 2 CSIM2 and the asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H CSIM 22 6 5 4 3 2 1 0 7 Symbol CSIM2 CSI...

Page 470: ...mory manipulation instruction RESET input sets ASIM to 00H SL 6 5 4 3 2 1 0 7 Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R W Address After Reset R W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled ...

Page 471: ... CSIM2 the asynchronous serial interface mode register ASIM the asynchronous serial interface status register ASIS and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H When the UART mode is selected 00H should be set in CSIM2 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 ...

Page 472: ...acter Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No parity Even parity PS0 0 1 0 parity always added in transmission No parity test in reception parity error not generated 0 1 1 Odd...

Page 473: ...ta from receive buffer register is read FE 0 1 Framing Error Flag Framing error not generated Framing error generatedNote 2 When stop bit is not detected PE 0 1 Parity Error Flag Parity error not generated Parity error generated When transmit data parity does not match Notes 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generat...

Page 474: ... 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k 5 Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS 1 MCS 0 0 0 0 0 fXX 210 fX 210 4 9 kHz fX 211 2 4 kHz 11 0 1 0 1 fXX fX 5 0 MHz fX 2 2 5 MHz 1 0 1 1 0 fXX 2 fX 2 2 5 MHz fX 22 1 25 MHz 2 0 1 1 1 fXX 22 fX 22 1 25 MHz fX 23 625 kHz 3 1 0 0 0 fXX 23 fX 23 625 kHz fX 24 313 kHz 4 ...

Page 475: ...rmally Therefore BRGC must not be written to during a communication operation Remarks 1 fSCK 5 bit counter source clock 2 k Value set in MDL0 to MDL3 0 k 14 3 fX Main system clock oscillation frequency 4 fXX Main system clock frequency fX or fX 2 5 MCS Bit 0 of oscillation mode selection register OSMS 6 n Value set in TPS0 to TPS3 1 n 11 7 Figures in parentheses apply to operation with fX 5 0 MHz ...

Page 476: ...DL0 to MDL3 0 k 14 Table 20 5 Relationship between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1...

Page 477: ...the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 20 6 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2...

Page 478: ...bit length for each data frame is carried out with asynchronous serial interface mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is selected by ASIM and the baud rate generator control ...

Page 479: ...is is an odd number a parity error is generated ii Odd parity At transmission Conversely to the situation with even parity control is executed so that the number of bits with a value of 1 contained in the transmit data including parity bit is an odd number The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a va...

Page 480: ...terface Transmission Completion Interrupt Request Generation Timing a Stop bit length 1 b Stop bit length 2 Caution The asynchronous serial interface mode register ASIM should not be rewritten during a transmit operation If the ASIM register is rewritten during transmission subsequent transmit operations may not be possible the normal state is restored by RESET input It is possible to determine wh...

Page 481: ...e frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated If an error is generated the receive data in which the error was generated is still transferred to RXB When an error is generated if bit 1 ISRM of ASIM is cleared to 0 INTSR is generate...

Page 482: ... Causes Receive Errors Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 20 10 Receive Error Timing Note If a receive error is generated while bit 1 ISRM of the asynchronous serial interface mode register ASIM i...

Page 483: ... the state of the receive buffer register RXB and whether a receive completion interrupt request INTSR is generated or not differ depending on the receive stop timing Figure 20 11 shows the timing Figure 20 11 State of Receive Buffer Register RXB When Receive Operation is Stopped and Whether Interrupt Request INTSR is Generated or Not When RXE is set to 0 at a time indicated by 1 RXB holds the pre...

Page 484: ...de register 2 CSIM2 the asynchronous serial interface mode register ASIM and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Caution Ensure that bit 0 and bits 3 through 6 are set to 0 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Clock Select...

Page 485: ... generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No parity Even parity PS0 0 1 0 parity always added in transmiss...

Page 486: ... 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK 16 fSCK 17 fSCK 18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k fSCK 5 bit counte...

Page 487: ...1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore BRGC must not be written to during a communi...

Page 488: ...through MDL3 to 1 1 1 1 The serial clock frequency becomes 1 2 of the source clock frequency for the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with MDL0 through MDL3 and TPS0 through TPS3 Be sure then to set MDL0 through MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula fXX Serial clock frequency Hz 2n x k 16 fX Main syste...

Page 489: ...it in synchronization with the serial clock Transmit shift register TXS SIO2 and receive shift register RXS shift operations are performed in synchronization with the fall of the serial clock SCK2 Then transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bi...

Page 490: ...to SIO2 The SIO2 shift order remains unchanged Thus MSB first and LSB first must be switched before writing data to the shift register 4 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or SCK2 is a h...

Page 491: ...ed to be generated will be generated Figure 20 14 illustrates the operation above Figure 20 14 Receive Completion Interrupt Request Generation Timing ISRM 1 Remark ISRM Bit 1 of asynchronous serial interface mode register ASIM fSCK 5 bit counter source clock of baud rate generator RXB Receive buffer register To avoid this phenomenon implement the following countermeasures Countermeasures In the ca...

Page 492: ...fSCK selected with BRGC Example of countermeasures An example of the countermeasures is shown below Condition fX 5 0 MHz Processor clock control register PCC 00H Oscillation mode selection register OSMS 01H Baud rate generator control register BRGC B0H when 2400 bps is selected for baud rate TCY 0 4 µs tCY 0 2 µs 1 T1 416 7 µs 2400 T2 12 8 x 2 25 6 µs T1 T2 2212 clock tCY RxD input INTSR INTSER wh...

Page 493: ... Example INTSER is generated 7 clocks MIN of CPU clock time from interrupt request to servicing Instructions for 2205 clocks MIN of CPU clock are required UART receive error interrupt request INTSER servicing EI RETI MOV A RXB Main processing ...

Page 494: ...494 MEMO ...

Page 495: ...real time output port mode can be specified bit wise 21 2 Real Time Output Port Configuration The real time output port consists of the following hardware Table 21 1 Real time Output Port Configuration Item Configuration Register Real time output buffer register RTBL RTBH Control register Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTP...

Page 496: ... time Output Buffer Register Configuration Table 21 2 Operation in Real time Output Buffer Register Manipulation In ReadNote 1 In WriteNote 2 Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits RTBL RTBH RTBL Invalid RTBL RTBH RTBH RTBL RTBH Invalid RTBL RTBH RTBL RTBH RTBL RTBH RTBH RTBL RTBH RTBL Notes 1 Only the bits set in the real time output port mode can be read When a read is performed t...

Page 497: ... port mode bit wise RTPM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 21 4 Real time Output Port Mode Register Format Cautions 1 When using these bits as a real time output port set the ports to which real time output is performed to the output mode set the bits of the port mode register 12 PM12 to 0 2 In the port specified as a real tim...

Page 498: ...ol register RTPC This register sets the real time output port operating mode and output trigger Table 21 3 shows the relationship between the real time output port operating mode and output trigger RTPC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 21 5 Real time Output Port Control Register Format Table 21 3 Real time Output Port Operati...

Page 499: ...an be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H and PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 22 1 A standby release signal is generat...

Page 500: ...r End of serial interface channel 1 transfer Serial interface channel 2 UART reception error generation End of serial interface channel 2 UART reception End of serial interface channel 2 3 wire transfer End of serial interface channel 2 UART transfer INTWDT A 0 INTWDT B 8 INTCSI0 0014H 9 INTCSI1 0016H 11 001AH INTSR INTCSI2 12 INTST 001CH Interrupt Type Default PriorityNote 1 Internal External Vec...

Page 501: ...onversion 0028H Generation of 8 bit timer event counter 5 match signal Generation of 8 bit timer event counter 6 match signal Software BRK BRK instruction execution 003EH E Vector Table Address 14 INTTM00 0020H 15 INTTM01 0022H Maskable 16 INTTM1 Internal 0024H B 17 INTTM2 0026H 19 INTTM5 002AH 20 INTTM6 002CH Notes 1 Default priorities are intended for two or more simultaneously generated maskabl...

Page 502: ... Request B Internal maskable interrupt Internal Bus IE PR ISP MK IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal C External maskable interrupt INTP0 Internal Bus IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Sampling Clock Edge Detector Sampling Clock Select Register SCS External ...

Page 503: ...ode Register INTM0 INTM1 Edge Detector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Internal Bus Priority Control Circuit Vector Table Address Generator Interrupt Request IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag ...

Page 504: ...sources Table 22 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTP6 PIF6 PMK6 PPR6 INTCSI0 CSIIF0 IF0H CSIMK0 M...

Page 505: ...input sets these registers to 00H Figure 22 2 Interrupt Request Flag Register Format Note WTIF is test input flag Vectored interrupt request is not generated Cautions 1 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer If used in the watchdog timer mode 1 set TMIF4 flag to 0 2 Set always 0 in IF1L bit 5 and bit 6 7 PIF6 Symbol IF0L 6 PIF5 5 PIF4 4 PIF3 3 PIF2 2 PIF1...

Page 506: ...tions 1 If TMMK4 flag is read when a watchdog timer is used in the watchdog timer mode 1 the read value becomes undefined 2 Because port 0 has a dual function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 ...

Page 507: ...e setting RESET input sets these registers to FFH Figure 22 4 Priority Specify Flag Register Format Cautions 1 When a watchdog timer is used in the watchdog timer mode 1 set 1 in TMPR4 flag 2 Set always 1 in PR1L bit 5 to bit 7 7 PPR6 Symbol PR0L 6 PPR5 5 PPR4 4 PPR3 3 PPR2 2 PPR1 1 PPR0 0 TMPR4 Address FFE8H FFH After Reset R W R W 0 1 Priority Level Selection High priority level Low priority lev...

Page 508: ...0 1 ES20 0 0 1 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 0 1 0 1 ES30 4 External interrupt mode register INTM0 INTM1 These registers set the valid edge for INTP0 to INTP6 INTM0 and INTM1 are set by 8 bit memory manipulation instructions RESET input sets these registers to 00H Figure 22 5 External Interrupt Mode Register 0 Format Cau...

Page 509: ...ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 1 0 1 ES50 0 0 1 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 0 1 0 1 ES60 0 0 1 1 INTP6 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES71 0 1 0 1 ES70 F...

Page 510: ...eption is carried out using INTP0 digital noise is removed with sampling clocks SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS to 00H Figure 22 7 Sampling Clock Select Register Format Caution fXX 2N is a clock to be supplied to the CPU and fXX 25 fXX 26 and fXX 27 are clocks to be supplied to the peripheral hardware fXX 2N stops in the HALT mode Remarks 1 N Value N 0...

Page 511: ...e eliminator input output timing Figure 22 8 Noise Eliminator Input Output Timing during Rising Edge Detection a When input is less than the sampling cycle tSMP b When input is equal to or twice the sampling cycle tSMP c When input is twice or more than the cycle frequency tSMP tSMP Sampling Clock INTP0 PIF0 Because sampling INTP0 level is active twice in succession in 2 PIF0 flag is set to 1 1 2 ...

Page 512: ...maskable interrupt enable disable and the ISP flag to control multiple interrupt servicing are mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions EI and DI When a vectored interrupt request is acknowledged and when the BRK instruction is executed the contents of PSW automatically is saved into a stack and the I...

Page 513: ...terrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution ...

Page 514: ...ter unaccessed Interrupt service start Interrupt request held pending Reset processing Interval timer Start No Yes Yes No Yes No Yes No Yes No WDTM Watchdog timer mode register WDT Watchdog timer Figure 22 11 Non Maskable Interrupt Request Acknowledge Timing TMIF4 Watchdog timer interrupt request flag Instruction The interrupt request generated in this period is acknowledged at timing Instruction ...

Page 515: ...maskable interrupt servicing program execution NMI Request 2 NMI Request 1 1 Instruction Execution Main Routine NMI Request 1 Execute NMI Request 2 Reserve Reserved NMI Request 2 Processing NMI Request 3 NMI Request 2 NMI Request 1 1 Instruction Execution Main Routine NMI Request 1 Execute NMI Request 2 Reserve NMI Request 3 Reserve Reserved NMI Request 2 Processing NMI Request 3 Not Acknowledged ...

Page 516: ...quest is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are specified for the same priority with the priority specify flag the interrupt request with the hi...

Page 517: ...rity is being serviced Start xxIF 1 xxMK 0 xxPR 0 Any simultaneously generated high priority interrupt requests Any simultaneously generated xxPR 0 interrupt requests IE 1 ISP 1 Vectored interrupt servicing Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Vectored in...

Page 518: ...gram counter PC are saved to stacks in this order Then the IE flag is reset to 0 and the contents of the vector tables 003EH and 003FH are loaded into PC and branched Return from the software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt fCPU 1 Instruction Divide Instruction PSW and PC Save Jump to Interrupt Servic...

Page 519: ...acknowledged as a multiple interrupt Interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the completion of the interrupt being serviced During non maskable interrupt servicing multiple interrupts are not enabled Table 22 4 shows an interrupt request enable...

Page 520: ... interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because the interrupt priority is lower than that of INTxx and a multiple interrupt is not generated INTyy request is retained and acknowledged after execution of 1 instruction execution of the main processing PR 0 Higher priority level PR 1 Lower priority level IE 0 Interrupt request acknowledge disable Main P...

Page 521: ...x servicing an EI instruction is not issued interrupt request INTyy is not acknowledged and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after 1 instruction execution of the main processing PR 0 Higher priority level IE 0 Interrupt request acknowledge disable Main Processing INTxx Servicing INTyy Servicing INTxx PR 0 1 Instruction Execution IE 0 INTyy PR 0 I...

Page 522: ...NTM1 registers Caution BRK instruction is not an interrupt request reserve instruction described above However in a software interrupt started by the execution of BRK instruction the IE flag is cleared to 0 Therefore interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskable interrupt requests are acknow...

Page 523: ...nternal INTPT4 Negative edge detection at port 4 External Figure 22 18 Basic Configuration of Test Function IF Test input flag MK Test mask flag 22 5 1 Registers controlling the test function The test function is controlled by the following three registers Interrupt request flag register 1L IF1L Interrupt mask flag register 1L MK1L Key return mode register KRM The names of the test input flag and ...

Page 524: ...ime the standby mode is released by the clock timer It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to FFH by the RESET signal input Figure 22 20 Format of Interrupt Mask Flag Register 1L Caution Set bits 5 and 6 to 1 7 WTIF Symbol IF1L 6 0 5 0 4 TMIF6 3 TMIF5 2 ADIF 1 TMIF2 0 TMIF1 Address FFE2H 00H After Reset R W R W 0 1 Clock timer overf...

Page 525: ...terrupt mask flag WTMK a standby release signal is generated The watch function is available by checking the WTIF flag at a shorter cycle than the watch timer overflow cycle 2 External test signal When a falling edge is input to the port 4 P40 to P47 pins an external test input signal INTPT4 is generated by which the KRIF flag is set At this time if it is not masked with the interrupt mask flag KR...

Page 526: ...526 MEMO ...

Page 527: ...ernal Memory Expansion Mode Pin function at external device connection Alternate function Name Function AD0 to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Upper Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 23 2 State of Port 4 to Port 6 Pins in External Memory Expansion Mode Ports and bits Port 4 Por...

Page 528: ...his mode the address strobe signal is not required to be used though it is output from the ASTB P67 pin The output timings are shown in Figures 23 9 through 23 12 Table 23 4 State of Port 4 to Port 6 and Port 8 Pins in Separate Bus Mode Ports and bits Port 4 Port 8 Port 5 Port 6 Modes 0 to 7 0 to 7 0 1 2 3 4 5 6 7 0 to 3 4 to 7 Single chip mode Port Port Port Port Port 256 byte expansion mode Data...

Page 529: ...78P078 78P078Y when internal PROM capacity is 48 Kbytes FFFFH SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH F800H F7FFH F400H F3FFH D000H CFFFH C100H C0FFH C000H BFFFH 0000H Reserved Buffer RAM Reserved Internal Expansion RAM Full Address Mode when MM2 to MM0 111 or 16 Kbyte Expansion Mode when MM2 to MM0 101 4 Kbyte Expansion Mode when MM2 to MM0 100 256 byte Expansi...

Page 530: ...nal ROM size to less than 56 Kbytes by the internal memory size switching register IMS SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH F800H F7FFH F400H F3FFH F000H EFFFH E100H E0FFH E000H DFFFH 0000H Reserved Buffer RAM Reserved Internal Expansion RAM Full Address Mode when MM2 to MM0 111 or 16 Kbyte Expansion Mode when MM2 to MM0 101 4 Kbyte Expansion Mode when MM2 to...

Page 531: ...Kbyte address space except for the internal ROM RAM and SFR areas and the reserved area Remark P60 to P63 enter the port mode without regard to the mode single chip mode or memory expansion mode 7 0 Symbol MM 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H 10H After Reset R W R W MM2 MM1 MM0 Single chip Memory Expansion Mode Selection P40 to P47 P50 to P57 P64 to P67 P80 to P87 Pin state P40 t...

Page 532: ... bit memory manipulation instruction RESET input sets this register to the value indicated in Table 23 5 Figure 23 3 Internal Memory Size Switching Register Format Notes 1 The values after reset depend on the product See Table 23 5 Table 23 5 Values when the Internal Memory Size Switching Register is Reset Type Number Reset Value µPD78076 78076Y CCH µPD78078 78078Y CFH µPD78P078 78P078Y 2 When usi...

Page 533: ...s selected the P80 A0 through P87 A7 pins can be used as an I O port It is set by an 8 bit memory manipulation instruction RESET signal input sets EBTS to 00H Figure 23 4 External Bus Type Select Register Format 7 0 Symbol EBTS 6 0 5 0 4 0 3 0 2 0 1 0 0 EBTS0 Address FF3FH 00H After Reset R W R W 0 1 Sets operation mode of external device expansion function Multiplexed bus mode Separate bus mode E...

Page 534: ...signal is not output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses and instruction ...

Page 535: ...1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Internal Wait Signal 1 clock wait ASTB RD Lower Address Operation Code AD0 to AD7 A8 to A15 Higher Address WAIT ...

Page 536: ...PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Higher Address Internal Wait Signal 1 clock wait ASTB RD Lower Address Read Data AD0 to AD7 A8 to A15 Higher Address WAIT ...

Page 537: ...0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi Z Higher Address ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi Z Lower Address Write Data ...

Page 538: ...Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB RD WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Hi Z Read Data Lower Address Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB RD WR AD0 to AD7 A8 to A15 Write Data Read Data ASTB RD WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi Z Lower Address Write Data Read Data ...

Page 539: ...s not output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 AD0 to AD7 A0 to A7 A8 to A15 pins Alternate function P40 to P47 P80 to P87 P50 to P57 Address data signal output pin Valid signal is output or input...

Page 540: ...bus mode use of the address strobe signal is not required though it is output from the ASTB P67 pin ASTBNote RD AD0 to AD7 A0 to A7 A8 to A15 Lower Address Operation Code Higher Address Lower Address ASTBNote RD AD0 to AD7 A0 to A7 A8 to A15 Lower Address Operation Code Higher Address Lower Address Internal Wait Signal 1 clock wait ASTBNote RD Lower Address Operation Code Higher Address Lower Addr...

Page 541: ...e bus mode use of the address strobe signal is not required though it is output from the ASTB P67 pin ASTBNote RD AD0 to AD7 A0 to A7 A8 to A15 Lower Address Read Data Higher Address Lower Address ASTBNote RD AD0 to AD7 A0 to A7 A8 to A15 Lower Address Read Data Higher Address Lower Address Internal Wait Signal 1 clock wait ASTBNote RD Lower Address Read Data Higher Address Lower Address AD0 to AD...

Page 542: ...de use of the address strobe signal is not required though it is output from the ASTB P67 pin ASTBNote WR AD0 to AD7 A0 to A7 A8 to A15 Lower Address Write Data Higher Address Lower Address Hi Z ASTBNote WR AD0 to AD7 A0 to A7 A8 to A15 Lower Address Write Data Higher Address Lower Address Internal Wait Signal 1 clock wait Hi Z ASTBNote WR Higher Address Lower Address AD0 to AD7 A0 to A7 A8 to A15...

Page 543: ...address strobe signal is not required though it is output from the ASTB P67 pin ASTBNote RD WR AD0 to AD7 A0 to A7 A8 to A15 Lower Address Write Data Higher Address Lower Address Hi Z Read Data Lower Address Higher Address Lower Address Internal Wait Signal 1 clock wait Hi Z ASTBNote RD WR AD0 to AD7 A0 to A7 A8 to A15 Write Data Read Data ASTBNote RD WR Higher Address Lower Address AD0 to AD7 A0 ...

Page 544: ...544 MEMO ...

Page 545: ...ra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and...

Page 546: ...stration below whether the STOP mode is cleared by RESET input or by interrupt request generation Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode select register OSMS 4 Figures in parentheses apply to operation with fX 5 0 MHz STOP Mode Clear X1 Pin Voltage Waveform VSS a Address FFFAH 04H After Reset R W R W 0 0 0 0...

Page 547: ... bit timer event counter 1 and 2 Operable Operable when TI1 or TI2 is selected as count clock 8 bit timer event counter 5 and 6 Operable Operable when TI5 or TI6 is selected as count clock Watch timer Operable when Operable Operable when fXT is selected fXX 27 is selected as count clock as count clock Watchdog timer Operable Operation stops A D converter Operable Operation stops D A converter Oper...

Page 548: ... released the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Release by non maskable interrupt request The HALT mode is released and vectored interrupt service is carried out if non maskable interrupt request is generated whether interrupt request acknowled...

Page 549: ... Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 5 0 MHz Table 24 2 Operation after HALT Mode Release Release Source MKxx PRxx IE ISP Operation Maskable interrupt 0 0 0 x Next address instruction execution request 0 0 1 x Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 x 0 0 1 1 1 Interrupt service execution 1 x x ...

Page 550: ...or Only main system clock stops oscillation CPU Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter Operable when watch timer output is used Operation stops as count clock fXT is selected as count clock for watch timer 8 bit timer event counters 1 and 2 Operable when TI1 or TI2 is selected for the count clock 8 bit timer event counters 5 and 6 Opera...

Page 551: ...mode If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt request acknowledge is disabled the next address instruction is executed Figure 24 4 STOP Mode Released by Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby status is a...

Page 552: ... STOP Mode Released by RESET Input Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 5 0 MHz Table 24 4 Operation after STOP Mode Release Release Source MKxx PRxx IE ISP Operation Maskable interrupt request 0 0 0 x Next address instruction execution 0 0 1 x Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 x 0 0 1 1 1 ...

Page 553: ... clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217 fX see Figures 25 2 to 25 4 Cautions 1 For an external reset input a low ...

Page 554: ...n Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing X1 Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing Hi z RESET Internal Reset Signal Port Pin Delay Delay Hi z X1 Normal Operation Normal Operation Reset Processing STOP Instruction Execution Reset Pe...

Page 555: ...EBTS 00H Memory expansion mode register MM 10H Oscillation stabilization time select register OSTS 04H Timer register TM0 00H Capture compare register CR00 CR01 Undefined Clock selection register TCL0 00H Mode control register TMC0 00H Capture compare control register 0 CRC0 04H Output control register TOC0 00H Timer register TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register ...

Page 556: ...receive control 00H register ADTC Automatic data transmit receive address 00H pointer ADTP Automatic data transmit receive interval 00H specify register ADTI Asynchronous serial interface mode 00H register ASIM Asynchronous serial interface status 00H register ASIS Baud rate generator control register BRGC 00H Transmit shift register TXS FFH Receive buffer register RXB Interrupt timing specify reg...

Page 557: ...re Status after Reset Interrupt Request flag register IF0L IF0H IF1L 00H Mask flag register MK0L MK0H MK1L FFH Priority specify flag register FFH PR0L PR0H PR1L External interrupt mode register 00H INTM0 INTM1 Key return mode register KRM 02H Sampling clock select register SCS 00H ...

Page 558: ...558 MEMO ...

Page 559: ... by the in circuit emulator IE 78000 R IE 78000 R A IE 78001 R A IE 78K0 NS 26 2 ROM Correction Configuration The ROM correction is executed by the following hardware Table 26 1 ROM Correction Configuration Item Configuration Register Correction address registers 0 and 1 CORAD0 CORAD1 Control register Correction control register CORCN Figure 26 1 shows a block diagram of the ROM correction Figure ...

Page 560: ...1 of the correction control register CORCN see Figure 26 3 are 0 2 Only addresses where operation codes are stored can be set in CORAD0 and CORAD1 3 Do not set the following addresses to CORAD0 and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H to 007FH Address value in vector table area 0000H to 003FH 2 Comparator The comparator always compares the corre...

Page 561: ...n Control Registers The ROM correction is controlled with the correction control register CORCN 1 Correction control register CORCN This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1 The correction control register consists of correction enable flags COREN0 COREN1 ...

Page 562: ... instruction after correction patch program to nonvolatile memory such as EEPROMTM outside the microcontroller When two places should be corrected store the branch destination judgment program as well The branch destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the correction branch Figure 26 4 Storing Example to EEPROM when One Place is Corrected Fig...

Page 563: ...ernal expansion RAM with the main program 5 After the main program is started the fetch address value and the values set in CORAD0 and CORAD1 are always compared by the comparator in the ROM correction circuit When these values match the correction branch request signal is generated Simultaneously the corresponding correction status flag CORST0 or CORST1 is set to 1 6 Branch to the address F7FDH b...

Page 564: ...ure 26 7 ROM Correction Operation No Yes Start of internal ROM program Does fetch address match with correction address Set correction status flag Correction branch branch to address F7FDH Execution of correction program ROM correction ...

Page 565: ...ction address register matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR addr16 to address F7FDH with the main program 3 Returns to the internal ROM program after executing the substitute instruction ADD A 2 ADD A 2 BR 1002H BR F702H ADD A 1 MOV B A 0000H 0080H Program start 10...

Page 566: ...agram when One Place is Corrected 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address Correction place Internal ROM Internal ROM JUMP FFFFH F7FFH F7FDH xxxxH 0000H 1 2 3 BR JUMP Correction program ...

Page 567: ...anches to address F7FDH when fetch address matches correction address 6 Branches to branch destination judgment program 7 Branches to correction program 2 by branch destination judgment program BTCLR CORST1 yyyyH 8 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address Internal ROM Correction place 1 Internal ROM JUMP Int...

Page 568: ...set address value 3 Do not set the address value of instruction immediately after the instruction that sets the correction enable flag COREN0 COREN1 to 1 to correction address register 0 or 1 CORAD0 CORAD1 the correction branch may not start 4 Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector table area 0000H ...

Page 569: ...the internal memory size switching register IMS Changing internal expansion RAM capacity by the YesNote 2 No internal expansion RAM size switching register IXS IC pin None Available VPP pin Available None P60 to P63 pins pull up resistor internal mask option None Available Electrical specifications Refer to the data sheet of individual product Notes 1 Internal PROM capacity becomes 60 Kbytes and i...

Page 570: ...a mask ROM version with a different size internal ROM is possible IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to CFH Figure 27 1 Internal Memory Size Switching Register Format Note When using the external device extension function on the following devices the internal ROM capacity must be 56 Kbytes or less µPD78078 78078Y 78P078 78P078Y Caution When using the mask...

Page 571: ...the same memory mapping as that of a mask ROM version with a different internal extension RAM is possible The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to 0AH Caution When the µPD78076 78078 78076Y or 78078Y is used be sure to set the value specified in Table 27 3 to IXS Other settings are prohibited Figure 27 2 Internal Extension RAM Size Switching Registe...

Page 572: ...device is set to the PROM programming mode This is one of the operating modes shown in Table 27 4 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 27 4 PROM Programming Operating Modes Pin Operating mode Page data latch H L H Data input Page write H H L High impedance Byte write L H L Data input Program verify L L H Data output L...

Page 573: ...write and verify operations are executed X times X 10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X 10 7 Program verify mode Setting CE to L ...

Page 574: ...h Address Address 1 Latch X X 1 0 1 ms program pulse Verify 4 bytes Pass Address N No Pass VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Address Address 1 No Yes X 10 Fail Fail Yes All Pass Defective product G Start address N Last address of program 27 3 2 PROM write procedure Figure 27 3 Page Program Mode Flowchart ...

Page 575: ...7 µPD78P078 78P078Y Page Data Latch Page Program Program Verify Data Input Data Output Hi Z A2 to A16 A0 A1 D0 to D7 VPP VDD VPP VDD 1 5 VDD VPP VIH CE PGM OE VIL VIH VIL VIH VIL Figure 27 4 Page Program Mode Timing ...

Page 576: ... X 0 X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X 10 Address Address 1 G Start address N Last address of program Figure 27 5 Byte Program Mode Flowchart ...

Page 577: ...L VIH VIL VPP VDD CE PGM OE Figure 27 6 Byte Program Mode Timing Cautions 1 Apply VDD before applying VPP and remove it after removing VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to VPP may have an adverse affect on reliability ...

Page 578: ...n Unused pins are handled as shown in 1 5 2 PROM programming mode and 2 5 Pin Configuration Top View 2 Supply 5 V to the VDD and VPP pins 3 Input address of data to be read to pins A0 through A16 4 Read mode 5 Output data to pins D0 through D7 The timing for steps 2 through 5 above is shown in Figure 27 7 Figure 27 7 PROM Read Timing Address Input A0 to A16 CE Input OE Input D0 to D7 Hi Z Hi Z Dat...

Page 579: ...To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from malfunction due to light coming in through the erasure window mask the window with the attached opaque film after writing the EPROM 27 6 Screening of One Time PROM Versions One time PROM versions cannot be fully tested by NEC before shipment due to the structure of one time PROM Therefore after us...

Page 580: ...580 MEMO ...

Page 581: ...N SET This chapter describes each instruction set of the µPD78078 and 78078Y Subseries as list table For details of its operation and operation code refer to the separate document 78K 0 Series USER S MANUAL Instructions U12326E ...

Page 582: ...names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 28 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable register even addresses onl...

Page 583: ...y flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses xH xL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data...

Page 584: ...A HL C HL C A 1 6 7 m HL C A XCH A rNote 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n m A HL B A HL C 2 8 10 n m A HL C Notes 1 For instructions that access the internal high speed RAM area or perform no data access 2 For instructions that access an area other than the internal hi...

Page 585: ...C A byte 2 4 A CY A byte CY x x x saddr byte 3 6 8 saddr CY saddr byte CY x x x A rNote 4 2 4 A CY A r CY x x x r A 2 4 r CY r A CY x x x A saddr 2 4 5 A CY A saddr CY x x x A addr16 3 8 9 n A CY A addr16 CY x x x A HL 1 4 5 n A CY A HL CY x x x A HL byte 2 8 9 n A CY A HL byte CY x x x A HL B 2 8 9 n A CY A HL B CY x x x A HL C 2 8 9 n A CY A HL C CY x x x Notes 1 For instructions that access the...

Page 586: ...L CY x x x A HL byte 2 8 9 n A CY A HL byte CY x x x A HL B 2 8 9 n A CY A HL B CY x x x A HL C 2 8 9 n A CY A HL C CY x x x AND A byte 2 4 A A byte x saddr byte 3 6 8 saddr saddr byte x A rNote 3 2 4 A A r x r A 2 4 r r A x A saddr 2 4 5 n A A saddr x A addr16 3 8 9 n A A addr16 x A HL 1 4 5 n A A HL x A HL byte 2 8 9 n A A HL byte x A HL B 2 8 9 n A A HL B x A HL C 2 8 9 n A A HL C x Notes 1 For...

Page 587: ...L B x A HL C 2 8 9 n A A HL C x CMP A byte 2 4 A byte x x x saddr byte 3 6 8 saddr byte x x x A rNote 3 2 4 A r x x x r A 2 4 r A x x x A saddr 2 4 5 n A saddr x x x A addr16 3 8 9 n A addr16 x x x A HL 1 4 5 n A HL x x x A HL byte 2 8 9 n A HL byte x x x A HL B 2 8 9 n A HL B x x x A HL C 2 8 9 n A HL C x x x Notes 1 For instructions that access the internal high speed RAM area or perform no data...

Page 588: ...t Accumulator after Addition x x x adjust ADJBS 2 4 Decimal Adjust Accumulator after Subtract x x x Bit mani MOV1 CY saddr bit 3 6 7 CY saddr bit x pulation CY sfr bit 3 7 CY sfr bit x CY A bit 2 4 CY A bit x CY PSW bit 3 7 CY PSW bit x CY HL bit 2 6 7 n CY HL bit x saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY x x HL bit CY 2 6 8 n m HL ...

Page 589: ...it 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 x x x HL bit 2 6 8 n m HL bit 1 CLR1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 x x x HL bit 2 6 8 n m HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x Notes 1 For instructions that access the internal high speed RAM area or perform no data access 2 For instructions that access...

Page 590: ... 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP AX AX SP 2 8 AX SP Uncondi BR addr16 3 6 PC addr16 tional addr16 2 6 PC PC 2 jdisp8 branch AX 2 8 PCH A PCL X Conditional BC addr16 2 6 PC PC 2 jdisp8 if CY 1 branch BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ addr16 2 6 PC PC 2 jdisp...

Page 591: ...addr16 4 12 n m PC PC 4 jdisp8 if PSW bit 1 x x x then reset PSW bit HL bit addr16 3 10 12 PC PC 3 jdisp8 if HL bit 1 then reset HL bit DBNZ B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 3 8 10 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 CPU SEL RBn 2 4 RBS1 0 n control NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable...

Page 592: ...592 CHAPTER 28 INSTRUCTION SET 28 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 593: ... ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B HL C X MULU...

Page 594: ...OVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV...

Page 595: ... CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 596: ...596 MEMO ...

Page 597: ...ions LED direct drive output 16 Not provided 4 AVDD pin Provided Not provided Provided AVREF0 pin functions alternately External Bus mode Selectable from multiplexed bus mode or separate Only separate bus mode expansion bus mode function Memory expansion mode Selectable from four types of memory expansion modes Only full address mode ROM correction function Provided Not provided Package 100 pin pl...

Page 598: ...598 MEMO ...

Page 599: ...PPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD78078 and 78078Y Subseries Figure B 1 shows the configuration example of the tools ...

Page 600: ...compiler package C library source file Device file Debugging tool System simulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC Interface adapter PC card interface etc PROM programming environment PROM programmer Programmer adapter PROM contained version In circuit emulator Emulation board Emulation probe Power supply unit Conversion socket or conversion adapte...

Page 601: ...mulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC or EWS Interface board PROM programming environment PROM programmer Programmer adapter PROM contained version In circuit emulator Emulation board Emulation probe Conversion socket or conversion adapter Target system I O board Probe board Emulation probe conversion board Interface adapter Remark The parts show...

Page 602: ...ely available Assembler Package and Device File Precautions for the use in PC environment Although C Compiler Package is a DOS based application it can be used in Windows environment through the use of Project Manager included in Assembler Package on Windows Part number µSxxxxCC78K0 DF78078Note A file which contains information peculiar to the device Device File Used in combination with separately...

Page 603: ...Media AA13 PC 9800 series Japanese WindowsNotes 1 2 3 5 inch 2HD FD AB13 IBM PC AT and Japanese WindowsNotes 1 2 3 5 inch 2HC FD BB13 compatibles English WindowsNotes 1 2 3P16 HP9000 series 700 HP UX rel 9 05 DAT DDS 3K13 SPARCstation SunOS rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS rel 6 1 3 5 inch 2HC FD Notes 1 Operates also in DOS environment 2 Does not support Windows...

Page 604: ...P078GC 100 pin plastic QFP GC 7EA GC 8EU type PA 78P078GF 100 pin plastic QFP GF 3BA type PA 78P078KL T 100 pin ceramic WQFN KL T type B 2 2 Software PG 1500 Controller Connects PG 1500 and the host machine with serial and parallel interface and controls the PG 1500 on the host machine The PG 1500 controller is a DOS based application Use it with the DOS prompt on Windows Part number µSxxxxPG1500 ...

Page 605: ... GC 8EU type and the NP 100GC The µPD78P078KL T and 78P078YKL T ceramic WQFN can be mounted instead of connecting NP 100GC A probe to connect an in circuit emulator and the target system For 100 pin plastic QFP GF 3BA type A conversion socket to connect the board of a target system designed to mount 100 pin plastic QFP GF 3BA type to the NP 100GF B 3 Debugging Tools B 3 1 Hardware 1 2 1 When using...

Page 606: ...o the board in the IE 78001 R A Supports 10Base 5 for EthernetTM A separately available adapter required for other systems A board to emulate peripheral hardware peculiar to the device Used in combination with an in circuit emulator and emulation probe conversion board A board required for using the IE 78078 NS EM1 with the IE 78001 R A A board to emulate peripheral hardware peculiar to the device...

Page 607: ...ly from hardware development without using in circuit emulator and improves the development efficiency and the software quality Used in combination with separately available Device File DF78078 Part number µSxxxxSM78K0 Remark xxxx in the part number differs depending on the host machine and OS used µSxxxx SM78K0 xxxx Host Machine OS Supply Media AA13 PC 9800 series Japanese WindowsNotes 1 2 3 5 in...

Page 608: ...ote 3P16 HP9000 series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Does not support WindowsNT A control program to debug the 78K 0 Series Adopting Windows on personal computers and OSF Motif on EWS as graphical user interface presents the appearance and the operability conforming to them Enhanci...

Page 609: ...rmer type In circuit Emulator for 78K 0 Series to IE 78001 R A If the user already owns a former type in circuit emulator for the 78K 0 Series IE 78000 R or IE 78000 R A it can be used in the same manner as the IE 78001 R A by replacing the break board inside the main unit with the IE 78001 R BK under development Table B 2 System Upgrading from Former type In circuit Emulator for 78K 0 Series to I...

Page 610: ... 0 618 E 15 0 0 591 F 21 55 G 3 55 0 140 0 848 K 18 1 0 713 L 13 75 0 541 M 0 5x24 12 0 0 020x0 945 0 472 Q 10 0 0 394 R 11 3 0 445 S 18 1 0 713 N 1 125 0 3 0 044 0 012 O 1 125 0 2 P 7 5 0 295 0 044 0 008 W 1 8 0 071 X C 2 0 C 0 079 Y 0 9 0 035 T 5 0 0 197 U 5 0 V 4 1 3 4 0 051 0 197 Z 0 3 0 012 φ φ φ φ φ φ φ φ φ φ φ φ TGC 100SDW TQPACK100SD TQSOCKET100SDW Package dimension unit mm H A B C I J K G...

Page 611: ...C D E F G H I J K L M N O P Q R S 24 6 21 15 18 6 4 C 2 0 8 12 0 22 6 25 3 6 0 16 6 19 3 8 2 8 0 2 5 2 0 0 35 2 3 1 5 0 969 0 827 0 591 0 732 4 C 0 079 0 031 0 472 0 89 0 996 0 236 0 654 076 0 323 0 315 0 098 0 079 0 014 0 091 0 059 φ φ φ φ Socket Drawing and Recommended Footprints EV 9200GF 100 Figure B 3 EV 9200GF 100 Drawing For Reference Only ...

Page 612: ...02 x 29 18 85 0 05 0 65 0 02 x 19 12 35 0 05 φ 0 001 0 002 0 002 0 002 0 001 0 002 0 003 0 002 0 003 0 002 0 003 0 002 0 001 0 001 0 001 0 002 φ 0 001 0 002 φ φ G φ φ Based on EV 9200GF 100 2 Pad drawing in mm Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECH...

Page 613: ...e application form in advance and sign the License Agreement Remark xxxx and in the part number differs depending on the host machine and OS used µSxxxxRX78013 Product Outline Max No for Use in Mass Production 001 Evaluation object Do not use for mass production 100K Mass production object 100 000 001M 1 000 000 010M 10 000 000 S01 Source program Source program for mass production object xxxx Host...

Page 614: ...g on the host machine and OS used µSxxxxMX78K0 Product outline Max No for Use in Mass Production 001 Evaluation object Use for preproduction xx Mass production object Use for mass production S01 Source program Can be purchased only when purchasing mass produced object xxxx Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Notes1 2 3 5 inch 2HD FD AB13 IBM PC AT and Japanese Windows...

Page 615: ... ADTI 421 Automatic data transmit receive control register ADTC 420 B Baud rate generator control register BRGC 465 C Capture compare control register 0 CRC0 193 Capture compare register 00 CR00 188 Capture compare register 01 CR01 188 Compare register 10 CR10 230 Compare register 20 CR20 230 Compare register 50 CR50 253 Compare register 60 CR60 253 Correction address register 0 CORAD0 560 Correct...

Page 616: ...errupt mode register 1 INTM1 299 508 I Internal extension RAM size switching register IXS 571 Internal memory size switching register IMS 532 570 Interrupt mask flag register 0H MK0H 506 Interrupt mask flag register 0L MK0L 506 Interrupt mask flag register 1L MK1L 506 524 Interrupt request flag register 0H IF0H 505 Interrupt request flag register 0L IF0L 505 Interrupt request flag register 1L IF1L...

Page 617: ... register 8 PM8 157 Port mode register 9 PM9 157 Port mode register 10 PM10 157 258 Port mode register 12 PM12 157 497 Port mode register 13 PM13 157 Priority specify flag register 0H PR0H 507 Priority specify flag register 0L PR0L 507 Priority specify flag register 1L PR1L 507 Processor clock control register PCC 167 Pull up resistor option register H PUOH 160 Pull up resistor option register L P...

Page 618: ...ister TMC0 192 16 bit timer output control register TOC0 194 16 bit timer register TM0 189 16 bit timer register TMS 230 Slave address register SVA 319 370 Successive approximation register SAR 295 T Timer clock select register 0 TCL0 190 285 Timer clock select register 1 TCL1 231 Timer clock select register 2 TCL2 271 278 290 Timer clock select register 3 TCL3 321 373 418 Timer clock select regis...

Page 619: ...0 CORAD1 Correction address register 1 560 CORCN Correction control register 561 CR00 Capture compare register 00 188 CR01 Capture compare register 01 188 CR10 Compare register 10 230 CR20 Compare register 20 230 CR50 Compare register 50 253 CR60 Compare register 60 253 CRC0 Capture compare control register 0 193 CSIM0 Serial operating mode register 0 323 374 CSIM1 Serial operating mode register 1...

Page 620: ...egister 161 531 O OSMS Oscillation mode selection register 170 OSTS Oscillation stabilization time select register 546 P P0 Port 0 136 P1 Port 1 138 P2 Port 2 139 141 P3 Port 3 143 P4 Port 4 144 P5 Port 5 145 P6 Port 6 146 P7 Port 7 148 P8 Port 8 150 P9 Port 9 151 P10 Port 10 153 P12 Port 12 155 P13 Port 13 156 PCC Processor clock control register 167 PM0 Port mode register 0 157 PM1 Port mode reg...

Page 621: ...SBIC Serial bus interface control register 325 376 SCS Sampling clock select register 197 510 SINT Interrupt timing specify register 327 378 SIO0 Serial I O shift register 0 319 370 SIO1 Serial I O shift register 1 417 SVA Slave address register 319 370 T TCL0 Timer clock select register 0 190 285 TCL1 Timer clock select register 1 231 TCL2 Timer clock select register 2 271 278 290 TCL3 Timer cloc...

Page 622: ...6 8 bit timer mode control register 6 257 TMS 16 bit timer register 230 TOC0 16 bit timer output control register 194 TOC1 8 bit timer output control register 234 TXS Transmit shift register 460 W WDTM Watchdog timer mode register 280 ...

Page 623: ... corrected The count clocks of 8 bit timer event counters 5 and 6 have been corrected A D converter mode register format has been modified 15 5 7 AVDD pin has been modified and Figure 15 12 Handling of AVDD Pin has been added Serial operating mode register 0 format has been modified Figure 17 34 SCK0 P27 Pin Configuration has been corrected The baud rate transmit receive clock range that can be ge...

Page 624: ...ure 12 3 Watchdog Timer Mode Register Format has been changed and caution has been added Caution has been added to Serial I O shift register 0 SIO0 of µPD78078Y subseries Figure 18 22 Example of Communication from Master to Slave with 9 clock wait selected for both master and slave has been corrected Figure 18 23 Example of Communication from Slave to Master with 9 clock wait selected for both mas...

Page 625: ...the serial interface channel 0 in SBI mode have been changed Cautions for the case that bus release signal REL and command signal CMD are misrecognized due to the bus line changing timing has been added Conditions and timings for the generation of interrupt request INTSR INTSER when a reception error is generated have been corrected Precautions for using UART mode have been added Precautions for r...

Page 626: ...626 MEMO ...

Page 627: ...erica NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Corporation Semiconductor Solution Engineering Division Technical Information Sup...

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