NEC mPD789101 User Manual Download Page 99

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CHAPTER 7 CLOCK GENERATOR (

PD789124, 789134 SUBSERIES)

User’s Manual U13045EJ2V0UM00

Figure 7-4. Examples of Incorrect Resonator Connection (2/2)

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of

oscillator (potential at points A and B

fluctuates)

(e) Signal is fetched

CL2

CL1

High current

CL2

CL1

PORTn
(n = 0 to 2, 5, 6)

High current

CL2

CL1

Summary of Contents for mPD789101

Page 1: ...ontrollers PD789101 PD789121 PD789102 PD789122 PD789104 PD789124 PD789111 PD789131 PD789112 PD789132 PD789114 PD789134 PD78F9116 PD78F9136 Document No U13045EJ2V0UM00 2nd edition Date Published July 1...

Page 2: ...2 User s Manual U13045EJ2V0UM00 MEMO...

Page 3: ...al All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar...

Page 4: ...s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these...

Page 5: ...sseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66...

Page 6: ...upt p 117 Addition of caution regarding rewrite of CR80 in section 9 2 1 8 bit compare register 80 CR80 p 120 Addition of explanation regarding settings in section 9 4 1 Operation as interval timer p...

Page 7: ...zation The PD789104 789114 789124 789134 Subseries User s Manual is divided into two parts this manual and instructions common to the 78K 0S Series PD789104 789114 789124 78K 0S Series 789134 Subserie...

Page 8: ...mation U13015E U13015J PD78F9116 Preliminary Product Information U13037E U13037J PD78F9136 Preliminary Product Information U13036E U13036J PD789104 789114 789124 789134 Subseries User s Manual This ma...

Page 9: ...Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J...

Page 10: ...10 User s Manual U13045EJ2V0UM00 MEMO...

Page 11: ...of Pin Functions 41 3 2 1 P00 to P03 Port 0 41 3 2 2 P10 P11 Port 1 41 3 2 3 P20 to P25 Port 2 41 3 2 4 P50 to P53 Port 5 42 3 2 5 P60 to P63 Port 6 42 3 2 6 RESET 42 3 2 7 X1 X2 PD789104 789114 Subs...

Page 12: ...2 1 Port 0 75 5 2 2 Port 1 76 5 2 3 Port 2 77 5 2 4 Port 5 81 5 2 5 Port 6 82 5 3 Port Function Control Registers 83 5 4 Operation of Port Functions 85 5 4 1 Writing to I O port 85 5 4 2 Reading from...

Page 13: ...Counter Control Registers 118 9 4 Operation of 8 Bit Timer Event Counter 120 9 4 1 Operation as interval timer 120 9 4 2 Operation as external event counter 122 9 4 3 Operation as square wave output 1...

Page 14: ...6 13 4 3 3 wire serial I O mode 189 CHAPTER 14 MULTIPLIER 199 14 1 Multiplier Function 199 14 2 Multiplier Configuration 199 14 3 Multiplier Control Register 201 14 4 Multiplier Operation 202 CHAPTER...

Page 15: ...d description methods 241 20 1 2 Description of operation column 242 20 1 3 Description of flag operation column 242 20 2 Operation List 243 20 3 Instructions Listed by Addressing Type 248 APPENDIX A...

Page 16: ...User s Manual U13045EJ2V0UM00 16 MEMO...

Page 17: ...tack Memory 58 4 14 General Register Configuration 59 5 1 Port Types 73 5 2 Block Diagram of P00 to P03 75 5 3 Block Diagram of P10 and P11 76 5 4 Block Diagram of P20 77 5 5 Block Diagram of P21 78 5...

Page 18: ...26 9 8 Start Timing of 8 Bit Timer Register 127 9 9 External Event Counter Operation Timing 127 10 1 Block Diagram of Watchdog Timer 130 10 2 Timer Clock Select Register 2 Format 131 10 3 Format of Wa...

Page 19: ...nterrupt Timing 186 13 10 Receive Error Timing 187 13 11 3 Wire Serial I O Mode Timing 192 14 1 Block Diagram of Multiplier 200 14 2 Multiplier Control Register 0 Format 201 14 3 Multiplier Operation...

Page 20: ...Mode 228 18 1 Communication Mode Selection Format 232 18 2 Flashpro III Connection in 3 Wire Serial I O Mode 233 18 3 Flashpro III Connection in UART Mode 234 18 4 Flashpro III Connection in Pseudo 3...

Page 21: ...Timer Event Counter 80 115 9 2 Square Wave Output Range of 8 Bit Timer Event Counter 80 115 9 3 8 Bit Timer Event Counter 80 Configuration 116 9 4 Interval Time of 8 Bit Timer Event Counter 80 At fX...

Page 22: ...lags Corresponding to Interrupt Request Signal 206 15 3 Time from Generation of Maskable Interrupt Request to Processing 213 16 1 HALT Mode Operating Status 221 16 2 Operation after Release of HALT Mo...

Page 23: ...le high speed 0 4 s and low speed 1 6 s system clock 5 0 MHz 20 I O ports Serial interface 1 channel 3 wire serial I O mode UART mode selectable 8 bit resolution A D converter 4 channels PD789104 Subs...

Page 24: ...1 2 mm Mask ROM PD789111GS 30 pin plastic shrink SOP 300 mil resin thickness 1 7 mm Mask ROM PD789111MC 5A4 30 pin plastic shrink SOP 300 mil resin thickness 1 2 mm Mask ROM PD789112GS 30 pin plastic...

Page 25: ...esides the above products a 30 pin plastic shrink DIP part number undefined is in planning Cautions 1 Connect the IC0 internally connected pin directly to the VSS pin 2 Connect the AVDD pin to the VDD...

Page 26: ...nput IC0 Internally Connected INTP0 to INTP2 Interrupt from Peripherals P00 to P03 Port 0 P10 P11 Port 1 P20 to P25 Port 2 P50 to P53 Port 5 P60 to P63 Port 6 RESET Reset RxD20 Receive Data SCK20 Seri...

Page 27: ...A D converter PD789104A with enhanced timer PD789124A with enhanced A D converter RC oscillation version of the PD789104A PD789104A with enhanced A D converter PD789026 with A D converter and multipl...

Page 28: ...n package SMB 1 ch version general on chip purpose EEPROM application PD789197AY On chip A D EEPROM converter PD789177 1 ch UART 1 ch PD789167 8 ch PD789156 8 K to 16 K 1 ch 4 ch 20 On chip PD789146 4...

Page 29: ...PP TI80 INTP2 P25 8 bit TIMER EVENT COUNTER 80 TO80 TO20 INTP1 P24 P00 to P03 PORT0 P10 P11 PORT1 P20 to P25 PORT2 P50 to P53 PORT5 P60 to P63 PORT6 SYSTEM CONTROL TO20 TO80 INTP1 P24 CPT20 INTP0 SS20...

Page 30: ...iplier 8 bits 8 bits 16 bits I O ports Total 20 CMOS input 4 CMOS I O 12 N ch open drain 12 V withstand voltage 4 A D converter 8 bit resolution 4 channels PD789104 Subseries 10 bit resolution 4 chann...

Page 31: ...h speed 0 5 s and low speed 2 0 s system clock 4 0 MHz 20 I O ports Serial interface 1 channel 3 wire serial I O mode UART mode selectable 8 bit resolution A D converter 4 channels PD789124 Subseries...

Page 32: ...M PD789131GS 30 pin plastic shrink SOP 300 mil resin thickness 1 7 mm Mask ROM PD789131MC 5A4 30 pin plastic shrink SOP 300 mil resin thickness 1 2 mm Mask ROM PD789132GS 30 pin plastic shrink SOP 300...

Page 33: ...e above products a 30 pin plastic shrink DIP part number undefined is in planning Note Under development Cautions 1 Connect the IC0 internally connected pin directly to the VSS pin 2 Connect the AVDD...

Page 34: ...20 Capture Trigger Input IC0 Internally Connected INTP0 to INTP2 Interrupt from Peripherals P00 to P03 Port 0 P10 P11 Port 1 P20 to P25 Port 2 P50 to P53 Port 5 P60 to P63 Port 6 RESET Reset RxD20 Rec...

Page 35: ...A D converter PD789104A with enhanced timer PD789124A with enhanced A D converter RC oscillation version of the PD789104A PD789104A with enhanced A D converter PD789026 with A D converter and multipl...

Page 36: ...n package SMB 1 ch version general on chip purpose EEPROM appliction PD789197AY On chip A D EEPROM converter PD789177 1 ch UART 1 ch PD789167 8 ch PD789156 8 K to 16 K 1 ch 4 ch 20 On chip PD789146 4...

Page 37: ...8 bit TIMER EVENT COUNTER 80 TO80 TO20 INTP1 P24 P00 to P03 PORT0 P10 P11 PORT1 P20 to P25 PORT2 P50 to P53 PORT5 P60 to P63 PORT6 SYSTEM CONTROL TO20 TO80 INTP1 P24 CPT20 INTP0 SS20 P23 WATCHDOG TIM...

Page 38: ...er 8 bits 8 bits 16 bits I O ports Total 20 CMOS input 4 CMOS I O 12 N ch open drain 12 V withstand voltage 4 A D converter 8 bit resolution 4 channels PD789124 Subseries 10 bit resolution 4 channels...

Page 39: ...used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register 0 PU0 P20 Input output Port 2 Input SCK20 ASCK20 P21 6 bit input output port SO20 TxD20...

Page 40: ...P22 SI20 TxD20 Output Serial data output from asynchronous serial interface Input P21 SO20 TI80 Input External count clock input to 8 bit timer TM80 Input P25 INTP2 TO80 Output 8 bit timer TM80 outpu...

Page 41: ...ion modes in 1 bit units 1 Port mode In this mode P20 to P25 function as a 6 bit I O port Port 2 can be specified as input or output mode in 1 bit units by using port mode register 2 PM2 Use of an on...

Page 42: ...l purpose input ports these pins function as the A D converter input pins 1 Port mode In the port mode port 6 functions as a 4 bit input only port 2 Control mode In the control mode the pins of port 6...

Page 43: ...to set the PD789134 in the test mode before shipment In the normal operation mode connect this pin directly to the VSS pin with as short a wiring length as possible If a potential difference is gener...

Page 44: ...Pin Name Input Output Circuit Type Input Output Recommended Connection of Unused Pins P00 to P03 5 A Input output Input Independently connect these pins to VDD or P10 P11 VSS via a resistor P20 SCK20...

Page 45: ...able VDD P ch VDD P ch IN OUT N ch Type 13 V VSS VSS Type 8 A Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch VSS Type 9 C IN Comparator VREF Threshold voltage AVSS P ch N ch Input en...

Page 46: ...User s Manual U13045EJ2V0UM00 46 MEMO...

Page 47: ...memory maps Figure 4 1 Memory Map PD789101 789111 789121 789131 FFFFH FF00H FEFFH FE00H FDFFH 0800H 07FFH 0000H 07FFH 0000H 0080H 007FH 0040H 003FH 0016H 0015H Data memory space Program memory space...

Page 48: ...132 FFFFH FF00H FEFFH FE00H FDFFH 1000H 0FFFH 0000H 0FFFH 0000H 0080H 007FH 0040H 003FH 0016H 0015H Data memory space Program memory space Special function registers 256 8 bits Internal high speed RAM...

Page 49: ...134 FFFFH FF00H FEFFH FE00H FDFFH 2000H 1FFFH 0000H 1FFFH 0000H 0080H 007FH 0040H 003FH 0016H 0015H Data memory space Program memory space Special function registers 256 8 bits Internal high speed RAM...

Page 50: ...FFH FF00H FEFFH FE00H FDFFH 4000H 3FFFH 0000H 3FFFH 0000H 0080H 007FH 0040H 003FH 0016H 0015H Data memory space Program memory space Special function registers 256 8 bits Internal high speed RAM 256 8...

Page 51: ...areas are allocated to the internal program memory space 1 Vector table area A 22 byte area of addresses 0000H to 0015H is reserved as a vector table area This area stores program start addresses to...

Page 52: ...ty of addressing modes which take account of memory manipulability etc Especially at addresses corresponding to data memory area FE00H to FEFFH particular addressing modes are possible to meet the fun...

Page 53: ...112 789122 789132 FFFFH 1000H 0FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH FE00H FDFFH Special function registers SFRs 256 8 bits Internal high speed RAM 256 8 bits Reserved Internal ROM 4 096 8 bi...

Page 54: ...114 789124 789134 FFFFH 2000H 1FFFH 0000H FE00H FDFFH FF00H FEFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits Internal high speed RAM 256 8 bits Reserved Internal ROM 8 192 8 bi...

Page 55: ...116 78F9136 FFFFH 4000H 3FFFH 0000H FE00H FDFFH FF00H FEFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits Internal high speed RAM 256 8 bits Reserved Flash memory 16 384 8 bits SF...

Page 56: ...tes of the instruction to be fetched When a branch instruction is executed immediate data or register contents is set RESET input sets the reset vector table values at addresses 0000H and 0001H to the...

Page 57: ...errupt sources This flag is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is se...

Page 58: ...es the SP contents undefined be sure to initialize the SP before instruction execution Figure 4 12 Data to be Saved to Stack Memory Figure 4 13 Data to be Restored from Stack Memory Interrupt PSW PC15...

Page 59: ...t registers in pairs can be used as a 16 bit register AX BC DE and HL They can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figu...

Page 60: ...ction This manipulation can also be specified with an address 16 bit manipulation A symbol reserved by assembler is described as the operand of a 16 bit manipulation instruction When specifying an add...

Page 61: ...2 TCL2 FF48H 16 bit timer mode control register 20 TMC20 FF50H 8 bit compare register 80 CR80 W FF51H 8 bit timer register 80 TM80 R Undefined FF53H 8 bit timer mode control register 80 TMC80 R W 00H...

Page 62: ...gister 20 RXB20 R Undefined FF80H A D converter mode register 0 ADM0 R W 00H FF84H A D input select register 0 ADS0 FFD0H Multiplication data register A0 MRA0 W Undefined FFD1H Multiplication data reg...

Page 63: ...7E 4 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferre...

Page 64: ...word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 and BR addr16 instructions are executed CALL addr16 and BR addr16 instructions can branch...

Page 65: ...instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces Illustration 4 3 4 Register addressing Function Register pai...

Page 66: ...g instruction execution 4 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bi...

Page 67: ...ister of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to...

Page 68: ...is addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Descripti...

Page 69: ...cuted When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp ca...

Page 70: ...accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description...

Page 71: ...paces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4 4 7 Stack addressing Function The stack...

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Page 73: ...n Figure 5 1 enabling various methods of control Numerous other functions are provided that can be used in addition to the digital I O port function For more information on these additional functions...

Page 74: ...ed as input port an on chip pull up resistor can be specified by means of pull up resistor option register 0 PU0 P20 Input output Port 2 Input ASCK20 SCK20 P21 6 bit I O port TxD20 SO20 P22 Input outp...

Page 75: ...oftware control only 5 2 1 Port 0 This is a 4 bit I O port with output latches Port 0 can be specified as input or output mode in 1 bit units by using port mode register 0 PM0 When pins P00 to P03 are...

Page 76: ...input port pins on chip pull up resistors can be connected in 2 bit units by using pull up resistor option register 0 PU0 RESET input sets port 1 to input mode Figure 5 3 shows the block diagram of po...

Page 77: ...nd external interrupt input RESET input sets port 2 to input mode Figures 5 4 through 5 7 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output...

Page 78: ...VDD P ch P21 TxD20 SO20 WRPUB2 RD WRPORT WRPM PUB21 Output latch P21 PM21 Alternate function Selector Serial output enable signal Figure 5 5 Block Diagram of P21 PUB2 Pull up resistor option register...

Page 79: ...nd P25 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD P ch P22 RxD20 SI20 P23 INTP0 CPT20 SS20 P25 INTP2 TI80 WRPUB2 RD WR...

Page 80: ...gram of P24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal WRPUB2 Selector RD PM24 PUB24 Alternate function Alternate function P24 INTP1 TO...

Page 81: ...igure 5 8 shows a block diagram of port 5 Figure 5 8 Block Diagram of P50 to P53 PM Port mode register RD Port 5 read signal WR Port 5 write signal Caution When using the pins of port 5 as input pins...

Page 82: ...6 This is a 4 bit input port The port is also used as an analog input to the A D converter RESET input sets port 6 to input mode Figure 5 9 shows a block diagram of port 6 Figure 5 9 Block Diagram of...

Page 83: ...to Table 5 3 Caution As port 2 has an alternate function as external interrupt input when the port function output mode is specified and the output level is changed the interrupt request flag is set W...

Page 84: ...h pin of port 2 The pin so specified by PUB2 is connected to on chip pull up resistor regardless of the setting of the port mode register PUB2 is set with a 1 bit or 8 bit manipulation instruction RES...

Page 85: ...lation become undefined 5 4 2 Reading from I O port 1 In output mode The contents of the output latch can be read by using a transfer instruction The contents of the output latch are not changed 2 In...

Page 86: ...User s Manual U13045EJ2V0UM00 86 MEMO...

Page 87: ...tion can be stopped by executing the STOP instruction 6 2 Configuration of Clock Generator The clock generator consists of the following hardware Table 6 1 Configuration of Clock Generator Item Config...

Page 88: ...PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 02H Figure 6 2 Processor Clock Control Register Format Caution Bit 0 and bits 2 to 7 must be set to 0 Remarks 1...

Page 89: ...ystal or ceramic oscillation b External clock Caution When using the system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect fr...

Page 90: ...al U13045EJ2V0UM00 90 CHAPTER 6 CLOCK GENERATOR PD789104 789114 SUBSERIES Figure 6 4 Examples of Incorrect Resonator Connection 1 2 a Too long wiring b Crossed signal line VSS X1 X2 VSS X1 X2 PORTn n...

Page 91: ...91 Figure 6 4 Examples of Incorrect Resonator Connection 2 2 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates e Signa...

Page 92: ...nerator is determined by the processor clock control register PCC as follows a The slow mode 2fCPU 1 6 s at 5 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H...

Page 93: ...he CPU clock before switching 6 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 6 5 Switching CPU Clock 1 The CPU is reset when the RESET pin is made low on...

Page 94: ...User s Manual U13045EJ2V0UM00 94 MEMO...

Page 95: ...llation can be stopped by executing the STOP instruction 7 2 Configuration of Clock Generator The clock generator consists of the following hardware Table 7 1 Configuration of Clock Generator Item Con...

Page 96: ...s set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 02H Figure 7 2 Processor Clock Control Register Format Caution Bit 0 and bits 2 to 7 must be set to 0 Remarks 1...

Page 97: ...lock Oscillator a RC oscillation b External clock Caution When using the system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effec...

Page 98: ...U13045EJ2V0UM00 98 CHAPTER 7 CLOCK GENERATOR PD789124 789134 SUBSERIES Figure 7 4 Examples of Incorrect Resonator Connection 1 2 a Too long wiring b Crossed signal line VSS CL2 CL1 VSS CL2 PORTn n 0...

Page 99: ...7 4 Examples of Incorrect Resonator Connection 2 2 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A and B fluctuates e Signal is fetche...

Page 100: ...generator is determined by the processor clock control register PCC as follows a The slow mode 2fCPU 2 0 s at 4 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 0...

Page 101: ...the CPU clock before switching 7 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 7 5 Switching CPU Clock 1 The CPU is reset when the RESET pin is made low o...

Page 102: ...User s Manual U13045EJ2V0UM00 102 MEMO...

Page 103: ...put and PWM output of arbitrary frequency see CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watchdog timer WDTM The watchdog timer can generate non maskable interrupts maskable interrupts and RESET with arbit...

Page 104: ...nctions Timer interrupt Timer output Count value capture 1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output control is possible when a...

Page 105: ...rol register 16 bit timer mode control register 20 TMC20 Port mode register 2 PM2 Figure 8 1 Block Diagram of 16 Bit Timer Counter Remark fCLK fX or fCC CPT20 P23 INTP0 SS20 Internal bus Internal bus...

Page 106: ...ion instruction This register is free running during count clock input RESET input clears this register to 0000H and after which it resumes free running Cautions 1 The count value after releasing stop...

Page 107: ...ntrol 16 bit timer counter 20 TM20 16 bit timer mode control register 20 TMC20 Port mode register 2 PM2 1 16 bit timer mode control register 20 TMC20 16 bit timer mode control register 20 TMC20 contro...

Page 108: ...timer TOC20 0 1 Timer output data inverse control Inverse disabled Inverse enabled TOD20 0 1 Timer output data Timer output of 0 Timer output of 1 Capture edge selection TOE20 0 1 TCL201 0 0 Other th...

Page 109: ...r timer output set the output latch of PM24 and P24 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 8 3 Port Mode Register 2 Format 1 1 PM25 PM...

Page 110: ...pt request signal INTTM20 is generated Table 8 3 shows the interval time and Figure 8 5 shows the timing of the timer interrupt operation Caution When rewriting CR20 during count operation be sure to...

Page 111: ...13045EJ2V0UM00 111 Figure 8 5 Timing of Timer Interrupt Operation Remark N 0000H to FFFFH Count clock TM20 count value CR20 INTTM20 TO20 TOF20 0000H 0001H N FFFFH 0000H 0001H N FFFFH N N N N N Interru...

Page 112: ...dge becomes operation prohibited When the count value of the 16 bit timer register 20 TM20 matches the value set in CR20 the output status of the TO20 P24 INTP1 TO80 pin is inverted This enables timer...

Page 113: ...il the next capture edge detection Table 8 4 and Figure 8 9 show the setting contents of the capture edge and capture operation timing respectively Table 8 4 Settings of Capture Edge CPT201 CPT200 Cap...

Page 114: ...SET input clears TM20 to 0000H and restarts free running Figure 8 10 shows the timing of 16 bit timer register 20 readout Cautions 1 The count value after releasing stop becomes undefined because the...

Page 115: ...C 64 s 1 fCC 250 ns 23 fCC 2 0 s 211 fCC 512 s 23 fCC 2 0 s Remark fX System clock oscillation frequency ceramic crystal oscillation fCC System clock oscillation frequency RC oscillation 2 External ev...

Page 116: ...n 8 bit timer event counter 80 consists of the following hardware Table 9 3 8 Bit Timer Event Counter 80 Configuration Item Configuration Timer register 8 bits 1 TM80 Register Compare register 8 bits...

Page 117: ...the timer operation once If CR80 is rewritten in the timer operation enabled state a match interrupt request signal may occur at the moment of rewrite 2 Do not set CR80 to 00H in the PWM output mode...

Page 118: ...Mode Control Register 80 Format Caution Be sure to set TMC80 after stopping timer operation Remark fX System clock oscillation frequency ceramic crystal oscillation fCC System clock oscillation frequ...

Page 119: ...timer output set the output latch of PM24 and P24 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 9 3 Port Mode Register 2 Format PM2n 0 1 1 1...

Page 120: ...imer operation enabled state a match interrupt request signal may occur at the moment of rewrite 2 If the count clock setting and TM80 operation enabled are set in TMC80 simultaneously using an 8 bit...

Page 121: ...ure 9 4 Interval Timer Operation Timing Remark Interval time N 1 t N 00H to FFH Clear Clear Interrupt accept Interrupt accept Count start Interval time Interval time Interval time Count clock TM80 cou...

Page 122: ...e value of 8 bit timer register 80 TM80 is incremented When the count value of TM80 matches the value set to CR80 the value of TM80 is cleared to 0 and TM80 continues counting At the same time an inte...

Page 123: ...ed Square wave output is cleared 0 when bit 7 TCE80 in TMC80 is set to 0 Table 9 6 shows square wave output range and Figure 9 6 shows timing of square wave output Cautions 1 Before rewriting CR80 sto...

Page 124: ...Figure 9 6 Square Wave Output Timing Note The initial value of TO80 during output enable TOE80 1 becomes low level Clear Clear Interrupt accept Interrupt accept Count start Count clock TM80 count val...

Page 125: ...tput enable TOE80 1 and PWM output to enable PWME80 1 4 Set the count value to CR80 5 Set TM80 to operation enable TCE80 1 When the count value of 8 bit timer register 80 TM80 matches the value set to...

Page 126: ...ut Timing Note The initial value of TO80 upon output enable TOE80 1 is low level Caution Do not set CR80 to 00H in the PWM output mode otherwise PWM may not be output normally Count clock TM80 CR80 TC...

Page 127: ...xternal Event Counter Operation Timing Cautions 1 When rewriting CR80 in timer counter operation mode i e PWME80 bit 6 of 8 bit timer mode control register 80 TMC80 is set to 0 be sure to stop the tim...

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Page 129: ...fX 5 0 MHz Operation At fCC 4 0 MHz Operation Detection Time 211 1 fW 410 s 512 s 213 1 fW 1 64 ms 2 05 ms 215 1 fW 6 55 ms 8 19 ms 217 1 fW 26 2 ms 32 8 ms fW fX or fCC fX System clock oscillation fr...

Page 130: ...mer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 10 1 Block Diagram of Watchdog Timer Remark fW fX or fCC Internal bus Internal bus Prescaler Selector Control circuit fW 26 fW...

Page 131: ...tem clock oscillation frequency ceramic crystal oscillation fCC System clock oscillation frequency RC oscillation TCL22 0 0 1 1 0 0 0 0 0 TCL22 TCL21 TCL20 TCL2 R W R W 7 6 5 4 3 2 1 0 TCL21 0 1 0 1 f...

Page 132: ...watchdog timer is cleared by setting RUN to 1 the actual overflow time is up to 0 8 shorter than the time set by timer clock select register 2 TCL2 2 In watchdog timer mode 1 or 2 set WDTM4 to 1 after...

Page 133: ...RUN is not set to 1 and the runaway detection time is exceeded the system is reset or a non maskable interrupt is generated by the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation i...

Page 134: ...t as the highest of all the maskable interrupts The interval timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the int...

Page 135: ...analog inputs ANI0 to ANI3 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time an A D session is completed 11 2 8 Bit A D Conv...

Page 136: ...ccessive approximation register is loaded into ADCR0 which is an 8 bit register that holds the result of A D conversion ADCR0 can be read with an 8 bit memory manipulation instruction RESET input make...

Page 137: ...s that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is supplied to any of these pins the conversion value for the correspond...

Page 138: ...e will fall below 14 s Cautions 1 The result of conversion performed immediately after bit 7 ADCS0 is set is undefined 2 The result of conversion after ADCS0 is cleared may be undefined for details re...

Page 139: ...the analog voltages to be converted to a digital signal ADS0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 11 3 Format of A D Input Select Registe...

Page 140: ...B of the SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 6 of the SAR is set automatically and comparison shifts to the next stage The next voltage tap of the series resistor s...

Page 141: ...11 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI3 and the A D conversion result A D conversion result register 0 ADCR0...

Page 142: ...ser s Manual U13045EJ2V0UM00 142 Figure 11 5 Relationships between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D conversion result ADCR0 1 512 1 256 3 512 2 256 5 512 3 256 50...

Page 143: ...cified in A D input selection register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same an interrupt request signal INTAD0...

Page 144: ...a voltage not lower than AVDD or not higher than AVSS even within the absolute maximum rating is input to a conversion channel the conversion output of the channel becomes undefined It may affect the...

Page 145: ...cause of this be sure to read out the A D conversion result while the A D converter is in operation Furthermore when reading out an A D conversion result after A D converter operation has stopped be s...

Page 146: ...ing noise may occur which prevents an A D conversion result from being attained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Interrupt r...

Page 147: ...in Figure 11 12 Figure 11 12 AVDD Pin Treatment 10 Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins Therefore if the output impedanc...

Page 148: ...User s Manual U13045EJ2V0UM00 148 MEMO...

Page 149: ...e of analog inputs ANI0 to ANI3 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time an A D session is completed 12 2 10 Bit A...

Page 150: ...successive approximation register is loaded into ADCR0 which is a 10 bit register the holds the result of A D conversion ADCR0 can be read with an 8 bit memory manipulation instruction RESET input mak...

Page 151: ...3 are the 4 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the r...

Page 152: ...time will fall below 14 s Cautions 1 The result of conversion performed immediately after bit 7 ADCS0 is set is undefined 2 The result of conversion after ADCS0 is cleared may be undefined for details...

Page 153: ...the analog voltages to be converted to a digital signal ADS0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 12 3 Format of A D Input Select Registe...

Page 154: ...e MSB of the SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 8 of the SAR is set automatically and comparison shifts to the next stage The next voltage tap of the series resist...

Page 155: ...ined 12 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI3 and the A D conversion result A D conversion result register 0...

Page 156: ...EJ2V0UM00 156 Figure 12 5 Relationships between Analog Input Voltage and A D Conversion Result 1 023 1 022 1 021 3 2 1 0 A D conversion result ADCR0 1 2 048 1 1 024 3 2 048 2 1 024 5 2 048 3 1 024 2 0...

Page 157: ...cified in A D input select register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same an interrupt request signal INTAD0 is...

Page 158: ...If a voltage not lower than AVDD or not higher than AVSS even within the absolute maximum rating is input a conversion channel the conversion output of the channel becomes undefined It may affect the...

Page 159: ...ecause of this be sure to read out the A D conversion result while the A D converter is in operation Furthermore when reading out an A D conversion result after A D converter operation has stopped be...

Page 160: ...upling noise may occur which prevents an A D conversion result from being attained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Interrup...

Page 161: ...in Figure 12 10 Figure 12 12 AVDD Pin Treatment 10 Input impedance of the AVDD pin A series resistor string of several 10 k is connected across the AVDD and AVSS pins Therefore if the output impedanc...

Page 162: ...User s Manual U13045EJ2V0UM00 162 MEMO...

Page 163: ...hable between MSB first and LSB first transmission This mode is used to transmit 8 bit data using three lines a serial clock SCK20 line and two serial data lines SI20 and SO20 As it supports simultane...

Page 164: ...ransmit shift register 20 TXS20 Transmit shift clock Selector CSIE20 DAP20 Data phase control Reception shift clock SI20 P22 RxD20 SO20 P21 TxD20 4 Parity operation Stop bit addition Reception data co...

Page 165: ...clock Transmission shift clock Reception shift clock Reception detection TXE20 RXE20 CSIE20 Selector Selector Selector 1 2 1 2 Transmission clock counter Reception clock counter 4 fX 2 fX 23 fX 24 fX...

Page 166: ...uffer register 20 RXB20 RXB20 holds receive data New receive data is transferred from receive shift register 0 RXS20 per 1 byte of data received When the data length is specified as seven bits the rec...

Page 167: ...ed to 00H if UART mode is selected CSIE20 0 1 3 wire serial I O mode operation control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Ope...

Page 168: ...eared to 00H 3 Switch operating modes after halting a serial transmit receive operation TXE20 0 1 Transmit operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 Symbol Address After reset R W...

Page 169: ...SCK20 clock CMOS output input 1 0 1 Internal SCK20 clock output 1 1 0 1 LSB External SCK20 clock input 1 0 1 Internal SCK20 clock output Other than above Setting prohibited 3 Asynchronous serial inter...

Page 170: ...face mode register 20 ASIM20 the stop bit detection in the case of reception is performed with 1 bit 2 Be sure to read receive buffer register 20 RXB20 when an overrun error occurs If not every time t...

Page 171: ...Be sure not to select n 1 during operation at fX 5 0 MHz because n 1 exceeds the baud rate limit 3 When the external input clock is selected set port mode register 2 PM2 in input mode Remarks 1 fX Sys...

Page 172: ...is generated by scaling the system clock The baud rate generated from the system clock is estimated by using the following expression Baud rate Hz fX System clock oscillation frequency ceramic crysta...

Page 173: ...baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock pulse received at the ASCK20 pin Table 13 4 Relations...

Page 174: ...21 SO20 TxD20 and P22 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operating mode register 20 CSIM20 and asynchronous serial interface mode r...

Page 175: ...lation instruction RESET input clears ASIM20 to 00H Caution Be sure to set bits 0 and 1 to 0 TXE20 0 1 Transmit operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 Symbol Address After rese...

Page 176: ...pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate that complies with the MIDI standard It is recommended that the ceramic crystal oscillation be used for the system...

Page 177: ...ration enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock pulse input to the SCK20 pin Output of the dedicated baud rate generator SSE20...

Page 178: ...tion control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 Symbol Address After reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive...

Page 179: ...ceive buffer register 20 RXB20 when an overrun error occurs If not every time the data is received an overrun error is generated PE20 0 1 Parity error flag 0 0 0 0 0 PE20 FE20 OVE20 ASIS20 Symbol Addr...

Page 180: ...limit 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fX System clock oscillation frequency ceramic crystal oscillation 2 n Values specified by the set...

Page 181: ...s generated by scaling the system clock The baud rate generated from the system clock is estimated by using the following expression Baud rate Hz fX System clock oscillation frequency ceramic crystal...

Page 182: ...e ASCK20 pin The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to ASCK20 pin Table 13 6 Relati...

Page 183: ...ta Format Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bit 2 bits When 7 bits are selected as the number of character bits only the l...

Page 184: ...bit is counted and if the number is odd a parity error is generated ii Odd parity At transmission Conversely to even parity the transmission operation is controlled so that the number of bits with a v...

Page 185: ...face Transmission Completion Interrupt Timing a Stop bit length 1 b Stop bit length 2 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during a transmit operation If ASIM20...

Page 186: ...ter the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to receive buffer register 20 RXB20 and a reception...

Page 187: ...13 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception o...

Page 188: ...RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception receive buffer register 20 RXB20 and receive completion interrupt 20 INTSR20 are as follows When RXE20 is set...

Page 189: ...ion RESET input clears CSIM20 to 00H Caution Bits 4 and 5 must be fixed to 0 CSIE20 0 1 3 wire serial I O mode operation control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After r...

Page 190: ...ve operation is halted TXE20 0 1 Transmit operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 Symbol Address After reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit o...

Page 191: ...PS203 1 n 8 3 Values in parentheses apply to operation with fX 5 0 MHz If the internal clock is used as the serial clock for the 3 wire serial I O mode set the TPS200 to TPS203 bits to set the frequen...

Page 192: ...20 Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI0 pin is latched in the receive buffer register RXB20 SIO20 on the rise of SCK20 At the en...

Page 193: ...n when DAP20 0 CKP20 0 SSE20 1 Notes 1 The value of the last bit previously output is output 2 DO0 is output until SS20 rises When SS20 is high SO20 is in a high impedance state 1 2 3 4 5 6 7 8 DI7 DI...

Page 194: ...0 Note The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 1 2 3 4 5 6 7 8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7...

Page 195: ...efore the first rising of SCK20 2 SO20 is high until SS20 rises after completion of DO0 output When SS20 is high SO20 is in a high impedance state vii Master operation when DAP20 1 CKP20 0 SSE20 0 1 2...

Page 196: ...The data of SI20 is loaded at the first falling edge of SCK20 Make sure that the master outputs the first bit before the first falling of SCK20 2 SO20 is high until SS20 rises after completion of DO0...

Page 197: ...bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20 0 Note The value of the last bit previously output is output 1 2 3 4 5 6 7 8 DO7 Note DO6 DO5 DOI4 DO3 DO2 DO1 DI7 DI6 DI...

Page 198: ...transmission shift register TXS20 SIO20 when the following two conditions are satisfied Serial operation mode register 20 CSIM20 bit 7 CSIE20 1 Internal serial clock is stopped or SCK20 is a high leve...

Page 199: ...ESET input makes this register undefined Caution Although this register is manipulated with a 16 bit memory manipulation instruction it can be also manipulated with an 8 bit memory manipulation instru...

Page 200: ...er value 3 CPU clock Start Clear Counter output 16 bit adder 16 bit multiplication result storage register 0 Master MUL0 16 bit multiplication result storage register 0 Slave Multiplication data regis...

Page 201: ...ltiplier MULC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Figure 14 2 Multiplier Control Register 0 Format Caution Be sure to set bits 1 to 7...

Page 202: ...ctor is added to the data of MUL0 at each CPU clock and the counter value is incremented by one 3 If MULST0 is cleared when the counter value is 111B the operation is stopped At this time MUL0 holds t...

Page 203: ...d The non maskable interrupt has one source of interrupt from the watchdog timer 2 Maskable interrupt These interrupts undergo mask control If two or more interrupts with the same priority are simulta...

Page 204: ...6H C 2 INTP1 0008H 3 INTP2 000AH 4 INTSR20 End of serial interface 20 UART reception Internal 000CH B INTCSI20 End of serial interface 20 3 wire transfer 5 INTST20 End of serial interface 20 UART 000E...

Page 205: ...errupt IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag Internal bus Interrupt request Vector table address generator Standby release signal MK IF IE Internal bus Interrupt re...

Page 206: ...mode register INTM0 Program status word PSW Table 15 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 15 2 Flags Corresponding to Int...

Page 207: ...W enabled only when the watchdog timer is used as an interval timer If the watchdog timer mode 1 and 2 are used set the TMIF4 flag to 0 2 Because port 2 has an alternate function as the external inter...

Page 208: ...sed in watchdog timer mode 1 and 2 its value becomes undefined 2 Because port 2 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode...

Page 209: ...MK 1 to disable interrupts After setting the INTM0 register clear the interrupt request flag IF 0 then clear the interrupt mask flag MK 0 which will enable interrupts 0 0 1 1 ES21 ES20 ES11 ES10 ES01...

Page 210: ...8 bit units and can carry out operations using a bit manipulation and dedicated instructions EI DI When a vectored interrupt request is acknowledged PSW is automatically saved into a stack and the IE...

Page 211: ...the stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 15 6 shows the flowchart from non maskable interrupt...

Page 212: ...knowledging Non Maskable Interrupt Request Start WDTM4 1 watchdog timer mode is selected Interval timer No WDT overflows No Yes Reset processing No Yes Yes Interrupt request is generated Interrupt pro...

Page 213: ...equest to Processing Minimum Time Maximum TimeNote 9 clocks 19 clocks Note The wait time is maximum when an interruptrequestisgeneratedimmediately before BT and BF instruction Remark 1 clock fCPU CPU...

Page 214: ...t Program Algorithm IF Interrupt request flag MK Interrupt mask flag IE Flag to control maskable interrupt request acknowledgement 1 enable 0 disable Start IF 1 MK 0 IE 1 Vectored interrupt processing...

Page 215: ...after the next instruction is executed Figure 15 11 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction I...

Page 216: ...set Example 2 A multiple interrupt is not generated because interrupts are not enabled Because interrupts are not enabled in interrupt INTxx servicing an EI instruction is not issued interrupt reques...

Page 217: ...on of the execution of the next instruction even if the interrupt request maskable interrupt non maskable interrupt and external interrupt is generated during the execution The following shows such in...

Page 218: ...User s Manual U13045EJ2V0UM00 218 MEMO...

Page 219: ...stops the entire system The power consumption of the CPU can be substantially reduced in this mode The low voltage VDD 1 8 V of the data memory can be retained Therefore this mode is useful for retai...

Page 220: ...cillation stabilization time of the PD789124 and 789134 Subseries is fixed to 27 fCC Figure 16 1 Oscillation Stabilization Time Select Register Format Caution The wait time after the STOP mode in a ce...

Page 221: ...Operating Status Item HALT Mode Operating Status Clock generator System clock can be oscillated Clock supply to CPU stops CPU Operation stopped Port Output latch Retains the status before setting the...

Page 222: ...is executed Figure 16 2 Releasing HALT Mode by Interrupt Remarks 1 The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged 2 The wait time is...

Page 223: ...fCC 32 s at fCC 4 0 MHz operation Remark fX System clock oscillation frequency ceramic crystal oscillation fCC System clock oscillation frequency RC oscillation Table 16 2 Operation after Release of H...

Page 224: ...ately after the STOP instruction has been executed the wait time set by the oscillation stabilization time select register OSTS elapses and then an operation mode is set The operation status in the ST...

Page 225: ...ss is executed Caution Be sure to use a vectored interrupt when releasing the STOP mode in the PD78F9116 and 78F9136 A runaway may be generated in the microcontroller if the STOP mode is released by a...

Page 226: ...ries 27 fCC 32 s at fCC 4 0 MHz operation Remark fX System clock oscillation frequency ceramic crystal oscillation fCC System clock oscillation frequency RC oscillation Table 16 4 Operation after Rele...

Page 227: ...nput or during the oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabili...

Page 228: ...stabilization time wait Normal operation reset processing Delay Delay Hi Z X1 CL1 Internal reset signal Port pin Overflow in watchdog timer During normal operation Reset period oscillation continues...

Page 229: ...gister TPC20 Undefined 8 bit timer event counter Timer register TM80 00H Compare register CR80 Undefined Mode control register TMC80 00H Watchdog timer Timer clock select register TCL2 00H Mode regist...

Page 230: ...rdware Status after Reset Multiplier 16 bit multiplication result storage register MUL0 Undefined Data register A MRA0 Undefined Data register B MRB0 Undefined Control register MULC0 00H Interrupt Req...

Page 231: ...refer to 16 2 2 STOP mode Electrical specifications Refer to the individual data sheets Cautions 1 There are differences in noise immunity and noise radiation between the flash memory versions and mas...

Page 232: ...Flashpro III and by means of serial communication Select a communication mode from those listed in Table 18 2 To select a communication mode the format shown in Figure 18 1 is used Each communication...

Page 233: ...e memory Data write Write to flash memory based on write start address and number of data written number of bytes Batch verify Compares all contents of memory with input data 18 1 3 Flashpro III conne...

Page 234: ...gure 18 4 Flashpro III Connection in Pseudo 3 Wire Mode When P0 Is Used Note n 1 2 VPPnNote VDD RESET SO SI GND VPP VDD AVDD RESET RxD20 TxD20 VSS AVSS CLK X1 Flashpro III PD78F9116 VPPnNote VDD RESET...

Page 235: ...shpro III Connection in 3 Wire Serial I O Mode Note n 1 2 Figure 18 6 Flashpro III Connection in UART Mode Note n 1 2 VPPnNote VDD RESET SCK SO SI GND VPP VDD AVDD RESET SCK20 SI20 SO20 VSS AVSS CLK P...

Page 236: ...045EJ2V0UM00 236 Figure 18 7 Flashpro III Connection in Pseudo 3 Wire Mode When P0 Is Used Note n 1 2 VPPnNote VDD RESET SCK SO SI GND VPP VDD AVDD RESET P00 Serial clock CLK P03 P02 Serial input P01...

Page 237: ...ashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro 4 0 MHz SIO CLK 1 0 MHz UART COMM PORT UART ch0 8 CPU CLK On Target Board On Target Board 4 1943 MHz UART BPS 9600 bpsNote 2 Pseudo 3 wire...

Page 238: ...User s Manual U13045EJ2V0UM00 238 MEMO...

Page 239: ...for Pins Pin Mask Option P50 to P53 On chip pull up resistor can be specified in 1 bit units For P50 to P53 port 5 an on chip pull up resistor can be specified by the mask option The mask option is sp...

Page 240: ...User s Manual U13045EJ2V0UM00 240 MEMO...

Page 241: ...direct address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r an...

Page 242: ...lag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in...

Page 243: ...fr sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte HL...

Page 244: ...ddr16 A HL 1 6 A CY A HL A HL byte 2 6 A CY A HL byte ADDC A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY...

Page 245: ...6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL A HL byte 2 6 A A HL byte OR A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2...

Page 246: ...saddr 2 4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 SET1...

Page 247: ...ddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jd...

Page 248: ...None 1st Operand A ADD MOVNote MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCHNote XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC...

Page 249: ...P None 1st Operand AX ADDW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVWNote INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd...

Page 250: ...0UM00 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand AX addr16 addr5 addr16 1st Operand Basic Instructions BR CALL CALLT BR BR BC BNC BZ BNZ Compound Instructions...

Page 251: ...the development tool configuration Support of the PC98 NX Series Unless otherwise specified the PD789134 Subseries supported by IBM PC AT and compatibles can be used for the PC98 NX Series When using...

Page 252: ...kage C compiler package System simulator Device file C compiler source file Integrated debugger Embedded software OS Host machine PC or EWS Interface adapter In circuit emulator Emulation board Emulat...

Page 253: ...ing the Project Manager of Windows included in the assembler package Part number S CC78K0S DF789136Note File containing the information inherent to the device Device file Used in combination with RA78...

Page 254: ...S C bus supported PC card and interface cable necessary when using a notebook PC as the host machine of the IE 78K0S NS PCMCIA socket supported Interface adapter necessary when using an IBM PC AT or c...

Page 255: ...ating system to be used S ID78K0S NS Host Machine OS Supply Media AA13 PC 9800 Series Japanese WindowsNote 3 5 2HD FD AB13 IBM PC AT compatibles Japanese WindowsNote 3 5 2HC FD Note Also operates in t...

Page 256: ...User s Manual U13045EJ2V0UM00 256 MEMO...

Page 257: ...OS controls task execution order and then perform the switching process to a task to be executed Caution when used in a PC environment The MX78K0S is a DOS based application Use this software in the D...

Page 258: ...258 User s Manual U13045EJ2V0UM00 MEMO...

Page 259: ...Asynchronous serial interface status register 20 ASIS20 170 179 A D conversion result register 0 ADCR0 136 A D converter mode register 0 ADM0 138 A D input select register 0 ADS0 139 B Baud rate gene...

Page 260: ...register 5 PM5 83 Processor clock control register PCC 88 96 Pull up resistor option register 0 PU0 84 Pull up resistor option register B2 PUB2 84 R Receive buffer register 20 RXB20 166 S Serial opera...

Page 261: ...nterrupt request flag register 0 207 IF1 Interrupt request flag register 1 207 INTM0 External interrupt mode register 0 209 M MK0 Interrupt mask flag register 0 208 MK1 Interrupt mask flag register 1...

Page 262: ...clock select register 2 131 TCP20 16 bit timer capture register 20 106 TM20 16 bit timer register 20 106 TM80 8 bit timer register 80 117 TMC20 16 bit timer mode control register 20 116 TMC80 8 bit t...

Page 263: ...ion frequency during RC oscillation to CHAPTER 7 2 0 to 4 0 MHz CLOCK GENERATOR PD789124 789134 SUBSERIES Addition of caution regarding rewrite of CR20 CHAPTER 8 16 BIT TIMER COUNTER Addition of cauti...

Page 264: ...User s Manual U13045EJ2V0UM00 264 MEMO...

Page 265: ...02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 2...

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