NEC mPD789101, User Manual

Page: 101 / 265

CHAPTER 7 CLOCK GENERATOR (
µ
PD789124, 789134 SUBSERIES)
User’s Manual U13045EJ2V0UM00
101
7.6 Changing Setting of CPU Clock
7.6.1 Time required for switching CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (refer to Table 7-2).
Table 7-2. Maximum Time Required for Switching CPU Clock
Set Value before Switching Set Value after Switching
PCC1 PCC1 PCC1
0 1
0 4 clocks
1 2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
7.6.2 Switching CPU clock
The following figure illustrates how the CPU clock switches.
Figure 7-5. Switching CPU Clock
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (2
7
/f
CC
) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (2.0
µ
s: at 4.0-MHz
operation).
<2> After the time during which the V
DD
voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can
be selected.
V
DD
RESET
CPU clock
Slow
operation Fastest
operation
Wait (32 s: at 4.0-MHz operation)
Internal reset operation
µ