NEC mPD789101, User Manual

Page: 133 / 265

CHAPTER 10 WATCHDOG TIMER
User’s Manual U13045EJ2V0UM00
133
10.4 Operation of Watchdog Timer
10.4.1 Operation as watchdog timer
The watchdog timer operates to detect a runaway when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20
to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started.
Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started. By setting
RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway detection
time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN
to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Caution The actual runaway detection time may be up to 0.8% shorter than the set time.
Table 10-4. Runaway Detection Time of Watchdog Timer
TCL22 TCL21 TCL20 Runaway Detection Time At f
X
= 5.0-MHz Operation At f
CC
= 4.0-MHz Operation
0 0 0 2 11
×
1/f
W
410
µ
s 512
µ
s
0 1 0 2 13
×
1/f
W
1.64 ms 2.05 ms
1 0 0 2 15
×
1/f
W
6.55 ms 8.19 ms
1 1 0 2 17
×
1/f
W
26.2 ms 32.8 ms
f
W
: f
X
or f
CC
f
X
: System clock oscillation frequency (ceramic/crystal oscillation)
f
CC
: System clock oscillation frequency (RC oscillation)