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CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
18.6 Timing Charts
In the I
2
C bus mode, the master outputs an address on the serial bus and selects one of the slave devices from
multiple slave devices as the communication target.
The master transmits the TRC0 bit, bit 3 of I
2
C bus status register 0 (IICS0), that indicates the transfer direction
of the data after the slave address and starts serial communication with the slave.
Figures 18-20 and 18-21 are the timing charts for data communication.
Shifting of serial shift register 0 (IIC0) is synchronized to the falling edge of the serial clock (SCL0). The transmission
data is transferred to the SO0 latch and output from the SDA0 pin with the MSB first.
The data input at the SDA0 pin is received by IIC0 at the rising edge of SCL0.