512
CHAPTER 26 ROM CORRECTION
User’s Manual U12697EJ3V0UM
(1) ROM correction address register (CORAH, CORAL)
The register that sets the header address (correction address) of the command within the mask ROM that needs
to be repaired. A maximum of four program locations can be repaired with ROM correction. First of all, the channel
is selected with bit 0 (CORCH0) and bit 1 (CORCH1) of the ROM correction control register (CORC), and the
address is then set in the specified channel’s address pointer when the address is written in CORAH and CORAL.
Figure 26-3. Format of ROM Correction Address Register (CORAH, CORAL)
7
0
Address After reset
R/W
CORAH
FF89H
00H
R/W
15
0
Address After reset
R/W
CORAL
FF8AH
0000H
R/W
(2) Comparator
ROM correction address registers H and L (CORAH, CORAL) normally compare the corrected address value
with the fetch register value. If any of the ROM correction control register (CORC) bits between bit 4 to bit 7
(COREN0 to 3) are 1 and the correct address matches the fetch address value, a table reference instruction
(CALLT) is issued from the ROM correction circuit.
26.3 Control Register for ROM Correction
ROM correction is controlled by the ROM correction control register (CORC).
(1) ROM correction control register (CORC)
The register that controls the issuance of the table reference instruction (CALLT) when the correct address set
in ROM correction address registers H and L (CORAH, CORAL) match the value of the fetch address.
This is composed of a correction enable flag (COREN0 to 3) that enbales or disables match detection with the
comparator, and four channel correction pointers.
CORC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CORC to 00H.
