CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
User’s Manual U12697EJ3V0UM
272
(c) Baud rate generator control registers 1 and 2 (BRGC1, BRGC2)
BRGC1 and BRGC2 are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets BRGC1 and BRGC2 to 00H.
Address: 0FF76H, 0FF77H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
BRGCn
0
TPSn2
TPSn1
TPSn0
MDLn3
MDLn2
MDLn1
MDLn0
TPSn2
TPSn1
TPSn0
5-bit counter source clock selection
m
0
0
0
External clock (ASCKn)
0
0
0
1
f
XX
(12.5 MHz)
0
0
1
0
f
XX
/2 (6.25 MHz)
1
0
1
1
f
XX
/4 (3.13 MHz)
2
1
0
0
f
XX
/8 (1.56 MHz)
3
1
0
1
f
XX
/16 (781 kHz)
4
1
1
0
f
XX
/32 (391 kHz)
5
1
1
1
TO1 (TM1 output)
0
MDLn3
MDLn2
MDLn1
MDLn0
Baud rate generator
k
input clock selection
0
0
0
0
f
SCK
/16
0
0
0
0
1
f
SCK
/17
1
0
0
1
0
f
SCK
/18
2
0
0
1
1
f
SCK
/19
3
0
1
0
0
f
SCK
/20
4
0
1
0
1
f
SCK
/21
5
0
1
1
0
f
SCK
/22
6
0
1
1
1
f
SCK
/23
7
1
0
0
0
f
SCK
/24
8
1
0
0
1
f
SCK
/25
9
1
0
1
0
f
SCK
/26
10
1
0
1
1
f
SCK
/27
11
1
1
0
0
f
SCK
/28
12
1
1
0
1
f
SCK
/29
13
1
1
1
0
f
SCK
/30
14
1
1
1
1
Setting prohibited
–
Cautions 1. If a write operation to BRGC1 and BRGC2 is performed during communication, the
baud rate generator output will become garbled and normal communication will not
be achieved. Consequently, do not write in BRGC1 or BRGC2 during communications.
2. Refer to the data sheet for details of the high-/low-level width of ASCKn when
selecting the external clock (ASCK) for the source clock of the 5-bit counter.