579
APPENDIX E REVISION HISTORY
User’s Manual U12697EJ3V0UM
2nd edition
Edition
Contents
Applied to:
(3/4)
CHAPTER 17
3-WIRE SERIAL
I/O MODE
CHAPTER 18
I
2
C BUS MODE
(
µ
PD784225Y
SUBSERIES
ONLY)
CHAPTER 21
EDGE DETECTION
FUNCTION
CHAPTER 22
INTERRUPT
FUNCTIONS
CHAPTER 23
LOCAL BUS
INTERFACE
FUNCTONS
CHAPTER 24
STANDBY
FUNCTION
CHAPTER 25
RESET FUNCTION
CHAPTER 26
ROM CORREC-
TION
CHAPTER 27
µ
PD78F4225 AND
µ
PD78F4225Y
PROGRAMMING
Modification of
Figure 17-1 Block Diagram of Clocked Serial Interface (in 3-
Wire Serial I/O Mode)
Modification of
Figure 18-3 Format of I
2
C Bus Control Register (IICC0)
Addition of note about bit 3 (TRC0) to
Figure 18-4 Format of I
2
C Bus Status
Register (IICS0)
Modification of
Figure 18-5 Format of Prescaler Mode Register (SPRM0) for
Serial Clock
Modification of description about interrupt request timing of master operation and
slave operation in
18.5.7 I
2
C interrupt request (INTIIC0)
Modification of value in
Table 18-5 Wait Times
Modification of
Figure 21-2 Block Diagram of P00 to P05
Addition of remark 3 to
Table 22-2 Interrupt Request Sources
Modification of
Figure 22-33 Data Transfer Control Timing
Modification of
Figure 22-36 Automatic Addition C Ring Control Block
Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation)
Modification of
Figure 22-37 Automatic Addition C Ring Control Timing
Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation)
Modification of
Figure 22-38 Automatic Addition C Ring Control Block
Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation)
Modification of
Figure 22-39 Automatic Addition C Ring Control Timing
Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation)
23.2 Control Registers
Modification of
Figure 23-1 Format of Memory Expansion Mode Register (MM)
Addition of
(3) Programmable wait control register 2 (PWC2)
Modification of
Figure 24-1 Standby Function State Transition
Modification of
Figure 24-4 Format of Oscillation Stabilization Time
Specification Register (OSTS)
Modification of
Table 24-2 Operating States in HALT Mode
Modification of
Figure 24-5 Operations After Releasing HALT Mode
Modification of caution in
24.4.1 Settings and operating states of STOP mode
Modification of
Table 24-5 Operating States in STOP Mode
Modification of
Figure 24-6 Operations After Releasing STOP Mode
Modification of
Table 24-7 Operating States in IDLE Mode
Modification of
Figure 24-9 Operations After Releasing IDLE Mode
Modification of description in
(iii) Releasing the HALT mode by RESET input
Modification of description in
(iii) Releasing the IDLE mode by RESET input
Modification of
Figure 25-2 Receiving Reset Signal
Modification of
Table 26-1 Differences Between 78K/IV ROM Correction and
78K/0 ROM Correction
Modification of example of four pointer settings in
26.5 Conditions for Executing
ROM Correction
Modification of
Figure 27-1 Format of Internal Memory Size Switching Register
(IMS)
Addition of dedicated flash programmer (Flashpro III)
