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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2
User’s Manual U12697EJ3V0UM
9.5 Cautions
(1) Error when the timer starts
The time until the coincidence signal is generated after the timer starts has a maximum error of one clock. The
reason is the starting of 8-bit timer counters 1 and 2 (TM1, TM2) is asynchronous with respect to the count pulse.
Figure 9-11. Start Timing of 8-Bit Timer Counter
TM1, TM2 count value
00H
01H
02H
04H
Count pulse
Timer starts
03H
(2) Operation after the compare register is changed while the timer is counting
If the value after 8-bit compare registers 10 and 20 (CR10, CR20) changes is less than the value of 8-bit timer
counter 1, 2 (TM1, TM2), counting continues, overflows, and counting starts again from 0. Consequently, when
the value (M) after CR10, CR20 changes is less than the value (N) before the change, the timer must restart
after CR10, CR20 changes.
Figure 9-12. Timing After Compare Register Changes During Timer Counting
CR10, CR20
N
M
Count pulse
TM1, TM2 count value
X – 1
X
FFFFH
0000H
0001H
0002H
Caution Except when the TI1, TI2 input is selected, always set TCE1 = 0, TCE2 = 0 before setting the
STOP mode.
Remark
N > X > M
(3) TM1, TM2 read out during timer operation
Since the count clock stops temporarily when TM1 and TM2 are read during operation, select for the count clock
a waveform with a high and low level that exceed 2 cycles of the CPU clock.
When reading TM1 and TM2 during cascade connection, to avoid reading while the count is changing, take
measures such as obtaining a count match by reading twice using software.