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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U12697EJ3V0UM
C (R2):
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This register functions as a loop counter and can be used by the DBNZ instruction.
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This register can store the offset in based indexed addressing.
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This register is used as the counter in string and SACW instructions.
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This register is used as the data pointer in a MACW or MACSW instruction.
RP2:
•
When context switching is used, this register saves the lower 16 bits of the program counter (PC).
RP3:
•
When context switching is used, this register saves the higher 4 bits of the program counter (PC) and the program
status word (PSW) (except bits 0 to 3 in PSWH).
VVP (RG4):
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This register functions as a pointer and specifies the base address in register indirect addressing, based
addressing, and based indirect addressing.
UUP (RG5):
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This register functions as a user stack pointer and implements another stack separate from the system stack
by the PUSHU and POPU instructions.
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This register functions as a pointer and acts as the register that specifies the base address during register indirect
addressing and based addressing.
DE (RP6), HL (RP7):
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This register stores the offset during indexed addressing and based indexed addressing.
TDE (RG6):
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This register functions as a pointer and sets the base address in register indirect addressing and based
addressing.
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This register functions as a pointer in string and SACW instructions.
