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CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS
User’s Manual U12697EJ3V0UM
23.6.3 External access status enable register
The external access status enable register (EXAE) controls the EXA signal output indicated during external access.
EXAE are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets to 00H.
Figure 23-14. Format of External Access Status Enable Register (EXAE)
Address: 0FF8DH After reset: 00H
Symbol
7
6
5
4
3
2
1
0
EXAE
0
0
0
0
0
0
0
EXAE0
EXAE
P37 function
0
Port function
1
External access status function
23.6.4 External access status signal timing
A timing chart for the P37/EXA and external bus interface pin is shown below. The EXA signal is set at low active,
and indicates the external access status when at “0”.
(a) Data fetch timing
Address
P4, P5, P60 to P63
P67/ASTB
P64/RD
P65/WR H
P37/EXA