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CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS
User’s Manual U12697EJ3V0UM
23.5.2 Access wait
An access wait is inserted during low RD and WR signals. The low level is lengthened by 1/f
XX
(80 ns, f
XX
= 12.5
MHz) per cycle.
The wait insertion methods are the programmable wait function that automatically inserts a preset number of cycles
and the external wait function that is controlled from the outside by the wait signal.
Wait cycle insertion control is set by the programmable wait control register (PWC1) for the 1 MB memory space.
If an internal ROM or internal RAM is accessed during a high-speed fetch, a wait is not inserted. If accessing an
internal SFR, a wait is inserted based on required timing unrelated to this setting.
If set so that an access has the same number of cycles as for an external ROM, a wait is also inserted in an internal
ROM access in accordance with the PWC1 setting.
If there is space that was externally selected to be controlled by the wait signal by PWC1, pin P66 acts as the WAIT
signal input pin. RESET input makes pin P66 act as an ordinary I/O port.
Figures 23-10 to 23-12 show the bus timing when an access wait is inserted.
