NEC mPD17120 Subseries User Manual Download Page 133

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CHAPTER 13 PERIPHERAL HARDWARE

118

Figure 13-1. Configuration of the 8-bit Timer Counter

TMOSEL

P0DBIO3

Timer

modulo register (8)

(TMM)

Timer

comparator (8)

P0D

output

latch

Interrupt control
register (RF : 0FH)

INT

Timer mode register
(RF : 11H)

TMRES

TMEN

TMCK1

TMCK0

Internal bus

Timer carry
output control
mode register
(RF : 12H)

Bit I/O port
control register
(RF : 33H)

Match

Reset

Clear

P0D

TMOUT

IRQTM set signal

IRQTM clear signal

Latch

/32

/256

/2048

Selector

CLK
R

Reset

INT

Internal
RESET

Timer count

(TMC)

Data buffer

(DBF)

TMOUT

Summary of Contents for mPD17120 Subseries

Page 1: ...Document No IEU 1367A O D No IEU 835A Date Published July 1995 P Printed in Japan µPD17120 µPD17121 µPD17132 µPD17133 µPD17P132 µPD17P133 µPD17120 SUBSERIES 4 BIT SINGLE CHIP MICROCONTROLLER 1993 ...

Page 2: ... the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an ou...

Page 3: ...efect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific appl...

Page 4: ...mnemonic of an instruction Use APPENDIX D INSTRUCTION LIST To look up an instruction when you do not know its mnemonic but know outlines of the function Refer to 18 3 LIST OF THE INSTRUCTION SET for search for the mnemonic of the instruction then see 18 5 INSTRUCTIONS for the function To look up electrical characteristics of the µPD17120 subseries Refer to DATA SHEET Legend Data representation wei...

Page 5: ...IE 17K ET CLICE ET Ver 1 6 EEU 931 EEU 1466 User s manual SE board User s manual SIMPLEHOSTTM EEU 723 EEU 1336 Introduction User s manual EEU 724 EEU 1337 Reference AS17K Ver 1 11 User s manual Device file User s manual Remark The numbers inside indicate English document number The µPD17120 subseries has different pin names and signal names depending on the system clock type as shown in the table ...

Page 6: ...2 Program Counter during Execution of the Branch Instruction BR 20 3 2 3 Program Counter during Execution of Subroutine Calls CALL 21 3 2 4 Program Counter during Execution of Return Instructions RET RETSK RETI 22 3 2 5 Program Counter during Table Reference MOVT 22 3 2 6 Program Counter during Execution of Skip Instructions SKE SKGE SKLT SKNE SKT SKF 22 3 2 7 Program Counter When an Interrupt Is ...

Page 7: ...7 3 2 Window Register Functions 45 7 4 BANK REGISTER BANK 46 7 5 INDEX REGISTER IX AND DATA MEMORY ROW ADDRESS POINTER Memory Pointer MP 47 7 5 1 Index Register IX 47 7 5 2 Data Memory Row Address Pointer Memory Pointer MP 47 7 5 3 MPE 0 and IXE 0 No Data Memory Modification 50 7 5 4 MPE 1 and IXE 0 Diagonal Indirect Data Transfer 52 7 5 5 MPE 0 and IXE 1 Index Modification 54 7 6 GENERAL REGISTER...

Page 8: ...FER 80 10 2 1 Data Buffer and Peripheral Hardware 81 10 2 2 Data Transfer with Peripheral Hardware 82 10 2 3 Table Reference 83 CHAPTER 11 ARITHMETIC AND LOGIC UNIT 85 11 1 ALU BLOCK CONFIGURATION 85 11 2 FUNCTIONS OF THE ALU BLOCK 85 11 2 1 Functions of the ALU 85 11 2 2 Functions of Temporary Registers A and B 90 11 2 3 Functions of the Status Flip flop 90 11 2 4 Performing Operations in 4 Bit B...

Page 9: ...t Output Switching by Group I O 113 12 7 2 Input Output Switching by Bit I O 114 CHAPTER 13 PERIPHERAL HARDWARE 117 13 1 8 BIT TIMER COUNTER TM 117 13 1 1 8 Bit Timer Counter Configuration 117 13 1 2 8 bit Timer Counter Control Register 119 13 1 3 Operation of 8 bit Timer Counters 120 13 1 4 Selecting Count Pulse 120 13 1 5 Setting a Count Value in Modulo Register and Calculation Method 121 13 1 6...

Page 10: ...Address after STOP Mode Cancellation 167 15 3 3 STOP Setting Condition 169 CHAPTER 16 RESET 171 16 1 RESET FUNCTIONS 171 16 2 RESETTING 172 16 3 POWER ON POWER DOWN RESET FUNCTION 173 16 3 1 Conditions Required to Enable the Power On Reset Function 173 16 3 2 Description and Operation of the Power On Reset Function 174 16 3 3 Condition Required for Use of the Power Down Reset Function 176 16 3 4 D...

Page 11: ...7 18 5 11 Other Instructions 249 CHAPTER 19 ASSEMBLER RESERVED WORDS 251 19 1 MASK OPTION PSEUDO INSTRUCTIONS 251 19 1 1 OPTION and ENDOP Pseudo Instructions 251 19 1 2 Mask Option Definition Pseudo Instructions 252 19 2 RESERVED SYMBOLS 254 19 2 1 List of Reserved Symbols µPD17120 17121 254 19 2 2 List of Reserved Symbols µPD17132 17133 17P132 17P133 260 APPENDIX A DEVELOPMENT TOOLS 267 APPENDIX ...

Page 12: ...on 43 7 4 Address Register Used as a Peripheral Register 44 7 5 Window Register Configuration 45 7 6 Bank Register Configuration 46 7 7 Index Register and Memory Pointer Configuration 48 7 8 Data Memory Address Modification by Index Register and Memory Pointer 48 7 9 Example of Operation When MPE 0 and IXE 0 51 7 10 Example of Operation When MPE 1 and IXE 0 53 7 11 Example of Operation When MPE 0 ...

Page 13: ...3 15 Serial Interface Control Register 139 13 16 Setting a Value in the Shift Register 141 13 17 Reading a Value from the Shift Register 142 14 1 Interrupt Control Register 148 14 2 Interrupt Handling Procedure 153 14 3 Return from Interrupt Handling 154 14 4 Interrupt Acceptance Timing Chart when INTE 1 and IP 1 155 15 1 Cancellation of HALT Mode 164 15 2 Cancellation of STOP Mode 168 16 1 Reset ...

Page 14: ... and Reading from the Port Register 0 71H 106 12 3 Writing reading to from Port Register 0 72H µPD17120 17121 107 12 4 Writing into and Reading from the Port Register 0 72H and Pin Function Selection 108 12 5 Register File Contents and Pin Functions 110 12 6 Contents Read from the Port Register 0 73H 110 12 7 Writing into and Reading from the Port Registers 0 6FH 0 0 6FH 1 111 13 1 Timer Resolutio...

Page 15: ... x MEMO ...

Page 16: ... the µPD17120 subseries Comparator input µPD17132 17133 17P132 17P133 only Comparison function with external reference voltage Vref Canbeusedas4 bitA Dconverterbyusing15typesofinternalreferencevoltage 1 16to15 16VDD depending on the software 3 wire serial interface 1 channel Power on power down reset circuit reducing external circuits µPD17P132 and 17P133 can operate in the same way as mask ROM ve...

Page 17: ...lation Instruction Execution Time 8 µs when fCC 2 MHz 2 µs when fX 8 MHz Standby Function HALT STOP Power on Power down Incorporated Incorporated Reset Circuit Can be used on an applied circuit Can be used on an applied circuit of VDD 5 V 10 of VDD 5 V 10 fX 400 kHz to 4 MHz 2 7 to 5 5 V 4 5 to 5 5 V When using the power on power down reset function 24 pin plastic shrink DIP 300 mil 24 pin plastic...

Page 18: ...75 mil Mask ROM µPD17132CS 24 pin plastic shrink DIP 300 mil Mask ROM µPD17132GT 24 pin plastic SOP 375 mil Mask ROM µPD17133CS 24 pin plastic shrink DIP 300 mil Mask ROM µPD17133GT 24 pin plastic SOP 375 mil Mask ROM µPD17P132CS 24 pin plastic shrink DIP 300 mil One time PROM µPD17P132GT 24 pin plastic SOP 375 mil One time PROM µPD17P133CS 24 pin plastic shrink DIP 300 mil One time PROM µPD17P133...

Page 19: ...pecified using a mask option P0B0 P0B1 P0B2 P0B3 P0B CMOS P0A0 P0A1 P0A2 P0A3 P0A CMOS P0C0 P0C1 P0C2 P0C3 P0C CMOS P0E0 P0E1 P0E N ch ALU Instruction Decoder ROM 768 16 bits Program Counter Stack 5 10 bits Interrupt Controller Timer IRQTM IRQSIO fX 2N Clock Divider System Clock Generator XIN XOUT P0D0 SCK P0D1 SO P0D2 SI P0D3 TMOUT INT fX 2N CPU CLK CLK STOP VDD Power On Power Down Reset RESET GN...

Page 20: ...m memory write verify mode of the µPD17P132 and µPD17P133 P0B0 P0B1 P0B2 P0B3 P0B CMOS P0A0 P0A1 P0A2 P0A3 P0A CMOS P0C0 Cin0 P0C1 Cin1 P0C2 Cin2 P0C3 Cin3 P0C CMOS Compa rator ALU Instruction Decoder ROM 1024 16 bits Program Counter Stack 5 10 bits Interrupt Controller Timer IRQTM IRQSIO fX 2N Clock Divider System Clock Generator XIN CLK Note XOUT P0D0 SCK P0D1 SO P0D2 SI P0D3 TMOUT INT VPP Note ...

Page 21: ...D17120 and 17121 GND XIN XOUT RESET P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 VDD P0E1 Vref Note 1 P0E0 P0D3 TMOUT P0D2 SI P0D1 SO P0D0 SCK INT P0C3 Cin3 Note 2 P0C2 Cin2 Note 2 P0C1 Cin1 Note 2 P0C0 Cin0 Note 2 µ PD17120CS PD17120GT PD17121CS PD17121GT PD17132CS PD17132GT PD17133CS PD17133GT PD17P132CS PD17P132GT PD17P133CS PD17P133GT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 µ...

Page 22: ...xternal interrupt input MD0 to MD3 Operating mode selection P0A0 to P0A3 Port 0A P0B0 to P0B3 Port 0B P0C0 to P0C3 Port 0C P0D0 to P0D3 Port 0D P0E0 to P0E3 Port 0E RESET Reset input SCK Serial clock input output SI Serial data input SO Serial data output TMOUT Timer output VDD Power supply VPP Programming voltage supply Vref External reference voltage XIN XOUT System clock oscillation GND CLK Ope...

Page 23: ... MEMO 8 ...

Page 24: ...t Pull up resistor can be incorporated by mask optionNote 5 P0A0 Port 0A CMOS Input 4 bit I O port Push pull 8 P0A3 Input output can be set by each bit 9 P0B0 Port 0B CMOS Input 4 bit I O port Push pull 12 P0B3 Input output can be set by 4 bit unit 13 P0C0 Cin0 Port 0C and analog voltage input of comparator CMOS Input P0C0 to P0C3 Push pull P0C 16 P0C3 Cin3 4 bit I O port Input output can be set b...

Page 25: ...SCK Serial clock input output 19 P0D1 SO SO Serial data output 20 P0D2 SI SI Serial data input 21 P0D3 TMOUT TMOUT Output of timer 22 P0E0 Port 0E and reference voltage input of comparator N ch Input 23 P0E1 Vref P0E0 P0E1 open drain P0E 2 bit I O port Input output can be set by each bit Pull up resistor can be incorporated per bit by mask optionNote Vref µPD17132 17133 17P132 17P133 only External...

Page 26: ... program memory writing verifying Input 5 MD0 Input for selecting operation mode in program memory writing verifying Input 8 MD3 9 D0 8 bit data input output in program memory writing verifying Input Output 12 D7 17 VPP Pin for applying programming voltage in program memory writing verifying Apply 12 5 V 24 VDD Positive power supply Apply 6 V in program memory writing verifying ...

Page 27: ...NS 12 2 2 PIN INPUT OUTPUT CIRCUIT Below are simplified diagrams of the input output circuits for each pin of the µPD17120 subseries 1 P0A0 P0A3 P0B0 P0B3 Data Output disable Selector P ch N ch VDD Input buffer Output latch ...

Page 28: ...N FUNCTIONS 13 2 P0C0 Cin0 P0C3 Cin3 Note Note Pins Cin0 to Cin3 are not included in the µPD17120 and 17121 Data Output disable Selector P ch N ch VDD Input buffer Output latch Input disable Analog comparator input ...

Page 29: ...istor by mask option and are always open 4 P0E0 Note The µPD17P132 and 17P133 have no pull up resistor by mask option and are always open Data Output disable Selector N ch VDD Input buffer Output latch Mask option Note Data Output disable N ch VDD Input buffer Output latch Mask option Note ...

Page 30: ...The µPD17120 and 17121 have no Vref pin function 2 The µPD17P132 and 17P133 have no pull up resistor by mask option and are always open 6 INT Data Vref enable N ch VDD Output latch Mask option Note 2 Selector Input buffer Vref Output disable Input buffer ...

Page 31: ...CHAPTER 2 PIN FUNCTIONS 16 7 RESET Note The µPD17P132 and 17P133 have no pull up resistor by mask option and are always open Input buffer VDD Mask option Note ...

Page 32: ...mption When pulling up or pulling down at a high resistance value be careful to ensure that no noise is caused in the relevant pin Although it depends on the applied circuit as well it is usual to choose several tens of kΩ as the resistance value for pull up or pull down 2 The INT pin is for the test mode setting function as well connect it directly to the GND when unused 3 If the applied circuit ...

Page 33: ...eeding VDD even in normal operation may result in placing the pin in test mode thus impeding normal operation For example if the RESET or INT pin wires are laid out too long wiring noise is added to these pins thus causing the above problem Therefore make sure that the wires are laid down in such a manner that such inter wire noises are suppressed as much as possible If noise is still a problem ta...

Page 34: ...er 3 2 PROGRAM COUNTER OPERATION Normally the program counter is automatically incremented each time a command is executed The memory address at which the next instruction to be executed is stored is assigned to the program counter under the following conditions At reset when a branch subroutine call return or table referencing instruction is executed or when an interrupt is received Sections 3 2 ...

Page 35: ...nted to the stack pointer return address MSB 0 All bits are set to 0 0 0 0 0 0 0 0 0 0 LSB 3 2 2 Program Counter during Execution of the Branch Instruction BR There are two ways to specify branching using the branch instruction One is to specify the branch address in the operand using the direct branch instruction BR addr The other is to branch to the address specified by the address register usin...

Page 36: ...utine call causes the value in the program counter to be saved in the stack and then the address specified in the operand to be placed in the program counter Direct subroutine calls can specify any address in program memory Figure 3 6 Value in the Program Counter during Execution of a Direct Subroutine Call An indirect subroutine call causes the value in the program counter to be saved in the stac...

Page 37: ... a no operation instruction NOP Therefore whether skip conditions are met or not the number of instructions executed and instruction execution time remain the same 3 2 7 Program Counter When an Interrupt Is Received When an interrupt is received the value in the program counter is saved in the address stack Next the vector address for the interrupt received is placed in the program counter 3 3 CAU...

Page 38: ...memory map Branch instructions subroutine calls and table references can specify any address in program memory 0000H 07FFH Figure 4 1 Program Memory Map for the µPD17120 Subseries 1 5K bytes 768 16 bits 0000H 02FFH 2K bytes 1024 16 bits 0000H 03FFH Reset start address Serial interface interrupt vector Timer interrupt vector External INT interrupt vector PD17120 17121 PD17132 17133 17P132 17P133 µ ...

Page 39: ...e However if for some reason a different kind of program is to be executed it will be necessary to change the flow of the program In this case the branch instruction BR instruction is used If the same section of program code is going to appear in a number of places reproducing the code each time it needs to be used will decrease the efficiency of the program In this case this section of program co...

Page 40: ... in the assembler A direct branch instruction can be used to branch to any address in program memory 3 Indirect branch When executing an indirect branch BR AR the program branches to the address specified by the value stored in the address register AR An indirect branch can be used to branch to any address in program memory Also refer to 7 2 ADDRESS REGISTER AR 4 Direct subroutine call When using ...

Page 41: ... Note The last address of the program memory of the µPD17120 and µPD17121 is 02FFH 5 Indirect subroutine call When using an indirect subroutine call CALL AR the value in the address register AR should be an address of the called subroutine This instruction can be used to call any address in program memory Also refer to 7 2 ADDRESS REGISTER AR ...

Page 42: ...can be used to table reference any location in program memory Caution Note that one level of the stack is temporarily used when performing table reference Also refer to 7 2 ADDRESS REGISTER AR and CHAPTER 10 DATA BUFFER DBF Remark As an exception execution of table reference instructions requires two instruction cycle Figure 4 3 Table Reference MOVT DBF AR b3 b2 b1 b0 DBF3 b3 b2 b1 b0 DBF2 b3 b2 b...

Page 43: ...fy that MOV RPL 7 SHL 1 operation results be stored in row address 7 ROMREF BANK0 Stores the start address of the constant data table in the address register AR MOV AR3 DL TABLE SHR 12 AND 0FH MOV AR2 DL TABLE SHR 8 AND 0FH MOV AR1 DL TABLE SHR 4 AND 0FH MOV AR0 DL TABLE AND 0FH ADD AR0 OFFSET Adds the offset address ADDC AR1 0 ADDC AR2 0 ADDC AR3 0 MOVT DBF AR Executes the table reference instruc...

Page 44: ... RPH 0 Sets the register pointer to row MOV RPL 7 SHL 1 address 7 ROMREF BANK0 Stores the start address of the constant data table in the address register AR MOV AR3 DL TABLE SHR 12 AND 0FH MOV AR2 DL TABLE SHR 8 AND 0FH MOV AR1 DL TABLE SHR 4 AND 0FH MOV AR0 DL TABLE AND 0FH ADD AR0 OFFSET Adds the offset address ADDC AR1 0 MOVT DBF AR Executes the table reference instruction PUT AR DBF BR AR TAB...

Page 45: ... MEMO 30 ...

Page 46: ...er bits are called the row address and the four low order bits are called the column address For example when the address of data memory is 1AH 0011010B the row address is 1H 001B and the column address is AH 1010B In the case of the µPD17120 and 17121 addresses 40H to 6EH should not be used because they are non mounted areas Sections 5 1 1 to 5 1 6 describe functions of data memory other than its...

Page 47: ...nk register BANK General register pointer RP Program status word PSWORD 5 1 2 Data Buffer DBF The data buffer consists of four nibbles allocated at addresses 0CH to 0FH in BANK0 of data memory Figure 5 3 shows the configuration of the data buffer Figure 5 3 Data Buffer Configuration Data Buffer DBF Address 0CH 0DH 0EH 0FH Symbol DBF3 DBF2 DBF1 DBF0 5 1 3 General Register GR The general register co...

Page 48: ...rs SYSREG In other words general data memory consists of 64 nibbles µPD17120 and 17121 or 111 nibbles µPD17132 17133 17P132 and 17P133 5 1 6 Uninstalled Data Memory There is no hardware installed at addresses 40H to 6EH of the µPD17120 and 17121 Any attempt to read this area will yield unpredictable results Writing data to this area is invalid and should therefore not be attempted Figure 5 4 Gener...

Page 49: ... MEMO 34 ...

Page 50: ...Stack Register ASR b8 b7 b6 b5 b4 b3 b2 b1 b0 b10 Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4 0H 1H 2H 3H 4H b2 SPb2 b1 SPb1 b0 SPb0 Stack Pointer SP BCDSK Interrupt Stack Register INTSK CMPSK CYSK ZSK IXESK 0H 6 2 FUNCTIONS OF THE STACK The stack is used to save the return address during execution of subroutine calls...

Page 51: ...s shown in Figure 6 1 the interrupt stack register consists of one 5 bit register When an interrupt is received five bits in the system register SYSREG mentioned later that is each flag BCD CMP CY Z IXE of the program status word PSWORD are saved When the interrupt return RETI is executed the program status word is restored from the interrupt stack register In the interrupt stack register every ti...

Page 52: ...ll cause an internal reset signal to be generated to prevent a software crash Since the stack pointer is located in the register file it can be read and written to directly by using the PEEK and POKE instructions to manipulate the register file When this is done the stack pointer value will change but the values in the address stack register will not be affected 6 6 STACK OPERATION DURING SUBROUTI...

Page 53: ...OP 6 6 2 Stack Operation during Table Reference MOVT DBF AR Table 6 3 shows stack operation during table reference Table 6 3 Stack Operation during Table Reference Instruction Instruction Cycle Operation MOVT DBF AR First 1 Stack pointer SP is decremented 2 Program counter PC is saved in the address stack register pointed to by the stack pointer SP 3 Value in the address register AR is transferred...

Page 54: ... of operations such as subroutine calls and returns the stack pointer SP simply functions as a 3 bit counter which is incremented and decremented When the value in the stack pointer is 0H and a CALL or MOVT instruction is executed or an interrupt is received the stack pointer is decremented to 7H The µPD17120 subseries treats this condition as a fault and generates an internal reset signal In orde...

Page 55: ... MEMO 40 ...

Page 56: ...d in addresses 74H to 7FH of data memory Because the system register is allocated in data memory it can be manipulated using any of the instructions available for manipulating data memory Therefore it is also possible to put the system register in the general register Figure 7 1 Allocation of System Register in Data Memory 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Column address Data memory ...

Page 57: ...77H 75H 76H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH b3 b2 b1 b0 AR3 0 0 0 0 b3 b2 b1 b0 AR2 0 0 0 0 b3 b2 b1 b0 AR1 0 0 0 0 b3 b2 b1 b0 AR0 0 0 0 0 b3 b2 b1 b0 WR b3 b2 b1 b0 BANK 0 0 0 0 b3 b2 b1 b0 IXH MPH 0 0 0 0 b3 b2 b1 b0 IXM MPL 0 0 0 0 b3 b2 b1 b0 IXL 0 0 0 0 b3 b2 b1 b0 RPH 0 0 0 0 b3 b2 b1 b0 RPL 0 0 0 0 b3 b2 b1 b0 PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M P E 0 0 0 0 0 0 0 0 B C D C M P C Y Z I X E Na...

Page 58: ... b1 b0 0 0 0 0 0 0 0 0 0 0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 7 2 2 Address Register Functions The address register is used to specify an address in program memory when executing an indirect branch instruction BR AR indirect subroutine call CALL AR or table reference MOVT DBF AR The address register can also be put on and taken off the stack by using the stack manipulation instructions PUSH AR PO...

Page 59: ...uted the subroutine located at the address in program memory specified by the value in the address register is called 5 Address register used as peripheral register The address register can be manipulated four bits at a time by using data memory manipulation instructions The address register can also be used as a peripheral register for transferring 16 bit data to the data buffer In other words by...

Page 60: ...er when RESET input is used to release the system from HALT or STOP mode the previous state of the window register is maintained Figure 7 5 Window Register Configuration 7 3 2 Window Register Functions The window register is used to transfer data to and from the register file RF Data is transferred to and from the register file using the instructions PEEK WR rf and POKE rf WR For details refer to ...

Page 61: ...four bits at address 79H BANK of the system register Bank register is a register for switching the banks of RAM However since the µPD17120 subseries has only one bank every bank register bit is fixed to 0 Figure 7 6 Bank Register Configuration 79H Bank register Address Name Bit Symbol Data Initial value when reset b3 b2 b1 b0 0 0 0 0 0 BANK BANK ...

Page 62: ...nter Memory Pointer MP MP is used for address modification to data memory It differs from IX in that its modification object is the row address of the address that is indirectly specified with the bank and operand r As shown in Figure 7 7 MPH and IXH and MPL and IXM are respectively mapped to the same addresses system registers 7AH and 7BH It is MPH s lower 3 bits and MPL s full 7 bits that are ac...

Page 63: ...mC Contents addressed with mR Data memory row address Direct address such as r mC Data memory column address 7AH Address Name Bit Symbol name Data Reset time value b3 b2 b1 b0 b3 b2 b1 b2 b1 b1 b0 b0 Index register IX Memory pointer MP IXH MPH IXM MPL IXL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IX MP Flag name M P E 7BH 7CH b1 b2 b3 0 0 0 0 7FH PSW I X E 0 Program status word PSWORD S lower 4 bits b3 Data M...

Page 64: ...9 Table 7 1 Address modified Instruction Statements ADD ADDC SUB SUBC AND OR r m XOR m n4 SKT SKF SKE SKGE SKLT SKNE LD r m ST m r MOV m n4 r m m r r m m n4 m n m n4 Arithmetic operation Logical operation Judge ment Comparison Transfer ...

Page 65: ...indirect transfer Example 2 General register is in row address 0 R005 MEM 0 05H M034 MEM 0 34H MOV R005 8 R005 8 MOV R005 M034 Indirect transfer of data in the register As shown in Figure 7 9 when the above instructions are executed the data stored in data memory address M034 is transferred to data memory location 38H In other words the MOV r m instruction causes the contents in the data memory ad...

Page 66: ...specified by r example above uses column address 0EH Therefore the address in the above example is 3EH The data transfer memory address source and destination in this example are the opposite of those shown in Example 2 source and destination are switched Figure 7 9 Example of Operation When MPE 0 and IXE 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F System register General register 8 E Row ad...

Page 67: ...is executed when MPE 1 the contents of the data memory address specified by m is transferred to the column address pointed to by the row address r being pointed to by the memory pointer In this case the indirect address specified by r becomes the value used for the bank and row address data memory pointer above example uses row address 6 The column address is the value in the general register addr...

Page 68: ...ress Example 1 MOV R005 M034 Column address specified as transfer destination Column address specified as transfer source Column address 1 2 3 4 5 6 7 8 9 A B C D E F 8 E General register Memory pointer 00110B Example 2 MOV M034 R00B Data memory address M General register address R Indirect transfer address R 0000 0000 0000 011 000 110 0100 0101 1000 Column Address Row Address Bank Contents of R A...

Page 69: ...03H M061 MEM 0 61H MOV IXL 0010B IX 00000010010B MOV IXM 0001B MOV IXH 0000B MPE 0 OR PSW DF IXE AND 0FH IXE 1 ADD R003 M061 As shown in Figure 7 11 when the instructions of Example 1 are executed the value in data memory address 73H real address and the value in general register address R003 address location 03H are added together and the result is stored in general register address R003 When the...

Page 70: ... 8 9 A B C D E F R003 General register Data memory address M General register address R Index modification 0000 0000 0000 BANK 0000 IXH 0000 110 000 110 001 IXM 111 0001 0011 0001 0010 IXL 0011 Column Address Row Address Bank Addresses in Example 1 ADD R003 M061 M061 00001100001B IX 00000010010B OR Real address 00001110011B M061 M061 IX Real address OR operation m Instruction is executed using thi...

Page 71: ...ng the contents of the index register The bank and row address of the indirect address specified by r are also modified using the index register The bank row address and column address specified by m direct address are all modified and the bank and row address specified by r indirect address are modified Therefore in the above example the direct address is 35H and the indirect address is 38H This ...

Page 72: ... Real address 00000110101B M034 8 Indirect address Column address specified as transfer destination Direct address R005 Example 3 Clearing all data memory setting to 0 M000 MEM 0 00H MOV IXL 0 IX 0 MOV IXM 0 MOV IXH 0 MPE 0 LOOP OR PSW DF IXE AND 0FH IXE 1 MOV M000 0 Set data memory specified by IX to 0 INC IX IX IX 1 AND PSW 1110B IXE 0 IXE is set to 0 so that address 7FH is not modified by IX SK...

Page 73: ...ess MOV IXL N SHL 1 AND 0FH Set the offset of the column address OR PSW DF IXE AND 0FH IXE 1 ADD M000 4 ADDC M001 0 A N A N 4 In the example above because an element is 8 bits the value resulting from left shifting the N s value by 1 bit is set for the index register Figure 7 13 Example of Operation When MPE 0 and IXE 1 Array Processing 0 1 2 3 4 5 6 7 0 System register Row address Column address ...

Page 74: ...r pointer consists of seven bits four bits in system register address 7DH RPH and the three high order bits of system register address 7EH RPL However because the four bits of address 7DH are always set to 0 the register effectively consists of the three high order bits of address 7EH All register bits are cleared to 0 at reset 7DH Address Name Bit Symbol Data Initial value when reset b3 b2 b1 b0 ...

Page 75: ...ions can be performed on the general register and data memory Note that addresses 40H to 6EH are uninstalled memory locations and should therefore not be specified as locations for the general register For example when instructions such as ADD r m and LD r m are executed instruction operand r can specify an address in the general register and m specifies an address in data memory In this way opera...

Page 76: ...tus word PSWORD b3 b2 b1 b0 I X E 0 PSW Data Z C Y C M P B C D RP As shown in Figure 7 16 the program status word consists of five bits the least significant bit of system register address 7EH RPL and all four bits of system register address 7FH PSW The program status word is divided into the following 1 bit flags Binary coded decimal flag BCD compare flag CMP carry flag CY zero flag Z and the ind...

Page 77: ...odification enabled Set when the result of an arithmetic operation is 0 0 Indicates that the result of the arithmetic operation is a value other than 0 1 Indicates that the result of the arithmetic operation is 0 Set when there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation 0 Indicates there was no carry or borrow 1 Indicates there was a carr...

Page 78: ...ag affects the setting and resetting of the Z flag Table 7 2 Zero Flag Z and Compare Flag CMP Condition When CMP 0 When CMP 1 When the result of the arithmatical operation is 0 Z 1 Z remains unchanged When the result of the arithmetic operation is other than 0 Z 0 Z 0 The Z and CMP flags are used to compare the contents of the general register with those of the data memory The Z flag does not chan...

Page 79: ...y arithmetic operations and rotations Also it is not affected by CMP flag 7 7 6 Binary Coded Decimal Flag BCD The BCD flag is used to specify BCD operations When the BCD flag is set BCD 1 all arithmetic operations will be performed in BCD When the BCD flag is reset BCD 0 arithmetic operations are performed in 4 bit binary The BCD flag does not affect logical operations bit evaluation comparison ev...

Page 80: ...located in address locations 74H to 7FH They are defined by the symbols AR3 AR2 PSW shown in Figure 7 2 As shown in Example 2 if these reserved words are used it is not necessary to define symbols For information concerning reserved words refer to CHAPTER 19 ASSEMBLER RESERVED WORDS Example 1 MOV 34H 0101B Using a data memory address like 34H or 76H will MOV 76H 1010B cause an error in the assembl...

Page 81: ...corporated macro instructions can be used as shown in Example 4 Example 3 F0003 FLG 0 00 3 Flag symbol definition SET1 F0003 Incorporated macro Expanded macro OR MF F0003 SHR 4 DF F0003 AND 0FH Set bit 3 of address 00H of BANK0 Example 4 SET1 BCD Incorporated macro Expanded macro OR MF BCD SHR 4 DF BCD AND 0FH Set the BCD flag BCD is defined as BCD FLG 0 7EH 0 CLR2 Z CY Identical address flag Expa...

Page 82: ... to write the value 1 to an address fixed at 0 Below is an example of the type of instructions that will cause the in circuit emulator to generate an error Example 1 MOV BAMK 0100B Attempts to write the value 1 to bit 3 an address fixed at 0 2 MOV IXL 1111B MOV IXM 1111B MOV IXH 0001B ADD IXL 1 ADDC IXM 0 ADDC IXH 0 However when all valid bits are set to 1 as shown in Example 2 executing the instr...

Page 83: ...is generated The assembler AS17K does not generate errors because it does not check the correspondence between the symbol including reserved words and the data memory address which are the objects of the data memory operation instruction However in the following case the assembler generates an error When a value of 1 or more is given to n in the incorporation macro instruction BANKn This is so bec...

Page 84: ...h the general register can be allocated are address locations 0H to 7H However note that addresses 40H to 6EH are uninstalled memory locations and should therefore not be specified as locations for the general register 8 2 FUNCTIONS OF THE GENERAL REGISTER The general register can be used in transferring data to and from data memory within an instruction It can also be used in performing arithmeti...

Page 85: ...ster 16 nibbles System register BANK0 General register when RPH 0000B RPL 010 B 7DH Address Name Bits Symbol Data b3 b2 b1 b0 0 b3 b2 b1 b0 7EH B C D RPH RPL General register pointer RP 0 0 0 0 0 0 Reset 0 0 0 0 Row address The general register pointer RP can be used to specify any row address in address locations 0H to 7H Column address ...

Page 86: ... has a total of 128 nibbles specified in row addresses from 0H to 7H and column address from 0H to 0FH Address locations 00H to 3FH define an area the control register Figure 9 1 Register File Configuration 0 1 2 3 4 5 6 7 General register 0 Row address Column address 1 2 3 4 5 6 7 8 9 A B C D E F 9 1 2 Relationship between the Register File and Data Memory Figure 9 2 shows the relationship betwee...

Page 87: ...allocated within the register file at address location 00H to 3FH The rest of the register file 40H to 7FH overlaps with data memory As shown in 9 2 3 because of this overlap this area of the register file is the same as normal memory with one exception The register file manipulation instructions PEEK and POKE can be used with this area of memory but not with normal data memory 9 2 2 Control Regis...

Page 88: ...of WR M032 MEM 0 32H Address 32H of the data memory is used as operation area of WR RF11 MEM 0 91H Symbol definition RF33 MEM 0 B3H Register file addresses 00H to 3FH must be defined with RF70 MEM 0 70H symbols as BANK0 address 80H to BFH RF73 MEM 0 73H Refer to 9 4 NOTES ON USING THE REGISTER FILE for details BANK0 1 PEEK WR RF11 CLR1 MPE Shows the example of saving WR contents to the general dat...

Page 89: ...7FH has the following effect When a PEEK WR rf or POKE rf WR instruction is executed the effect is the same as if they were being executed on the data memory address in the current bank specified by rf Addresses 40H to 7FH of the register file can be operated by normal memory manipulation instructions Control registers can be manipulated in 1 bit unit by using built in macro instruction Figure 9 3...

Page 90: ...ter address area will yield unpredictable values In addition attempting to write to this area has no effect Concerning the configuration of control register refer to Figures 19 1 and 19 2 9 4 CAUTIONS ON USING THE REGISTER FILE 9 4 1 Concerning Operation of the Control Register Read Only and Unused Registers It is necessary to take note of the following notes concerning device operation and use of...

Page 91: ...ch causes and error to be generated PEEK WR 02H POKE 21H WR Case in which no error is generated RF71 MEM 0 71H Symbol definition PEEK WR RF71 Caution should especially be taken with regard to the following point When using a symbol to define the control register as an address in data memory it needs to be defined as addresses 80H to BFH of BANK0 Since the control register is manipulated using the ...

Page 92: ...d macro instructions the contents of the register file can be manipulated one bit at a time Due to the fact that most of control register consists of 1 bit flags the assembler AS17K has reserved words predefined symbols for use with these flags However note that there is no reserved word for the stack pointer for its use as a flag The reserved word used for the stack pointer is SP for its use as d...

Page 93: ... MEMO 78 ...

Page 94: ...IGURATION Figure 10 1 shows the allocation of the data buffer in data memory As shown in Figure 10 1 the data buffer is allocated in address locations 0CH to 0FH in BANK0 and consists of a total of 16 bits 4 4 bits Figure 10 1 Allocation of the Data Buffer 0 1 2 3 4 5 6 7 0 BANK0 Column address 1 2 3 4 5 6 7 8 9 A B C D E F Data memory Data buffer DBF System register SYSREG Row address Figure 10 2...

Page 95: ...tructions 10 2 FUNCTIONS OF THE DATA BUFFER The data buffer has two separate functions The data buffer is used for data transfer with peripheral hardware The data buffer is also used for reading constant data in program memory Figure 10 3 shows the relationship between the data buffer and peripheral hardware Figure 10 3 Relationship Between the Data Buffer and Peripheral Hardware 01H Shift registe...

Page 96: ...T GET write only PUT and read only GET The following describes what happens when a GET instruction is used with write only hardware PUT only and when a PUT instruction is used with read only hardware GET only Reading GET from write only PUT only peripheral hardware will yield an unpredictable value Writing PUT to read only GET only peripheral hardware has no effect regarded as a NOP instruction Ta...

Page 97: ...Data in peripheral hardware b4 b5 b6 b7 DBF2 Don t care DBF3 Don t care b0 Effective bits b7 PUT DBF1 Data buffer When only eight bits of data are being written from the data buffer the upper eight bits of the data buffer DBF3 DBF2 are irrelevant Example 2 GET instruction when the effective bits in peripheral hardware are the 8 bits from 7 to 0 When only eight bits of data are being read into the ...

Page 98: ... in program memory ROM can be read into the data buffer The MOVT instruction is explained below MOVT DBF AR The contents of the program memory being pointed to by the address register AR is read into the data buffer DBF DBF3 DBF2 DBF1 DBF0 16 bits Date buffer MOVT DBF AR Program memory ROM b15 b0 ...

Page 99: ... MEMO 84 ...

Page 100: ... 1 lists each arithmetic logical instruction evaluation instruction and rotation instruction By using the instructions listed in Table 11 1 4 bit arithmetic logical operations evaluations and rotations can be performed in a single instruction Arithmetic operations in decimal can also be performed in a single instruction 11 2 1 Functions of the ALU The arithmetic operations consists of addition and...

Page 101: ... version circuit 7EH 7FH Program status word PSWORD b0 BCD b3 CMP b2 CY b1 Z b0 IXE Status flip flop CMP flag FF CY flag FF Z flag FF BCD flag FF Function outline Indicates when the result of an arithmetic operation is 0 Stores the borrow or carry from an arithmetic operation Used to indicate whether to store the result of an arithmetic operation Used to indicate whether to perform decimal correct...

Page 102: ...CHAPTER 11 ARITHMETIC AND LOGIC UNIT 87 MEMO ...

Page 103: ...ry Result is stored in general register AND m n4 m m n4 AND operation is performed on immediate data and contents of data memory Result is stored in data memory XOR r m r r m XOR operation is performed on contents of general register and data memory Result is stored in general register XOR m n4 m m n4 XOR operation is performed on immediate data and contents of data memory Result is stored in data...

Page 104: ...d Held Don t care Don t care Don t care Held Held Held Table 11 1 List of ALU Instructions 2 2 ALU Function Operational Variance Depending on Program Status Word PSWORD CY flag Z flag BCD flag s value CMP flag s value Operating action Modifica tion by IXE 1 The binary operation result is stored The BCD operation result is stored The binary operation result is not stored The BCD operation result is...

Page 105: ...ion is 0000B otherwise it is reset 0 However as described below depending on the status of the CMP flag the conditions which cause this flag to be set 1 can be changed i When CMP 0 Z flag is set 1 when the result of an arithmetic operation is 0000B otherwise it is reset 0 ii When CMP 1 The previous state of the Z flag is maintained when the result of an arithmetic operation is 0000B otherwise it i...

Page 106: ...hrough direct manipulation of the values in the program status word When the flags in the program status word are manipulated the corresponding flag in the status flip flop is also manipulated 11 2 4 Performing Operations in 4 Bit Binary When the BCD flag is set to 0 arithmetic operations are performed in 4 bit binary 11 2 5 Performing Operations in BCD When the BCD flag is set to 1 decimal correc...

Page 107: ...7 1 1011 1 1101 28 1 1100 1 1010 29 1 1101 1 1011 30 1 1110 1 1100 31 1 1111 1 1101 Table 11 2 Results of Arithmetic Operations Performed in 4 Bit Binary and BCD Operation Result Subtraction in 4 bit Binary Subtraction in BCD Operation Result CY Operation Result CY 0 0 0000 0 0000 1 0 0001 0 0001 2 0 0010 0 0010 3 0 0011 0 0011 4 0 0100 0 0100 5 0 0101 0 0101 6 0 0110 0 0110 7 0 0111 0 0111 8 0 10...

Page 108: ...dress in data memory In the instruction ADD m n4 the first data operand m is used to specify an address in data memory The second operand n4 is immediate data In the rotation instruction RORC r only the first data operand r used to specify the contents of an address in the general register is used Next using the data stored in temporary registers A and B the ALU executes the operation specified by...

Page 109: ...d addition and subtraction of data memory and immediate data When the operands r and m are used addition or subtraction is performed using the general register and data memory When the operands m and n4 are used addition or subtraction is performed using data memory and immediate data Arithmetic operations are affected by the status flip flop and the program status word PSWORD in the system regist...

Page 110: ... operations are performed The result of the operation is stored in the general register or data memory When the result of the operation is greater than 1001B 9D or less than 0000B 0D the carry flag is set 1 otherwise it is reset 0 When the result of the operation is 0000B 0D the Z flag is set 1 otherwise it is reset 0 Operations in BCD are performed by first computing the result in binary and then...

Page 111: ...hen an arithmetic operation is performed on the program status word itself the result is stored in the program status word This means that there is no way to determine if there is a carry or borrow in the result of the operation nor if the result of the operation is zero However when the CMP flag is set 1 results of arithmetic operations are not stored Therefore even in the above case the CY and Z...

Page 112: ...uctions The SKT instruction skips the next instruction when a bit is judged as TRUE 1 and the SKF instruction skips the next instruction when a bit is judged as FALSE 0 The SKT and SKF instructions can only be used with data memory Bit judgement are not affected by the BCD flag in the program status word PSWORD and bit judgements do not cause either the CY or Z flag in the program status word PSWO...

Page 113: ... number 2 bits 3 2 and 0 of data memory M1 are judged Since bit 2 of data memory M1 is FALSE 0 the program branches to C 11 5 2 FALSE 0 Bit Judgement The FALSE 0 bit judgement instruction SKF m n is used to determine whether or not the bits specified by n in the four bits of data memory m are FALSE 0 When all bits specified by n are FALSE 0 this instruction causes the next instruction to be skippe...

Page 114: ... a value in data memory and immediate data In order to compare values in the general register and data memory a subtraction instruction is performed according to the values in the CMP and Z flags in the program status word PSWORD For more information concerning comparison of the general register and data memory refer to 11 3 Comparison judgements are not affected by the BCD or CMP flags in the pro...

Page 115: ...umber 2 because the contents of data memory M1 and immediate data 1000B are not equal the program branches to C 11 6 2 Not Equal to Judgement The not equal to judgement instruction SKNE m n4 is used to determine if immediate data and the contents of a location in data memory are not equal This instruction causes the next instruction to be skipped when the immediate data and the contents of data me...

Page 116: ...e in data memory is equal to that of the immediate data Lastly it will branch to E since the value in data memory is less than that of the immediate data 11 6 4 Less Than Judgement The less than judgement instruction SKLT m n4 is used to determine if the contents of a location in data memory is a value less than that of the immediate data operand If the value in data memory is less than that of th...

Page 117: ...d for rotation to the right RORC r rotates the contents of the general register in the direction of its least significant bit When this instruction is executed the contents of the CY flag becomes the most significant bit of the general register bit 3 and the least significant bit of the general register is placed in the CY flag Example 1 MOV PSW 0100B Sets CY flag to 1 MOV R1 1100B RORC R1 When th...

Page 118: ...ft Rotation to the left is performed by using the addition instruction ADDC r m Example MOV PSW 0000B Resets CY flag to 0 MOV R1 1000B MOV R2 0100B MOV R3 0010B ADDC R3 R3 ADDC R2 R2 ADDC R1 R1 The program code above rotates the 13 bits in CY R1 R2 and R3 to the left ...

Page 119: ... MEMO 104 ...

Page 120: ...ecuted for the port register pin statuses are read When P0ABIOn is 1 n 0 to 3 each pin of port 0A is used as output port and the contents written in the output latch are output to pins If a read instruction is executed when pins are output ports the contents of the output latch rather than pin statuses are fetched At reset P0ABIOn is set to 0 and all P0A pins become input ports The contents of the...

Page 121: ...is executed for the port register pin statuses are read When P0BGIO is 1 all pins of port 0B are used as output ports The contents written in the output latch are output to pins If a read instruction is executed when pins are used as output ports the contents of the output latch rather than pin statuses are fetched At reset P0BGIO is 0 and all P0B pins are input ports The value of the port 0B outp...

Page 122: ...ruction is executed for the port register the pin statuses are read If P0CBIOn is 1 n 0 to 3 the P0Cn pins are used as output port and the contents written in the output latch are output to pins If a read instruction is executed when pins are used as output ports the contents of the latch rather than pin statuses are fetched At reset P0CBIO0 to P0CBIO3 are 0 and all P0C pins are input ports The co...

Page 123: ...ort If P0CnIDI is 1 n 0 to 3 the P0Cn Cinn pin functions as the analog input pin of the comparator Therefore when using pins as analog inputs 1 should be set to P0CnIDI at the initial setting of the program Switching of the analog input pins to be compared is executed by CMPCH0 and CMPCH1 RF address 1CH To use the pins as analog input pins of the comparator set P0CBIOn 0 so that they are set as in...

Page 124: ...atch are output to pins If a data read instruction is executed when pins are used as output ports the output latch value rather than pin statuses is fetched At reset P0DBIOn is set to 0 and all P0D pins become input ports The contents of the port output latch become 0 The output latch contents remain unchanged even if P0DBIOn changes from 1 to 0 Port 0D can also be used for serial interface input ...

Page 125: ... 0 73H Port Mode Contents Read from the Port Register 0 73H Input port Pin status Output port Output latch contents An internal clock is selected as a serial clock Output latch contents An external clock is selected as a serial clock Pin status SI Pin status SO Not defined TMOUT Output latch contents Caution Using the serial interface causes the output latch for the P0D1 SO pin to be affected by t...

Page 126: ...EBIOn is 0 n 0 1 the each pin of P0E is used as input port If a data read instruction is executed for the port register the pin statuses are read If P0EBIOn is 1 n 0 1 the each pin of P0E is used as output port and the value written in the output latch are output pins If a data read instruction is executed regardless of the mode the pin statuses rather than output latch value are fetched At reset ...

Page 127: ...0E1 instruction is executed to bring the P0E1 pin to low level the status of each pin of port 0E changes as shown in Figure 12 1 2 In this case the P0E1 pin naturally changes to output low level but the value of the port register changes so that pin P0E0 which should output high level also outputs low level This result comes about because the CLR1 P0E1 instruction is executed not on the port regis...

Page 128: ... called group I O Port 0B is used as group I O The register shown in the figure below is used for input output switching Figure 12 2 Input Output Switching by Group I O RF 24H Read write Initial value when reset Bit 3 0 0 R W Read R write W P0BGIO 0 1 Function Sets Port 0B to input mode Sets Port 0B to output mode Bit 2 0 0 Bit 1 0 0 Bit 0 P0BGIO 0 ...

Page 129: ...g Figure 12 3 Bit I O Port Control Register 1 4 RF 35H Read write Initial value when reset Bit 3 P0ABIO3 0 R W Read R write W P0ABIO0 0 1 Function Sets P0A0 to input mode Sets P0A0 to output mode Bit 2 P0ABIO2 0 Bit 1 P0ABIO1 0 Bit 0 P0ABIO0 0 P0ABIO1 0 1 Function Sets P0A1 to input mode Sets P0A1 to output mode P0ABIO2 0 1 Function Sets P0A2 to input mode Sets P0A2 to output mode P0ABIO3 0 1 Func...

Page 130: ...R write W P0CBIO0 0 1 Function Sets P0C0 to input mode Sets P0C0 to output mode Bit 2 P0CBIO2 0 Bit 1 P0CBIO1 0 Bit 0 P0CBIO0 0 P0CBIO1 0 1 Function Sets P0C1 to input mode Sets P0C1 to output mode P0CBIO2 0 1 Function Sets P0C2 to input mode Sets P0C2 to output mode P0CBIO3 0 1 Function Sets P0C3 to input mode Sets P0C3 to output mode ...

Page 131: ...ets P0D1 to input mode Sets P0D1 to output mode P0DBIO2 0 1 Function Sets P0D2 to input mode Sets P0D2 to output mode P0DBIO3 0 1 Function Sets P0D3 to input mode Sets P0D3 to output mode Figure 12 3 Bit I O Port Control Register 4 4 RF 32H Read write Initial value when reset Bit 3 0 0 R W Read R write W P0EBIO0 0 1 Function Sets P0E0 to input mode Sets P0E0 to output mode Bit 2 0 0 Bit 1 P0EBIO1 ...

Page 132: ...lation on the register file using the PEEK POKE instruction 13 1 1 8 Bit Timer Counter Configuration Figure 13 1 shows the configuration of the 8 bit timer counter The 8 bit timer counter consists of the comparator which compares the 8 bit count register 8 bit modulo register count register and modulo register values and the separator which selects the count pulse Caution The modulo register is fo...

Page 133: ...errupt control register RF 0FH INT Timer mode register RF 11H TMRES TMEN TMCK1 TMCK0 Internal bus Timer carry output control mode register RF 12H Bit I O port control register RF 33H Match Reset Clear P0D3 TMOUT IRQTM set signal IRQTM clear signal Latch fX 32 fX 256 fX 2048 Selector D CLK R Reset INT Internal RESET 2 Timer count register 8 TMC Data buffer DBF TMOUT FF Q ...

Page 134: ...nitial value when reset Bit 3 TMEN 1 Bit 2 TMRES 0 Bit 1 TMCK1 0 Bit 0 TMCK0 0 R W Read R write W TMCK1 0 0 1 1 Source Clock Selection fx 256 fx 32 fx 2048 External clock from INT pin TMRES 0 1 TMCK0 0 1 0 1 Timer Reset No influence to timer Reset count register TMC and IRQTM Remark TMRES is automatically cleared 0 when set 1 When reading it 0 is always read TMEN 0 1 Timer Start Instruction Stop t...

Page 135: ...egister is initial value FFH the comparator outputs a match signal when 256 is counted The match signal from the comparator clears the contents of the count register to 0 and automatically sets the interrupt request flag IRQTM to 1 At this time interrupt handling occurs if the EI instruction interrupt acceptance enable instruction is executed and also the interrupt enable flag IPTM is set When an ...

Page 136: ... Setting the count value in modulo register A count value is set in the modulo register via the data buffer using the PUT instruction The peripheral address of the modulo register is 03H When a value is sent by the PUT instruction data in the eight low order bits DBF1 and DBF0 of data buffer is sent to the modulo register Figure 13 3 shows an example of count value setting ...

Page 137: ... word TMM Caution The range of values that can be set in the module register is 01H to FFH If 00H is set normal counting operation is not performed The modulo register is for writing only If is not possible to read a value from the modulo register Neither is it possible while the 8 bit timer counter is in operation to stop the counting operation even by executing the PUT TMM and DBF instructions D...

Page 138: ...ple and program example when calculating count value by interval time Example of assuming 7 ms as interval time for timer System clock fX 8 MHz Assuming 7 ms as interval time it is impossible to set 7 ms interval time from the resolution of the timer Therefore count value should be calculated by selecting the source clock the resolution of which is maximum fX 256 resolution 32 µs to set the neares...

Page 139: ...ount register of the 8 bit timer counter is cleared to 0 by setting to 1 the TMRES flag However the scaler for generating the count pulse from the system clock is not reset Therefore if during counting the TMRES flag is set to 1 to clear the count to 0 an error margin of one cycle of the count pulse is generated in the timing of the first count A count example when setting the modulo register to 2...

Page 140: ...el or from the high level When started from the high level the next rising edge is the first count When started from the low level the count starting point is the first count Therefore only the first count after the counting is started generates an error of 0 5 to 1 5 counts during the time until the identity signal is issued An example of counting when 1 is set for the modulo register is shown be...

Page 141: ... data buffer using the GET instruction The count register values of timer are assigned to peripheral address 02H Count register values of timer can be read into DBF by using the GET instruction During execution of the GET instruction timer count register stops count operation and a count value is retained When a count pulse enters the timer in use during execution of the GET instruction the count ...

Page 142: ...l Address 02H Count value 2 Program example Measuring pulse width input from INT pin system clock fX 8 MHz The following is an example of measuring generation interval of external interrupt from INT pin by using timer At this time the pulse width from INT pin should be within the count up time of timer Program example CNTTMH MEM 0 30H Symbol definition of save area of count value CNTTML MEM 0 31H ...

Page 143: ...ESTART INTJOB Vector interrupt becomes interrupt prohibit GET DBF TMC state automatically immediately after accepting interrupt MOV RPH DM CNTTMH SHR 7 AND 0EH Sets general register pointer by using symbol defined CNTTMH and CNTTML AND RPL 0001B OR RPL DM CNTTMH SHR 3 AND 0EH At this time BCD flag retains the previous state LD CNTTMH DBF1 Stores count value to count save area LD CNTTML DBF0 EI Mak...

Page 144: ...put pin The mask option enables this pin to contain a pull up resistor If this pin does not contain a pull up resistor its initial status is high impedance An internal timer output flip flop starts operating when TMEN is set to 1 To make the flip flop start output beginning at an initial value set 1 in TMRES and reset the flip flop Remark The µPD17P132 and 17P133 have no mask option resistor Figur...

Page 145: ...x 15 6 ms 0 1 approx 7 64 µs approx 1 9 ms 1 0 approx 489 µs approx 125 ms 1 1 INT pin Note 2 0 0 128 µs 32 768 ms 0 1 16 µs 4 096 ms 1 0 1 024 ms 262 144 ms 1 1 INT pin Note 2 0 0 512 µs 131 072 ms 0 1 64 µs 16 384 ms 1 0 4 096 ms 1 048576 s 1 1 INT pin Note 2 Notes 1 The guaranteed frequency range of oscillation for the µPD17120 17132 17P132 is fCC 400 kHz to 2 4 MHz 2 High low level width of IN...

Page 146: ...used as a 4 bit A D converter by software using 15 types of internal reference voltage 13 2 1 Configuration of Comparator Figure 13 8 Configuration of Comparator Remark The sampling time of an analog input is as follows µPD17132 17P132 8 fCC 4 µs at 2 MHz µPD17133 17P133 28 fX 3 5 µs at 8 MHz RF 1CH CMPCH1 CMPCH1 0 0 RF 1DH CMPVREF1 CMPVREF2 RF 1EH CMPSTRT CMPRSLT 0 0 Selector Control circuit Sele...

Page 147: ...rating during analog voltage comparison CMPSTRT 0 Comparator is stopped comparison is completed When comparing comparator analog voltage CMPSTRT 1 manipulating comparator input channel selection flag CMPCH1 CMPCH0 or comparator reference voltage selection flag CMPVREF0 to CMPVREF3 is ignored and the data in these registers remain unchanged Therefore changing comparator operation modes are disabled...

Page 148: ... 3 CMPVREF3 1 Bit 2 CMPVREF2 0 Bit 1 CMPVREF1 0 Bit 0 CMPVREF0 0 R W Read R write W Selected Reference Voltage Voltage applied to Vref pin 1 16 VDD 2 16 VDD 1 8 VDD 3 16 VDD 4 16 VDD 1 4 VDD 5 16 VDD 6 16 VDD 3 8 VDD 7 16 VDD 8 16 VDD 1 2 VDD 9 16 VDD 10 16 VDD 5 8 VDD 11 16 VDD 12 16 VDD 3 4 VDD 13 16 VDD 14 16 VDD 7 8 VDD 15 16 VDD CMPVREF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CMPVREF3 0 0 0 0 0 0 0 ...

Page 149: ... to Cin3 is higher than the external internal reference voltage CMPSTRT 0 1 CMPRSLT 0 1 Comparator Operation Check at Reading Comparator Operation Start at Writing During comparator operation is stopped or comparator voltage comparison operation is completed During comparator is operating Invalid Start comparator operation Remark CMPSTRT is cleared to 0 only when the comparator voltage com parison...

Page 150: ...CK0 Serial clock to be selected 0 0 External clock from the SCK pin 0 1 fX 16 1 0 fX 128 1 1 fX 1024 2 Transmission operation By setting to 1 SIOEN each pin of port 0D P0D0 SCK P0D1 SO P0D2 SI functions as a pin for serial interfacing At this time if SIOTS is set to 1 the operation is started synchronously with the falling edge of the serial clock Also setting SIOTS will result in automatically cl...

Page 151: ...an output instruction is executed for P0D1 the output latch state of the shift register is also changed P0D2 SI LSB MSB P0D1 SO Serial start SIOTS SIOCK1 SIOCK0 SIOHIZ IRQSIO clear signal IRQSIO set signal Carry Clear Serial clock counter Clock P0D0 SCK f X 1024 f X 128 f X 16 SIOEN P0DBIO0 P0DBIO1 Shift register SIOSFR Q S R Selector Selector Output latch Output latch Note One shot ...

Page 152: ...and reception Serial data input output is controlled by a serial clock The MSB of the shift register is output from the SO line with a falling edge of the serial clock SCK The contents of the shift register is shifted one bit and at the same time data on the SI line is loaded into the LSB of the shift register The serial clock counter counts serial clock pulses Every time it counts eight clocks th...

Page 153: ... 14 Timing of the 8 Bit Reception Mode High impedance 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK pin SO pin IRQSIO SI pin Transmission starts in synchronization with the SCK pin falling edge An instruction which writes 1 into SIOTS is executed Transmission start indication Transmission completion Remark DIn Serial input data 3 Operation stop mode If the value in SIOTS RF address 1AH bit 3...

Page 154: ... shift register is operating Start and Stop of Serial Transmission at Writing Forced termination of the shift register Disables intermediate restart Start of shift register operation At internal clock selection Starts operating internal devided signal of a system clock fX as a serial clock At external clock selection Starts operation in synchronization with an SCK pin falling edge SIOHIZ 0 1 SIOTS...

Page 155: ...rite Initial value when reset Bit 3 0 0 R W Read R write W Bit 2 0 0 Bit 1 0 0 Bit 0 SIOEN 0 SIOEN 0 1 Serial Interface Enable The pins of port 0D P0D0 SCK P0D1 SO P0D2 SI function as the serial interface The pins of port 0D P0D0 SCK P0D1 SO P0D2 SI function as ports Remark Refer to CHAPTER 12 PORTS ...

Page 156: ... not affect the shift register Figure 13 16 Setting a Value in the Shift Register Example of setting value 64H in the shift register SIODATL DAT 4H SIODATL is assigned to 4H using symbol definition SIODATH DAT 6H SIODATH is assigned to 6H using symbol definition MOV DBF0 SIODATL MOV DBF1 SIODATH PUT SIOSFR DBF Value is transmitted using reserved word SIOSFR PUT SIOSFR DBF SIOSFR Peripheral Address...

Page 157: ...low order bits DBF1 DBF0 are valid Executing the GET instruction does not affect the eight high order bits of DBF Figure 13 17 Reading a Value from the Shift Register GET DBF SIOSFR Example of using reserved words DBF and SIOSFR GET DBF SIOSFR SIOSFR Peripheral Address 01H Data Buffer DBF3 Retained 8 bit data b7 0 b5 1 b4 0 b3 0 b2 1 b1 0 b0 0 b6 1 b0 0 b1 0 b2 1 b3 0 b0 0 b1 1 b2 1 b3 0 b0 b1 b2 ...

Page 158: ...nterrupt request flag Example MAIN CALL SIOJOB BR MAIN SIOJOB DI Prohibits interrupt in SIOJOB CLR1 IRQSIO Clears interrupt request flag of SIO SET1 SIOEN Enables SIO MOV DBF0 SIODATL Sets transmitted data MOV DBF1 SIODATH PUT SIOSFR DBF INITFLG SIOTS NOT SIOHIZ SIOCK1 NOT SIOCK0 Sets serial clock to fX 128 starts shift register operation and outputs serial data LOOP SKT1 IRQSIO Transmission recep...

Page 159: ... 0H MOV SIODATL 0H CLR1 IRQSIO Clears interrupt request flag of SIO SET1 SIOEN Enables SIO INITFLG SIOTS SIOHIZ NOT SIOCK1 NOT SIOCK0 Sets serial clock to external clock starts receiving serial data and sets P0D1 SO pins to input port output high impedance EI Permits all interrupts Main processing MAIN CALL JOB CALL JOB BR MAIN SIOJOB GET DBF SIOSFR Reads reception data MOV RPH 0000B Sets general ...

Page 160: ... released by an interrupt request Release source can be selected by the interrupt enable flag Cautions 1 In interrupt handling the BCD CMP CY Z and IXE flags are saved in the stack automatically by the hardware for one level of multiple interrupts The DBF and WR are not saved by the hardware when peripheral hardware such as the timers or serial interface is accessed in interrupt handling It is rec...

Page 161: ...If two or more interrupt requests occur or the retained interrupt requests are enabled at the same time they are handled according to priorities shown in Table 14 1 Table 14 1 Interrupt Source Types Vector Internal Address External INT pin RF 0FH bit 0 1 0003H IRQ IP IEGMD0 1 External Rising edge or falling RF 3FH RF 2FH RF 1FH Edge can be selected bit 0 bit 0 Timer 2 0002H IRQTM IPTM Internal RF ...

Page 162: ...sed to determine whether an accepted interrupt is to be executed If the EI instruction is executed INTE for enabling interrupt reception is set Since the INTE flag is not registered in the register file flag status cannot be checked by instructions The DI instruction clears the INTE flag to 0 and disables all interrupts At reset the INTE flag is cleared to 0 and all interrupts are disabled Table 1...

Page 163: ... to 1 during PEEK instruction execution Note Since the INT flags are not latched they change all the time in response to the logical state of the pin However once the IRQ flag is set it stays set until an interrupt is accepted The POKE instruction to address 0FH is invalid RF 1FH Read write Initial value when reset Bit 3 0 0 Bit 2 0 0 Bit 1 IEGMD1 0 Bit 0 IEGMD0 0 R W Read R write W IEGMD1 IEGMD0 ...

Page 164: ...n interrupt request from the INT pin is forced to occur RF 3FH Read write Initial value when reset Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 IRQTM 1 R W Read R write W IRQTM 0 TM Interrupt Request at Reading 1 No interrupt request has been issued from timer or a timer interrupt is being handled The contents of the timer count register matches that of the timer modulo register and an interrupt request oc...

Page 165: ...eding No interrupt request has been issued from the serial interface or a serial interface interrupt is being handled Serial interrupt transmission is completed and an interrupt request occurs Or a serial interface intrrupt request is being held IRQSIO 0 SIO Interrupt Request at Writing An interrupt request from the serial interface is forcibly released An interrupt request from the serial interfa...

Page 166: ...s the EI instruction If the IRQ flag is set to 1 executes interrupt handling IPTM 0 TM Interrupt Enable Disables an interrupt from timer Holds an interrupt if the IRQTM flag is set to 1 1 Enables an interrupt from timer Executed the EI instruction If the IRQTM flag is set to 1 executes interrupt handling IPSIO 0 SIO Interrupt Enable Disables an interrupt from serial interface Holds an interrupt if...

Page 167: ...ted after two instruction cycles are completed If interrupt operation is started one level of the address stack register is consumed to store the return address of the program and also a level of the interrupt stack register is used to save the PSWORD in the system register If multiple interrupts are enabled and occure simultaneously the interrupts are processed in order of higher priority In this...

Page 168: ...1 NO NO YES YES Clear INTE flat and IRQ associated with accepted interrupt to 0 Decrement stack pointer by 1 SP 1 Save contents of program counter in stack pointed to by stack pointer Load vector address into program counter Save PSWORD content in interrupt stack register Hold interrupt until IP is set Hold interrupt until EI instruction is executed ...

Page 169: ...s not set for the RETI instruction Interrupt handling is completed To handle a pending interrupt successively execute the EI instruction immediately before the RETI instruction and set the INTE flag to 1 2 To execute the RETI instruction following the EI instruction no interrupt is accepted between EI instruction execution and RETI instruction execution This is because the EI instruction sets the ...

Page 170: ...er than MOVT or EI Machine cycle Instruction IRQ M0 An instruction other than MOVT or EI INT cycle M1 M2 M3 M0 M1 M2 M3 M0 M1 M2 M3 M0 M1 Vector address instruction Interrupt occurrence recognized 2 When the skip condition for the skip instruction is materialized in 1 3 When an interrupt has occurred after M2 of an instruction other than MOVT or EI Machine cycle Instruction IRQ M0 M1 M2 M3 M0 M1 M...

Page 171: ...nstruction INT cycle M1 M2 M3 M0 M1 M2 M3 M0 M1 M2 M3 M0 M1 Vector address instruction Interrupt occurrence recognized 6 When an interrupt has occurred before M2 of an EI instruction Machine cycle Instruction IRQ M0 EI instruction INT cycle M1 M2 M3 M0 M1 M2 M3 M0 M1 M2 M3 M0 M1 Vector address instruction Interrupt occurrence recognized An instruction other than MOVT or EI 7 When an interrupt has ...

Page 172: ...is cycle PC and PSWORD saving and IRQ clearing are performed 2 For execution of the MOVT instruction two instruction cycles are exceptionally required 3 The EI instruction is considered to prevent multiple interrupts from occurring when returning from the interrupt operation Machine cycle Instruction IRQ M0 Skip instruction INT cycle M1 M2 M3 M0 M1 M2 M3 M0 M1 M2 M3 M0 M1 Vector address instructio...

Page 173: ...d be executed by software In the following program after generating external interrupt the signal from INT pin becomes effective after confirming that there is not change in the level of INT pin two times in every 100 µs Example WAITCNT MEM 0 00H Counter of wait processing KEYON FLG 0 01H 3 If key ON is determined even just once KEYON 1 SECOND FLG 0 01H 0 A flag describing key checking for the sec...

Page 174: ... the level of INT pin BR KEY_OFF If INT pin is high level interrupt is invalid and returns to main processing SKF1 SECOND First wait BR WAIT_END If it is the first time wait again after setting SECOND In the case of the second time finish wait processing SET1 SECOND MOV WAITCNT 0 BR INT_JOB WAIT_END SET1 KEYON Judges that there is key input BR INT_JOB_END KEY_OFF CLR1 SECOND SECOND 0 INT_JOB_END M...

Page 175: ... MEMO 160 ...

Page 176: ... mode that halts CPU operation because the clock supplying the CPU is stopped even when the system clock s oscillation continues Although compared with STOP mode this mode does not reduce the current consumption operation can start immediately after HALT is canceled because the system clock is oscillating Also in either the STOP mode or HALT mode the status of items such as the data memory registe...

Page 177: ...e clock has been selected for the shift clockNote 1 ComparatorNote 2 Operation stoppedNote 1 Operation stopped The result after resumption of the operation is undefined INT Operable Notes 1 At the point where STOP 0000B has been executed the pin s status is placed in input port mode even when the pin is used with its dual function 2 Limited to µPD17132 17133 17P132 and 17P133 Cautions 1 Be sure to...

Page 178: ...e is canceled 4 Even if the HALT instruction is executed when IRQ 1 the HALT instruction is ignored handled as the NOP instruction thus failing to place the system in HALT mode 15 2 2 Start Address after HALT Mode is Canceled The start address varies depending on the cancellation condition and the interrupt enable condition Table 15 3 Start Address After HALT Mode Cancellation Cancellation Conditi...

Page 179: ...de c HALT cancellation by IRQ if EI Execution of the HALT instruction Interrupt operation acceptance IRQ Operation mode HALT mode Operation mode Execution of the HALT instruction TM count up RESET Operation mode HALT mode System reset srtate WAIT a Operation mode Start of address 0 WAIT a This refers to the wait time until TM counts the divide by 256 clock up to 256 256 256 fX when approximately 3...

Page 180: ...al hardware used for HALT cancellation is cleared to 0 The interrupt enable flag IP of the peripheral hardware used for HALT cancellation is set to 1 Caution Be sure to code a NOP instruction immediately before the HALT instruction The time of one instruction is generated between the IRQ operation instruction and the HALT instruction by coding the NOP instruction immediately before the HALT instru...

Page 181: ...cted correctly to the HALT instruction HALT 1000B Executes the HALT instruction correctly placing the system in HALT mode 2 An incorrect program example Setting of IRQ CLR1 IRQ Clearance of IRQ is not reflected as to the HALT instruction It is the instruction following the HALT instruction that is reflected HALT 1000B The HALT instruction is ignored not placing the system in HALT mode ...

Page 182: ...t IP 1 Cancellation by IRQTM is not possible 3 Even if the STOP instruction is executed when IRQ 1 the STOP instruction is ignored handled as a NOP instruction thus failing to place the system in STOP mode 15 3 2 Start Address after STOP Mode Cancellation The start address varies depending on the cancellation condition and the interrupt enable condition Table 15 5 Start Address After STOP Mode Can...

Page 183: ...g on the resonator Execution of the STOP instruction TM count up IPQ Operation mode STOP mode WAIT c Operation mode WAIT c This refers to the wait time until TM counts the divide by m clock up to n 1 n 1 m fX α n and m values immediately before the system is placed in STOP mode α Oscillation growth time Varies depending on the resonator Execution of the STOP instruction Interrupt operation accepta...

Page 184: ...lue of the timer wait time for generation of oscillation stability Clears the interrupt request flag IRQSIO of the serial interface to 0 Sets the interrupt enable flag IPSIO of the serial interface to 1 Caution Be sure to code a NOP instruction immediately before the STOP instruction The time of one instruction is generated between the IRQ operation instruction and the STOP instruction by coding t...

Page 185: ...lected correctly to the STOP instruction STOP 1000B Executes the STOP instruction correctly placing the system in STOP mode 2 An incorrect program example Setting of IRQ CLR1 IRQ Clearance of IRQ is not reflected to the STOP instruction It is the instruction following the STOP instruction that is reflected STOP 1000B The STOP instruction is ignored not placing the system in STOP mode ...

Page 186: ...ode Program Counter 0000H 0000H 0000H Port Input Output mode Input Input Input Output latch 0 0 Undefined General Purpose Other than DBF Undefined Retains the status immedi Undefined Data Memory ately preceding the resetting DBF Undefined Undefined Undefined System Register Other than WR 0 0 0 WR Undefined Retains the status immedi Undefined ately preceding the resetting Control Register SP 5H IRQ...

Page 187: ...ernally generated Operation is the same as that when reset is caused externally by the RESET input At address stack overflow and underflow reset oscillation stabilization wait time WAIT a does not occur Operation starts from address 0000H after initial statuses are internally set Figure 16 2 Resetting RESET TMEN TMRES Operationg mode RESET WAIT aNote Operating mode Note This is oscillation stabili...

Page 188: ... externally 16 3 1 Conditions Required to Enable the Power On Reset Function This function is effective when used together with the power down reset function The following conditions are required to validate the power on reset function 1 The power voltage must be 4 5 to 5 5 V during normal operation including the standby state 2 The frequency of the system clock oscillator must be 400 kHz to 4 MHz...

Page 189: ...4 MHzNote in which the microcontroller is guaranteed to operate When this period elapses the microcontroller enters normal operation mode Figure 16 3 shows an example of the power on reset operation Note µPD17121 17133 17P133 only Operation of the power on reset circuit 1 This circuit always monitors the voltage applied to the VDD pin 2 This circuit resets the microcontroller Note until power reac...

Page 190: ...refers to the state in which all of the functions of the microcontroller are stopped A Voltage at which oscillation starts B Voltage at which the power on reset operation terminates VDD V 5 0 2 7 A B 0 Time t State of oscillation Period in which the microcon troller is guar anteed to operate Power on reset signal Operation state of the micro controller Oscillation stop Oscillation start Undefined ...

Page 191: ...operation is terminated the microcontroller waits the time required for stable oscillation using the timer The microcontroller then enters normal operation starts from the top of memory Figure 16 4 shows an example of the power down operation Figure 16 5 shows an example of reset operation during the period from power down reset to power recovery Operation of the power down reset circuit 1 This ci...

Page 192: ...ped VDD V 5 0 4 5 2 7 C State of oscillation Period in which the microcon troller is guar anteed to operate Power down reset signal Operation state of the micro controller 3 5 0 Oscillating Guaranteed period Power on reset signal Oscillating mode Reset state Power down reset Oscillation stop Undefined periodNote Time t Maximum voltage detected by the power down reset function 4 5V Typical voltage ...

Page 193: ...oscillation Period in which the microcon troller is guar anteed to operate Power down reset signal Operation state of the micro controller 3 5 0 Oscillating Power on reset signal Oscillating mode Reset state Power down reset Time t Maximum voltage detected by the power down reset function 4 5V Typical voltage detected by the power down reset function 3 5V Voltage at which the power down reset func...

Page 194: ...pply pin Apply 6 V to this pin CLK Clock input for updating address Updates program memory address by inputting four pulses MD0 MD3 Select operation mode D0 D7 8 bit data I O pins 17 1 DIFFERENCES BETWEEN MASK ROM VERSION AND ONE TIME PROM VERSION The µPD17P132 and 17P133 are microcontrollers replacing the program memory of the on chip mask ROM version µPD17132 and 17133 to one time PROM Table 17 ...

Page 195: ... highly compatible with the masked ROM product they still differ from each other in terms of their internal ROM circuits and some electrical features When switching from a PROM product to a ROM product ensure to make sufficient application evaluations based on masked ROM product samples 17 2 OPERATING MODE IN PROGRAM MEMORY WRITING VERIFYING The µPD17P132 and 17P133 become program memory writing v...

Page 196: ... the program inhibit mode 7 Write data in mode for 1 ms writing 8 Set the program inhibit mode 9 Set the verify mode MD0 MD3 LLHH If the program has been correctly written proceed to 10 If not repeat 7 through 9 10 Additional writing of number of times the program has been written in 7 through 9 1ms 11 Set the program inhibit mode 12 Input four pulses to the CLK pin to update the program memory ad...

Page 197: ...s 5 Apply 6 V to VDD and 12 5 V to VPP 6 Set mode selector pins to the program inhibit mode 7 Set the verify mode When clock pulses are input to the CLK pin data for each address can be sequentially output with four clocks as one cycle 8 Set the program inhibit mode 9 Set the program memory address 0 clear mode 10 Change the voltage of VDD and VPP pins to 5 V 11 Turn off the power Repeat times Wri...

Page 198: ...ITING VERIFYING 183 Figure 17 2 shows the program reading procedure 2 through 9 Figure 17 2 Procedure of Program Memory Reading Reset VDD 1 VDD GND VDD VPP VDD GND VPP CLK MD0 MD1 D0 D7 Hi Z Output data Output data Hi Z MD2 MD3 L ...

Page 199: ... MEMO 184 ...

Page 200: ...100 4 AND r m AND m n4 0101 5 XOR r m XOR m n4 0110 6 OR r m OR m n4 INC AR INC IX MOVT DBF AR BR AR CALL AR RET RETSK EI DI 0111 7 RETI PUSH AR POP AR GET DBF p PUT p DBF PEEK WR rf POKE rf WR RORC r STOP s HALT h NOP 1000 8 LD r m ST m r 1001 9 SKE m n4 SKGE m n4 1010 A MOV r m MOV m r 1011 B SKNE m n4 SKLT m n4 1100 C BR addr CALL addr 1101 D MOV m n4 1110 E SKT m n 1111 F SKF m n 185 ...

Page 201: ...ck register IX Index register MP Data memory row address pointer MPE Memory pointer enable flag m Data memory address indicated by mR and mC mR Data memory row address upper mC Data memory column address lower n Bit position 4 bits n4 Immediate data 4 bits PC Program counter p Peripheral address pH Peripheral address upper 3 bits pL Peripheral address lower 4 bits r General register column address...

Page 202: ...C r m n4 m m n4 10101 mR mC n4 Test SKT m n CMP 0 if m n n then skip 11110 mR mC n SKF m n CMP 0 if m n 0 then skip 11111 mR mC n Compare SKE m n4 m n4 skip if zero 01001 mR mC n4 SKNE m n4 m n4 skip if not zero 01011 mR mC n4 SKGE m n4 m n4 skip if not borrow 11001 mR mC n4 SKLT m n4 m n4 skip if borrow 11011 mR mC n4 Rotate RORC r CY r b3 r b2 r b1 r b0 00111 000 0111 r Transfer LD r m r m 01000...

Page 203: ...NTSK SP SP 1 00111 100 1110 0000 Interrupt EI INTEF 1 00111 000 1111 0000 DI INTEF 0 00111 001 1111 0000 Others STOP s STOP 00111 010 1111 s HALT h HALT 00111 011 1111 h NOP No operation 00111 100 1111 0000 18 4 ASSEMBLER AS17K MACRO INSTRUCTIONS Legend flag n FLG symbol Can be omitted Mnemonic Operand Operation n Macro SKTn flag 1 flag n if flag 1 flag n all 1 then skip 1 n 4 Instructions SKFn fl...

Page 204: ...y contents to the general register contents and stores the result in general register When CMP 1 r m The result is not stored in the register Carry flag CY and zero flag Z are changed according to the result Sets carry flag CY if a carry occurs as a result of the addition Resets the carry flag CY if no carry occurs If the addition result is other than zero zero flag Z is reset regardless of compar...

Page 205: ...RPL 0 and stores the result in address 0 03H 0 03H 0 03H 0 2FH MEM003 MEM 0 03H MEM02F MEM 0 2FH MOV BANK 00H Data memory bank 0 MOV RPH 00H General register bank 0 MOV RPL 00H General register row address 0 ADD MEM003 MEM02F Example 2 Adds the address 0 2FH contents to the address 0 23H contents when row address 2 0 20H 0 2FH in bank 0 is specified as the general register RPH 0 RPL 4 and stores t...

Page 206: ...6FH Address obtained as result of ORing index register con tents 0 40H and data memory address 0 2FH MEM003 MEM 0 03H MEM02F MEM 0 2FH MOV RPH 00H General register bank 0 MOV RPL 00H General register row address 0 MOV IXH 00H IX 00001000000B MOV IXM 04H MOV IXL 00H SET1 IXE IXE flag 1 ADD MEM003 MEM02F IX 00001000000B 0 40H Bank operand OR 00000101111B 0 2FH Specified address 00001101111B 0 6FH Ex...

Page 207: ...s case MP memory pointer for general register indirect transfer is invalid because the MPE flag memory pointer enable is reset 4 Note The first operand for the ADD r m instruction is a column address in general register Therefore if the instruction is described as follows the column address for the general register is 03H MEM013 MEM 0 13H MEM02F MEM 0 2FH ADD MEM013 MEM02F Indicates the general re...

Page 208: ...flag Z is reset regardless of compare flag CMP If the addition result is zero with the compare flag reset CMP 0 the zero flag Z is set If the addition result is zero with the compare flag set CMP 1 the zero flag Z is not changed Addition can be executed in binary 4 bit or BCD The BCD flag for the PSWORD specifies which kind of addition is to be executed 3 Example 1 Adds 5 to the address 0 2FH cont...

Page 209: ...s and stores the result in address 0 2FH At this time data memory address 0 2FH can be specified by selecting data memory address 2FH if IXE 1 IXH 0 IXM 0 and IXL 0 i e IX 0 00H 2 2FH 0 2FH 05H Address obtained as result of ORing index register contents 0 00H and data memory address 0 2FH MEM02F MEM 0 2FH MOV BANK 00H Data memory bank 0 MOV IXH 00H IX 00000000000B MOV IXM 00H MOV IXL 00H SET1 IXE ...

Page 210: ... If the addition result is other than zero zero flag Z is reset regardless of compare flag CMP If the addition result is zero with the compare flag reset CMP 0 the zero flag Z is set If the addition result is zero with the compare flag set CMP 1 the zero flag Z is not changed Addition can be executed in binary 4 bit or BCD The BCD flag for program status word PSWORD specifies which kind of additio...

Page 211: ...t when row address 2 in bank 0 0 20H 0 2FH is specified as a general register MEM00D MEM 0 0DH MEM00E MEM 0 0EH MEM00F MEM 0 0FH MEM02D MEM 0 2DH MEM02E MEM 0 2EH MEM02F MEM 0 2FH MOV RPH 00H General register bank 0 MOV RPL 04H General register row address 2 MOV BANK 00H Data memory bank 0 ADDC MEM00F MEM02F ADDC MEM00E MEM02E ADDC MEM00D MEM02D Example 3 Adds the address 0 0FH contents to the add...

Page 212: ...dds the 12 bit contents for addresses 0 40H through 0 42H to the 12 bit contents for addresses 0 0DH through 0 0FH and stores the result in 12 bit contents for addresses 0 0DH through 0 0FH 0 0DH 0 0DH 0 40H 0 0EH 0 0EH 0 41H CY 0 0FH 0 0FH 0 42H CY MEM000 MEM 0 00H MEM001 MEM 0 01H MEM002 MEM 0 02H MEM00D MEM 0 0DH MEM00E MEM 0 0EH MEM00F MEM 0 0FH MOV BANK 00H Data memory bank 0 MOV RPH 00H Gene...

Page 213: ...a carry occurs as a result of the addition Resets the carry flag CY if no carry occurs If the addition result is other than zero zero flag Z is reset regardless of compare flag CMP If the addition result is zero with the compare flag reset CMP 0 the zero flag Z is set If the addition result is zero with the compare flag set CMP 1 the zero flag Z is not changed Addition can be executed in binary 4 ...

Page 214: ...rough 0 4FH 0 4FH 0 4FH 05H 0 4EH 0 4EH CY 0 4DH 0 4DH CY MEM00D MEM 0 0DH MEM00E MEM 0 0EH MEM00F MEM 0 0FH MOV BANK 00H Data memory bank 0 MOV IXH 00H IX 00001000000B 0 40H MOV IXM 04H MOV IXL 00H SET1 IXE IXE flag 1 ADD MEM00F 5 0 4FH 0 4FH 5H ADDC MEM00E 0 0 4EH 0 4EH CY ADDC MEM00D 0 0 4DH 0 4DH CY 5 INC AR Increment address register 1 OP code 10 8 7 4 3 0 00111 000 1001 0000 2 Function AR AR...

Page 215: ...on instructions ADD AR0 01H ADDC AR1 00H ADDC AR2 00H ADDC AR3 00H Example 2 Transfers table data 16 bits 1 address at a time to DBF data buffer using the table reference instruction for details refer to 10 2 3 Table Reference Address Table data 010H DW 0F3FFH 011G DW 0A123H 012H DW 0FFF1H 013H DW 0FFF5H 014H DW 0FF11H MOV AR3 0H Sets table data address MOV AR2 0H 0010H in address register MOV AR1...

Page 216: ...Adds 1 to the total of 12 bit contents for IXH IXM and IXL index registers in the system register and stores the result in IXH IXM and IXL IXL IXL 1 IXM IXM CY IXH IXH CY INC IX This program can be rewritten as follows with addition instructions ADD IXL 01H ADDC IXM 00H ADDC IXH 00H Example 2 Clears all the contents for data memory addresses 0 00H through 0 73H to 0 using the index register MOV IX...

Page 217: ...eral register contents and stores the result in general register When CMP 1 r m The result is not stored in the register Carry flag CY and zero flag Z are changed according to the result Sets carry flag CY if a borrow occurs as a result of the subtraction Resets the carry flag if no borrow occurs If the subtraction result is other than zero zero flag Z is reset regardless of compare flag CMP If th...

Page 218: ...es the result in address 0 23H 0 23H 0 23H 0 2FH MEM023 MEM 0 23H MEM02F MEM 0 2FH MOV BANK 00H Data memory bank 0 MOV RPH 00H General register bank 0 MOV RPL 04H General register row address 2 SUB MEM023 MEM02F Example 3 Subtracts the address 0 6FH contents from the address 0 03H contents and stores the result in address 0 03H At this time data memory address 0 6FH can be specified by selecting d...

Page 219: ... 0 MOV RPH 00H General register bank 0 MOV RPL 00H General register row address 0 MOV IXH 00H IX 00000010000B 0 10H MOV IXM 01H MOV IXL 00H SET1 IXE IXE flag 1 SUB MEM003 MEM02F IX 00000010000B 0 10H Bank operand OR 00000101111B 0 2FH Specified address 00000111111B 0 3FH 4 Note The first operand for the SUB r m instruction must be a general register address Therefore if the instruction is describe...

Page 220: ...et regardless of compare flag CMP If the subtraction result is zero with the compare flag reset CMP 0 the zero flag Z is set If the subtraction result is zero with the compare flag set CMP 1 the zero flag Z is not changed Subtraction can be executed in binary 4 bit or BCD The BCD flag for program status word PSWORD specifies which kind of subtraction is to be executed 3 Example 1 Subtracts 5 from ...

Page 221: ... and stores the result in address 0 2FH At this time data memory address 0 2FH can be specified by selecting data memory address 2FH if IXE 1 IXH 0 IXM 0 and IXL 0 i e IX 0 00H 0 2FH 0 2FH 5 Address obtained as a result of ORing index register contents 0 00H and data memory address 0 2FH MEM02F MEM 0 2FH MOV BANK0 00H Data memory bank 0 MOV IXH 00H IX 00000000000B 0 00H MOV IXM 00H MOV IXL 00H SET...

Page 222: ...f the subtraction result is other than zero zero flag Z is reset regardless of compare flag CMP If the subtraction result is zero with the compare flag reset CMP 0 the zero flag Z is set If the subtraction result is zero with the compare flag set CMP 1 the zero flag Z is not changed Subtraction can be executed in binary 4 bit or BCD The BCD flag for program status word PSWORD specifies which kind ...

Page 223: ...H MEM002 MEM 0 02H MEM00D MEM 0 0DH MEM00E MEM 0 0EH MEM00F MEM 0 0FH MOV BANK 00H Data memory bank 0 MOV RPH 00H General register bank 0 MOV RPL 00H General register row address 0 MOV IXH 00H IX 00001000000B 0 40H MOV IXM 04H MOV IXL 00H SET1 IXE IXE flag 1 SUB MEM00D MEM000 0 0DH 0 0DH 0 40H SUBC MEM00E MEM001 0 0EH 0 0EH 0 41H SUBC MEM00F MEM002 0 0FH 0 0FH 0 42H Example 3 Compares the 12 bit c...

Page 224: ...t immediate data from data memory with carry flag 1 OP code 10 8 7 4 3 0 10011 mR mC n4 2 Function When CMP 0 m m n4 CY Subtracts immediate data and the value of carry flag CY from the data memory contents and stores the result in data memory When CMP 1 m n4 CY The result is not stored in the data memory Carry flag CY and zero flag Z are changed according to the result Sets carry flag CY if a borr...

Page 225: ...ugh 0 0FH and stores the result in addresses 0 0DH through 0 0FH 0 0FH 0 0FH 05H 0 0EH 0 0EH CY 0 0DH 0 0DH CY MEM00D MEM 0 0DH MEM00E MEM 0 0EH MEM00F MEM 0 0FH SUB MEM00F 05H SUBC MEM00E 00H SUBC MEM00D 00H Example 2 To subtract 5 from the 12 bit contents for addresses 0 4DH through 0 4FH and store the result in addresses 0 4DH through 0 4FH 0 4FH 0 4FH 05H 0 4EH 0 4EH CY 0 4DH 0 4DH CY MEM00D M...

Page 226: ...P flag 1 Z flag 1 SUB MEM000 0H Contents for addresses 0 00H 0 03H do not SUBC MEM001 0AH change because CMP flag is set SUBC MEM002 3H SUBC MEM003 0FH SKF1 Z Z flag 1 if contents are the same if not Z flag 0 BR LAB1 BR LAB2 LAB1 LAB2 18 5 3 Logical Operation Instructions 1 OR r m OR between general register and data memory 1 OP code 10 8 7 4 3 0 00110 mR mC r 2 Function r r m ORs the general regi...

Page 227: ... 1 1 1 1 Address 03H OR MEM003 MEM 0 03H MEM02F MEM 0 2FH MOV MEM003 1010B MOV MEM02F 0111B OR MEM003 MEM02F 2 OR m n4 OR between data memory and immediate data 1 OP code 10 8 7 4 3 0 10110 mR mC n4 2 Function m m n4 ORs the data memory contents and immediate data Stores the result in data memory 3 Example 1 To set bit 3 MSB for address 0 03H 0 03H 0 03H 1000B Address 0 03 1 don t care MEM003 MEM ...

Page 228: ...100 mR mC r 2 Function r r m ANDs the general register contents with data memory contents and stores the result in general register 3 Example 1 ANDs the address 0 03H 1010B contents and the address 0 2FH 0110B contents Stores the result 0010B in address 0 03H 0 03H 0 03H 0 2FH MEM003 MEM 0 03H MEM02F MEM 0 2FH MOV MEM003 1010B MOV MEM02F 0110B AND MEM003 MEM02F 1 0 1 0 Address 03H 0 1 1 0 Address ...

Page 229: ... data Stores the result in data memory 3 Example 1 To reset bit 3 MSB for address 0 03H 0 03H 0 03H 0111B Address 0 03H 1 don t care MEM003 MEM 0 03H AND MEM003 0111B Example 2 To reset all the bits for address 0 03H MEM003 MEM 0 03H AND MEM003 0000B or MEM003 MEM 0 03H MOV MEM003 00H 5 XOR r m Exclusive OR between general register and data memory 1 OP code 10 8 7 4 3 0 00101 mR mC r ...

Page 230: ...H contents are the same as those for address 0 0FH jumps to LBL1 otherwise jumps to LBL2 This example is to compare the status of an alternate switch address 0 03H contents with the internal status address 0 0FH contents and to branch to changed switch processing 1 0 1 0 Address 03H 0 1 1 0 Address 0FH 1 1 0 0 Address 03H XOR Bits changed MEM003 MEM 0 03H MEM00F MEM 0 0FH XOR MEM003 MEM00F SKNE ME...

Page 231: ... 1 and 3 in address 0 03H and store the result in address 03H MEM003 MEM 0 03H XOR MEM003 1010B 18 5 4 Judgment Instruction 1 SKT m n Skip next instruction if data memory bits are true 1 OP code 10 8 7 4 3 0 11110 mR mC n 2 Function CMP 0 if m n n then skip Skip the next one instruction if the result of ANDing the data memory contents and immediate data n is equal to n Executes as NOP instruction ...

Page 232: ...o instructions are the same SKT 13H 1111B SKE 13H 0FH 2 SKF m n Skip next instruction if data memory bits are false 1 OP code 10 8 7 4 3 0 11111 mR mC n 2 Function CMP 0 if m n 0 then skip Skips the next one instruction if the result of ANDing the data memory contents and immediate data n is 0 Executes as NOP instruction 3 Example 1 Stores immediate data 00H to address 0FH in the data memory conte...

Page 233: ...34H 1111B SKE 34H 00H 18 5 5 Comparison Instructions 1 SKE m n4 Skip if data memory equal to immediate data 1 OP code 10 8 7 4 3 0 01001 mR mC n4 2 Function m n4 skip if zero Skip the next one instruction if the data memory contents are equal to the immediate data value Executes as NOP instruction 3 Example To transfer 0FH to address 24H if the address 24H contents are 0 if not jumps to OPE1 MEM02...

Page 234: ...n 3 Example Jumps to XYZ if the address 1FH contents are 1 and the address 1EH contents are 3 otherwise jumps to ABC To compare 8 bit data this instruction is used in the following combination 3 1 1EH 0 0 1 1 1FH 0 0 0 1 MEM01E MEM 0 1EH MEM01F MEM 0 1FH SKNE MEM01F 01H SKE MEM01E 03H BR ABC BR XYZ The above program can be rewritten as follows using compare and zero flags MEM01E MEM 0 1EH MEM01F M...

Page 235: ...dresses 1FH higher and 2FH lower is greater than immediate data 17H if not executes RETSK MEM01E MEM 0 1FH MEM02F MEM 0 2FH SKGE MEM01F 1 RETSK SKNE MEM01F 1 SKLT MEM02F 8 7 1 RET RETSK 4 SKLT m n4 Skip if data memory less than immediate data 1 OP code 10 8 7 4 3 0 11011 mR mC n4 2 Function m n4 skip if borrow Skips the next one instruction if the data memory contents are less than the immediate d...

Page 236: ... flag to the right by 1 bit 3 Example 1 When row address 0 of bank 0 0 00H 0 0FH is specified as general register RPH 0 RPL 0 rotate the value of address 0 00H 1000B to the right by 1 bit to make it 0100B 0 00H 0 00H 2 MEM000 MEM 0 00H MOV RPH 00H General register bank 0 MOV RPL 00H General register row address 0 CLR1 CY CY flag 0 RORC MEM000 Example 2 When row address 0 of bank 0 0 00H 0 0FH is s...

Page 237: ...ank 0 MOV RPL 00H General register row address 0 CLR1 CY CY flag 0 RORC MEM00C RORC MEM00D RORC MEM00E RORC MEM00F 18 5 7 Transfer Instructions 1 LD r m Load data memory to general register 1 OP code 10 8 7 4 3 0 01000 mR mC r 2 Function r m Stores the data memory contents to general register 3 Example 1 To store the address 0 2FH contents to address 0 03H 0 03H 0 2FH MEM003 MEM 0 03H MEM02F MEM 0...

Page 238: ...y selecting data memory address 2FH if IXE 1 IXH 0 IXM 4 and IXL 0 i e IX 0 40H IXH 00H IXM 04H IXL 00H IXE flag 1 0 03H 0 6FH Address obtained as result of ORing index register contents 040H and data memory contents 0 2FH MEM003 MEM 0 03H MEM02F MEM 0 2FH MOV IXH 00H IX 00001000000B 0 40H MOV IXM 04H MOV IXL 00H SET1 IXE IXE flag 1 LD MEM003 MEM02F Bank 0 Column address System register 0 1 2 3 4 ...

Page 239: ...3H ST 2FH 03H Transfer general register contents to data memory Bank 0 Column address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F General register Row address Example 2 Stores the address 0 00H contents to addresses 0 18H through 0 1FH The data memory addresses 18H 1FH are specified by the index register 0 18H 0 00H 0 19H 0 00H 0 1FH 0 00H MOV IXH 00H IX 00000000000B 0 00H MOV ...

Page 240: ...System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F General register Row address 3 MOV r m Move data memory to destination indirect 1 OP code 10 8 7 4 3 0 01010 mR mC r 2 Function When MPE 1 MP r m When MPE 0 BANK mR r m Stores the data memory contents to the data memory addressed by the general register contents When MPE 0 transfer is performed in the same row address in the same bank...

Page 241: ... address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F General register Row address F Example 2 Stores the address 0 20H contents to address 0 3FH with the MPE flag set to 1 The row address for the transfer destination data memory address is specified by the memory pointer MP contents The column address is specified by the general register contents at address 0 00H 0 3FH 0 20H ME...

Page 242: ...the general register contents to data memory When MPE 0 transfer is performed in the same row address in the same bank 3 Example 1 Stores the address 0 2FH contents to address 0 20H with the MPE falg cleared to 0 The transfer destination data memory address is at the same row address as the transfer source The column address is specified by the general register contents at address 0 00H 0 20H 0 2F...

Page 243: ... source data memory is specified by the memory pointer MP contents The column address is specified by the general register contents at address 0 00H 0 20H 0 3FH MEM000 MEM 0 00H MEM020 MEM 0 20H MOV MEM000 0FH Sets column address in general register MOV MPH 00H Sets row address in memory pointer MOV MPL 03H SET1 MPE MPE flag 1 MOV MEM020 MEM000 Store Bank 0 Column address System register 0 1 2 3 4...

Page 244: ... MEM050 MEM 0 50H MOV MEM050 0AH Example 2 Stores immediate data 07H to address 0 32H when data memory address 0 00H is specified with IXH 0 IXM 3 IXL 2 and IXE flag 1 0 32H 07H MEM000 MEM 0 00H MOV IXH 00H IX 00000110010B 0 32H MOV IXM 03H MOV IXL 02H SET1 IXE IXE flag 1 MOV MEM000 07H 6 MOVT DBF AR Move program memory data specified by AR to DBF 1 OP code 10 8 7 4 3 0 00111 000 0001 0000 2 Funct...

Page 245: ...gisters AR3 AR2 AR1 and AR0 in the system register to data buffers DBF3 DBF2 DBF1 and DBF0 Table data Address ORG 0010H 0010H DW 0000000000000000B 0000H 0011H DW 1010101111001101B 0ABCDH Table reference program MOV AR3 00H AR3 00H Sets 0011H in address register MOV AR2 00H AR2 00H MOV AR1 01H AR1 01H MOV AR0 01H AR0 01H MOVT DBF AR Transfers address 0011H data to DBF In this case the data are stor...

Page 246: ...ister AR value to address stack register specified by stack pointer 3 Example 1 Sets 003FH in address register and stores it in stack MOV AR3 00H MOV AR2 00H MOV AR1 03H MOV AR0 0FH PUSH AR Bank 0 Column address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address 0 0 3 F S T A C K 0 0 3 F ...

Page 247: ...e exists after a subroutine Address 0010H CALL SUB1 DATA TABLE 0011H DW 0012H DW 0013H DW 0014H DW 1A1FH 002FH 010AH 0555FH 002FH DW 0030H 0FFFH SUB1 POP AR MOV MOV MOV MOV PUSH RET AR3 AR2 AR1 AR0 AR 00H 00H 03H 00H If POP instruction is executed at this time the contents of address register is 0011H the next address of CALL instruction ...

Page 248: ... an interrupt processing routine is being executed the PSW contents are transferred to the address register through WR at the beginning of the interrupt processing and saved to address stack register by the PUSH instruction Before the execution returns from the interrupt routine the address register contents are restored through WR to PSW by the POP instruction EI Genetates interrupt factor PEEK P...

Page 249: ...ister file contents to window register WR 3 Example Stores the stack pointer SP contents at address 01H in the register file to the window register PEEK WR SP SP WR Bank 0 Column address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address Column address 0 1 2 3 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address Register file ...

Page 250: ... to register file 3 Example 1 Stores immediate data 0FH to P0DBIO for the register file through the window register MOV WR 0FH POKE P0DBIO WR Sets all of P0D0 P0D1 P0D2 and P0D3 in output mode WR Bank 0 Column address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address Column address 0 1 2 3 0 1 2 3 4 5 6 7 8 9 A B C D E F Row address Register file P0DBIO ...

Page 251: ... 7FH contents in system register to WR POKE MEM05F WR Stores WR contents to address 5FH in data memory 11 GET DBF p Get peripheral data to data buffer 1 OP code 10 8 7 4 3 0 00111 PH 1011 PL 2 Function DBF p Stores the peripheral register contents to data buffer DBF 3 Example 1 Stores the 8 bit contents for shift register SIOSFR in the serial interface to data buffers DBF0 and DBF1 GET DBF SIOSFR ...

Page 252: ... depending on the circuit For example if the GET instruction is executed to access a peripheral circuit which should be accessed in 8 bit units data is stored in the lower 8 bits for the data buffer DBF DBF1 DBF0 Data buffer DBF3 Retain DBF2 Retain DBF1 b7 DBF0 b0 GET Actual bits b7 b0 Data of peripheral hardware Bank 0 Column address System register 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F...

Page 253: ...OV DBF1 0AH PUT SIOSFR DBF 4 Note Up to 16 bits in the data buffer are available When a peripheral circuit is accessed by the PUT instruction the number of bits by which the circuit is to be accessed differs depending on the circuit For example if the PUT instruction is executed to access the shift register SIO which should be accessed in 8 bits units only the lower 8 bits for the data buffer DBF ...

Page 254: ... 8 Branch Instructions 1 BR addr Branch to the address 1 OP code 10 0 01100 addr 2 Function PC addr Branches to an address specified by addr 3 Example FLY LAB 0FH Defines FLY 0FH BR FLY Jumps to address 0FH BR LOOP1 Jumps to LOOP1 BR 2 Jumps to an address 2 addresses lower than current address BR 3 Jumps to an address 3 addresses higher than current address LOOP1 ...

Page 255: ...R0 AR3 and jumps to address 003FH by using the BR AR instruction MOV AR3 00H AR3 00H MOV AR2 00H AR2 00H MOV AR1 03H AR1 03H MOV AR0 0FH AR0 0FH BR AR Jumps to address 003FH Example 2 Changes the branch destination according to the data memory address 0 10H contents as follows 0 10H contents Branch destination label 00H AAA 01H BBB 02H CCC 03H DDD 04H EEE 05H FFF 06H GGG 07H HHH 08H 0FH ZZZ Jump t...

Page 256: ...ss 1 MOV AR3 00H AR3 00H Sets AR to 001 H MOV AR2 00H AR2 00H MOV AR1 01H AR1 01H ST AR0 MEM010 AR0 0 10H SKF AR0 1000B Sets 08H in AR0 if AR0 contents are greater than 08H AND AR0 1000B BR AR 4 Note The higher 6 bits of address register are fixed to 0 Only lower 10 bits can be used 18 5 9 Subroutine Instructions 1 CALL addr Call subroutine 1 OP code 10 0 11100 addr 2 Function SP SP 1 ASR PC PC ad...

Page 257: ...CALL SUB1 MAIN Example 2 SUB1 CALL SUB1 MAIN CALL SUB2 RET SUB2 CALL SUB3 RET SUB3 RET 2 CALL AR Call subroutine specified by address register 1 OP code 00111 000 0101 0000 2 Function SP SP 1 ASR PC PC AR Increments and saves to the stack the program counter PC value and branches to a subroutine that starts from the address specified by address register AR ...

Page 258: ... CALL AR instruction MOV AR3 00H AR3 00H MOV AR2 00H AR2 00H MOV AR1 02H AR1 02H MOV AR0 00H AR0 00H CALL AR Calls subroutine at address 0020H Example 2 Calls the following subroutine by the data memory address 0 10H contents 0 10H Contents Subroutine 00H SUB1 01H SUB2 02H SUB3 03H SUB4 04H SUB5 05H SUB6 06H SUB7 07H SUB8 08H 0FH SUB9 ...

Page 259: ...18H BR SUB9 MOV MOV MOV MOV MOV ST SKF AND CALL RPH RPL AR3 AR2 AR1 AR0 AR0 AR0 AR 00H 02H 00H 00H 01H 10H 1000B 1000B General register bank 0 General register row address 1 AR3 00H address register 001 H AR2 00H AR1 01H AR0 0 10H If the content of AR0 is larger than 08H set AR0 content to 08H To jump table Returns here when executing RET instruction in each subroutine 4 Note The higher 6 bits of ...

Page 260: ...nstruction to the program counter 3 Example 4 RETSK Return to the main program then skip next instruction 1 OP code 00111 001 1110 0000 2 Function PC ASR SP SP 1 and skip Instruction to return to the main program from a subroutine Skips the instruction next to the CALL instruction Executes as NOP instruction Therefore restores the return address saved to the stack by the CALL instruction to progra...

Page 261: ... Instruction to return to the main program from an interrupt service program Restores the return address saved to the stack by a vector interrupt to the program counter Part of the system register is also returned to the status before the occurrence of the vector interrupt 3 Note 1 The system register contents that are automatically saved i e that can be restored by the RETI instruction when an in...

Page 262: ...est is accepted after the instruction next to that that has accepted the interrupt has been completely executed excluding an instruction that manipulates program counter The flow then shifts to the vector addressNote1 Notes 1 The vector address differs depending on the interrupt to be accepted Refer to Table 14 1 Interrupt Source Types Generating interrupt request MOV ADD ADD 0AH 0BH 0CH 00H 01H 0...

Page 263: ...ction has been executed therefore the interrupt is not accepted However interrupt request flag IRQ is set and the interrupt is accepted as soon as the interrupt enable flag is set Example 2 An example of an interrupt which occurs in response to an interrupt request being accepted when program counter PC is being executed Generating interrupt request BR ABC EI MOV ADD 0AH 0BH 00H 01H EI RET Interru...

Page 264: ... be released is specified by operand s For the stop releasing condition s refer to 15 3 2 HALT h Halt CPU and release by condition h 1 OP code 3 0 00111 011 1111 h 2 Function Places the device in the halt mode In the halt mode the power dissipation for the device is reduced The condition under which the halt mode is to be released is specified by operand h For halt releasing condition h refer to 1...

Page 265: ... MEMO 250 ...

Page 266: ...AS171 µPD171 device file must be in the current directory at assembly time Specify mask options for the following pins RESET pin Port 0D P0D3 P0D2 P0D1 P0D0 Port 0E P0E1 P0E0 19 1 1 OPTION and ENDOP Pseudo Instructions The block from the OPTION pseudo instruction to the ENDOP pseudo instruction is defined as the option definition block The format for the mask option definition block is shown below...

Page 267: ...l up resistor The OPTRES format is shown below Specify the RESET mask option in the operand field Symbol Mnemonic Operand Comment label OPTRES RESET comment The OPTP0D format is shown below Specify mask options for all pins of port 0D Specify the pins in the operand field starting at the first operand in the order P0D3 P0D2 P0D1 then P0D0 Symbol Mnemonic Operand Comment label OPTP0D P0D3 P0D2 P0D1...

Page 268: ...f describing mask options RESET pin Pull up P0D3 Open P0D2 Open P0D1 Pull up P0D0 Pull up P0E1 Pull up P0E0 Open Symbol Mnemonic Operand Comment µPD17133 Setting mask options OPTION OPTRES PULLUP OPTP0D OPEN OPEN PULLUP PULLUP OPTP0E PULLUP OPEN ENDOP ...

Page 269: ... MEM 0 7AH R W Index register high MPH MEM 0 7AH R W Data memory row address pointer high MPE FLG 0 7AH 3 R W Memory pointer enable flag IXM MEM 0 7BH R W Index register middle MPL MEM 0 7BH R W Data memory row address pointer low IXL MEM 0 7CH R W Index register low RPH MEM 0 7DH R W General register pointer high RPL MEM 0 7EH R W General register pointer low PSW MEM 0 7FH R W Program status word...

Page 270: ...W Port 0D bit 3 P0D2 FLG 0 73H 2 R W Port 0D bit 2 P0D1 FLG 0 73H 1 R W Port 0D bit 1 P0D0 FLG 0 73H 0 R W Port 0D bit 0 Register file control register 1 2 Symbol Name Attribute Value Read Write Description SP MEM 0 81H R W Stack pointer SIOEN FLG 0 8AH 0 R W SIO enable flag INT FLG 0 8FH 0 R INT pin status flag PDRESEN FLG 0 90H 0 R W Power down reset enable flag TMEN FLG 0 91H 3 R W Timer enable...

Page 271: ...output port P0CBIO3 FLG 0 B4H 3 R W P0C3 input output selection flag 1 output port P0CBIO2 FLG 0 B4H 2 R W P0C2 input output selection flag 1 output port P0CBIO1 FLG 0 B4H 1 R W P0C1 input output selection flag 1 output port P0CBIO0 FLG 0 B4H 0 R W P0C0 input output selection flag 1 output port P0ABIO3 FLG 0 B5H 3 R W P0A3 input output selection flag 1 output port P0ABIO2 FLG 0 B5H 2 R W P0A2 inpu...

Page 272: ...CHAPTER 19 ASSEMBLER RESERVED WORDS 257 Others Symbol Name Attribute Value Description DBF DAT 0FH Fix operand value of PUT GET MOVT instructions IX DAT 01H Fix operand value of INC instruction ...

Page 273: ...0 R W 0 0 0 0 P 0 B G I O 0 0 0 R W 0 0 0 P 0 E B I O 0 0 0 R W 0 0 P 0 D B I O 0 0 P 0 E B I O 1 P 0 D B I O 2 P 0 D B I O 3 P 0 D B I O 1 0 R W 0 0 P 0 C B I O 0 0 P 0 C B I O 2 P 0 C B I O 3 P 0 C B I O 1 0 R W 0 0 P 0 A B I O 0 0 P 0 A B I O 2 P 0 A B I O 3 P 0 A B I O 1 Figure 19 1 Configuration of Control Register µPD17120 17121 1 2 Remark means the address when using assembler AS17K All fla...

Page 274: ...I E G M D 0 0 0 0 R W 0 S I O E N 0 0 0 0 R W 0 0 0 0 I R Q 0 I E G M D 1 0 0 0 0 R 0 I N T 0 Note 0 0 0 0 R W 0 0 I P 0 I P T M I P S I O R W 0 0 0 0 I R Q T M 1 0 0 R W 0 0 0 0 I R Q S I O 0 0 0 Figure 19 1 Configuration of Control Register µPD17120 17121 2 2 Note The INT flag differs depending on the INT pin state at the time ...

Page 275: ...r BANK MEM 0 79H R W Bank register IXH MEM 0 7AH R W Index register high MPH MEM 0 7AH R W Data memory row address pointer high MPE FLG 0 7AH 3 R W Memory pointer enable flag IXM MEM 0 7BH R W Index register middle MPL MEM 0 7BH R W Data memory row address pointer low IXL MEM 0 7CH R W Index register low RPH MEM 0 7DH R W General register pointer high RPL MEM 0 7EH R W General register pointer low...

Page 276: ...Port 0E bit 0 P0A3 FLG 0 70H 3 R W Port 0A bit 3 P0A2 FLG 0 70H 2 R W Port 0A bit 2 P0A1 FLG 0 70H 1 R W Port 0A bit 1 P0A0 FLG 0 70H 0 R W Port 0A bit 0 P0B3 FLG 0 71H 3 R W Port 0B bit 3 P0B2 FLG 0 71H 2 R W Port 0B bit 2 P0B1 FLG 0 71H 1 R W Port 0B bit 1 P0B0 FLG 0 71H 0 R W Port 0B bit 0 P0C3 FLG 0 72H 3 R W Port 0C bit 3 P0C2 FLG 0 72H 2 R W Port 0C bit 2 P0C1 FLG 0 72H 1 R W Port 0C bit 1 P...

Page 277: ...ltage selection flag bit 1 CMPVREF0 FLG 0 9DH 0 R W Comparator reference voltage selection flag bit 0 CMPSTRT FLG 0 9EH 1 R Comparator start flag CMPRSLT FLG 0 9EH 0 R W Comparator comparison result flag IEGMD1 FLG 0 9FH 1 R W INT pin edge detection selection flag bit 1 IEGMD0 FLG 0 9FH 0 R W INT pin edge detection selection flag bit 0 P0C3IDI FLG 0 A3H 3 R W P0C3 input port disable flag P0C3 Cin3...

Page 278: ...t output selection flag 1 output port P0ABIO0 FLG 0 B5H 0 R W P0A0 input output selection flag 1 output port IRQSIO FLG 0 BDH 0 R W SIO interrupt request flag IRQTM FLG 0 BEH 0 R W Timer interrupt request flag IRQ FLG 0 BFH 0 R W INT pin interrupt request flag Peripheral hardware register Symbol Name Attribute Value Read Write Description SIOSFR DAT 01H R W Peripheral address of the shift register...

Page 279: ...0 0 T M O S E L 0 0 0 R W 1 S P 0 1 0 0 R W 0 0 0 0 P 0 B G I O 0 0 0 R W 0 0 0 P 0 E B I O 0 0 0 R W 0 0 P 0 D B I O 0 0 P 0 E B I O 1 P 0 D B I O 2 P 0 D B I O 3 P 0 D B I O 1 0 R W 0 0 P 0 C B I O 0 0 P 0 C B I O 2 P 0 C B I O 3 P 0 C B I O 1 0 R W 0 0 P 0 A B I O 0 0 P 0 A B I O 2 P 0 A B I O 3 P 0 A B I O 1 0 R W 0 0 P 0 C 0 I D I 0 P 0 C 2 I D I P 0 C 3 I D I P 0 C 1 I D I Remark means the a...

Page 280: ... N T 0 0 0 0 0 R W 0 0 I P 0 I P T M I P S I O R W 0 0 0 0 I R Q T M 1 0 0 R W 0 0 0 0 I R Q S I O 0 0 0 0 0 0 0 0 0 C M P R S L T C M P S T R T 1 R R W R W 0 C M P V R E F 0 0 C M P V R E F 1 0 C M P V R E F 2 1 C M P V R E F 3 0 0 0 0 0 C M P C H 1 C M P C H 1 0 R W Figure 19 2 Configuration of Control Register µPD17132 17133 17P132 17P133 2 2 Note The INT flag differs depending on the INT pin s...

Page 281: ...266 MEMO ...

Page 282: ...nts of the data memory in a real time environment SE Board The SE 17120 is an SE board for the µPD17120 subseries The board is SE 17120 used for evaluation of single system units as well as for debugging by being combined with an in circuit emulator Emulation Probe The EP 17120CS which is the emulation probe for the µPD17120 sub EP 17120CS series connects between an SE board and a target system PR...

Page 283: ...r PC 9800 series MS DOSTM IBM PC AT PC DOSTM PC 9800 series MS DOS IBM PC AT PC DOS PC 9800 series MS DOS IBM PC AT PC DOS 5 inch 2HD µS5A10AS17K 3 5 inch 2HD µS5A13AS17K 5 inch 2HC µS7B10AS17K 3 5 inch 2HC µS7B13AS17K 5 inch 2HD µS5A10AS17120Note 3 5 inch 2HD µS5A13AS17120Note 5 inch 2HC µS7B10AS17120Note 3 5 inch 2HC µS7B13AS17120Note 5 inch 2HD µS5A10IE17K 3 5 inch 2HD µS5A13IE17K 5 inch 2HC µS...

Page 284: ...ng medium Use UV EPROM to place an order for the mask ROM Add PROM as an assemble option of the Assembler AS17K and create a mask ROM ordering HEX file with extender for PRO Next write the mask ROM ordering HEX file into the UV EPROM Create three UV EPROMs with the same contents 3 Prepare necessary documents Fill out the following forms to place an order for the mask ROM Mask ROM ordering sheet Ma...

Page 285: ... MEMO 270 ...

Page 286: ...ystem clock oscillation circuit make sure that its ground wire s resistance component and impedance component are minimized Also to avoid the effect of wiring capacity etc please wire the part encircled in the dotted line in Figure C 1 in the manner described below Make the wiring as short as possible Do not allow it to intersect other signal conductors Do not let it be near lines in which a large...

Page 287: ...b Signal conductors are intersecting c Functuating large current located d Current flowing in the GND line of the too close to the signal conductor oscillation circuit Points A and B s potentials change as to point C e Signals are being extracted XIN GND XOUT PORT XIN GND XOUT PORT A B C Large volume current XIN GND XOUT Large current XIN GND XOUT XIN GND XOUT Too long ...

Page 288: ... C POP AR 233 CALL addr 217 PUSH AR 230 CALL AR 242 PUT p DBF 238 D R DI 248 RET 245 RETI 246 E RETSK 245 EI 247 RORC r 221 G S GET DBF p 236 SKE m n4 218 SKF m n 217 H SKGE m n4 220 HALT h 249 SKLT m n4 220 SKNE m n4 219 I SKT m n 216 INC AR 199 ST m r 224 INC IX 201 STOP s 249 SUB m n4 205 L SUB r m 202 LD r m 222 SUBC m n4 209 SUBC r m 207 M MOV m n4 229 X MOV m r 227 XOR m n4 216 MOV r m 225 X...

Page 289: ... MEMO 274 ...

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