15.0 Switching Characteristics
AC Specs DP83902A
Note:
All Timing is Preliminary (Continued)
Register Write (Non-Latched, ADS0
e
1)
TL/F/11157 – 36
Symbol
Parameter
Min
Max
Units
rsws
Register Select to Write Setup (Note 1)
15
ns
rswh
Register Select Hold from Write
0
ns
rwds
Register Write Data Setup
20
ns
rwdh
Register Write Data Hold
21
ns
wackl
Write Low to ACK Low (Note 2)
n
*
bcyc
a
30
ns
wackh
Write High to ACK High
30
ns
ww
Write Width from ACK
50
ns
Note 1:
Assumes ADS0 is high when RA0–3 changing.
Note 2:
ACK is not generated until CS and SWR are low and the ST-NIC has synchronized to the register access. In Dual Bus systems additional cycles will be
used for a local DMA or remote DMA to complete.
55
Obsolete