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15.0 Switching Characteristics
AC Specs DP83902A
Note:
All Timing is Preliminary (Continued)
Register Read (Non-Latched, ADS0
e
1)
TL/F/11157 – 34
Symbol
Parameter
Min
Max
Units
rsrs
Register Select to Read Setup
10
ns
(Notes 1, 3)
rsrh
Register Select Hold from Read
0
ns
ackdv
ACK Low to Valid Data
55
ns
rdz
Read Strobe to Data TRI-STATE (Note 2)
15
70
ns
rackl
Read Strobe to ACK Low (Note 3)
n
*
bcyc
a
30
ns
rackh
Read Strobe to ACK High
30
ns
Note 1:
rsrs includes flow-through time of latch.
Note 2:
These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.
Note 3:
CS may be asserted before of after RA0–3, and SRD, since address decode begins when ACK is asserted. If CS is asserted after RA0–3, and SRD, rackl
is referenced from falling edge of CS.
53
Obsolete