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15.0 Switching Characteristics
AC Specs DP83902A
Note:
All Timing is Preliminary (Continued)
Wait State Insertion
TL/F/11157 – 41
Symbol
Parameter
Min
Max
Units
ews
External Wait Setup to T3 0Clock (Note 1)
10
ns
ewr
External Wait Release Time (Note 1)
15
ns
Note 1:
The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network
rates. The allowable wait states are found in the table below. (Assumes 10 Mbit/sec data rate.)
BSCK (MHz)
Max
Ý
of Wait States
Byte Transfer
Word Transfer
8
0
1
10
0
1
12
1
2
14
1
2
16
1
3
18
2
3
20
2
4
Table assumes 10 MHz network clock.
The number of allowable wait states in byte mode can be
calculated using:
Ý
W
(byte mode)
e
#
8 tnw
4.5 tbsck
b
1
J
Ý
W
e
Number of Wait States
tnw
e
Network Clock Period
tbsck
e
BSCK Period
The number of allowable wait states in word mode can be
calculated using:
Ý
W
(word mode)
e
#
5 tnw
2 tbsck
b
1
J
60
Obsolete