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TL/F/11157
DP83902A
ST-NIC
Serial
Network
Interface
Controller
for
Twisted
Pair
PRELIMINARY
November 1995
DP83902A ST-NIC
TM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA/CD local area net-
works. These include Ethernet (10BASE5), Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T). The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface,
and 10BASE-T transceiver functions in accordance with the
IEEE 802.3 standards.
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard. This functional block incorporates the
receiver, transmitter, collision, heartbeat, loopback, jabber,
and link integrity blocks as defined in the standard. The
transceiver when combined with equalization resistors,
transmit/receive filters, and pulse transformers provides a
complete physical interface from the DP83902A’s ENDEC
module and the twisted pair medium.
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit/sec. Also included are colli-
sion detect translator and diagnostic loopback capability.
The ENDEC module interfaces directly to the transceiver
module, and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers.
(Continued)
Features
Y
Single chip solution for IEEE 802.3, 10BASE-T
Y
Integrated controller, ENDEC, and transceiver
Y
Full AUI interface
Y
No external precision components required
Y
3 levels of loopback supported
Transceiver Module
Y
Integrates transceiver electronics, including:
Ð Transmitter and receiver
Ð Collision detect, heartbeat and jabber timer
Ð Link integrity test
Y
Link disable and polarity detection/correction
Y
Integrated smart receive squelch
Y
Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y
10 Mb/s Manchester encoding/decoding, plus clock re-
covery
Y
Transmitter half or full step mode
Y
Squelch on receive and collision pairs
Y
Lock time 5 bits typical
Y
Decodes Manchester data with up to
g
18 ns jitter
MAC/Controller Module
Y
100% DP8390 software/hardware compatible
Y
Dual 16-bit DMA channels
Y
16-byte internal FIFO
Y
Efficient buffer management implementation
Y
Independent system and network clocks
Y
Supports physical, multicast and broadcast address fil-
tering
Y
Network statistics storage
1.0 System Diagram
Station or DTE
TL/F/11157 – 1
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
ST-NIC
TM
is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
Obsolete