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10.0 Internal Registers
(Continued)
10.3 REGISTER DESCRIPTIONS
(Continued)
INTERRUPT MASK REGISTER (IMR)
0FH (WRITE)
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit
in the IMR is set low, an interrupt will not occur when the bit in the ISR is set.
The IMR powers up to all zeroes.
7
6
5
4
3
2
1
0
Ð
RDCE CNTE OVWE TXEE
RXEE
PTXE
PRXE
Bit
Symbol
Description
D0
PRXE
Packet Received Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when packet received
D1
PTXE
Packet Transmitted Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when packet is transmitted
D2
RXEE
Receive Error Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when packet received with error
D3
TXEE
Transmit Error Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when packet transmission results in error
D4
OVWE
Overwrite Warning Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to store incoming packet
D5
CNTE
Counter Overflow Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when MSB of one or more of the Network Statistics counters has been set
D6
RDCE
DMA Complete Interrupt Enable
0: Interrupt Disabled
1: Enables Interrupt when Remote DMA transfer has been completed
D7
Reserved
Reserved
28
Obsolete