15.0 Switching Characteristics
AC Specs DP83902A
Note:
All Timing is Preliminary (Continued)
Register Write (Latched Using ADS0)
TL/F/11157 – 35
Symbol
Parameter
Min
Max
Units
rss
Register Select Setup to ADS0 Low
10
ns
rsh
Register Select Hold from ADS0 Low
17
ns
aswi
Address Strobe Width In
15
ns
rwds
Register Write Data Setup
20
ns
rwdh
Register Write Data Hold
21
ns
ww
Write Strobe Width from ACK
50
ns
wackh
Write Strobe High to ACK High
30
ns
wackl
Write Low to ACK Low (Notes 1, 2)
n
*
bcyc
a
30
ns
rswsl
Register Select to Write Strobe Low
10
ns
Note 1:
ACK is not generated until CS and SWR are low and the ST-NIC has synchronized to the register access. In Dual Bus Systems additional cycles will be
used for a local DMA or Remote DMA to complete.
Note 2:
CS may be asserted before or after SWR. If CS is asserted after SWR, wackl is referenced from falling edge of CS.
54
Obsolete