![background image](http://html.mh-extra.com/html/national-semiconductor/st-nic-dp83902a/st-nic-dp83902a_manual_710381046.webp)
13.0 Bus Arbitration and Timing
(Continued)
The FIFO at the Beginning of Transmit
Before transmitting, the ST-NIC performs a prefetch from
memory to load the FIFO. The number of bytes prefetched
is the programmed FIFO threshold. The next BREQ is not
issued until after the ST-NIC actually begins transmitting
data, i.e., after SFD. The Transmit Prefetch diagram illus-
trates this process.
Transmit Prefetch Timing
TL/F/11157 – 59
Maximum Bus Latency for Byte Mode
TL/F/11157 – 60
Maximum Bus Latency for Word Mode
TL/F/11157 – 61
45
Obsolete