National Semiconductor PC16552C, Manual

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TL/F/11195 – 5 TL/F/11195 – 6
FIGURE 4. Fairness State Machines
All four machines use their particular DMA request signal
(RX1, RX2, TX1 or TX2) to move from the IDLE state to XFR
to FAIR. But it is all the other request signals that either
keep the machine in the FAIR state (if there is at least one
active) or allow it to move back to IDLE via TEMP (no other
requests active). Thus if a particular channel finishes being
serviced and there are others waiting for service at the time,
the channel will be degated by its FR signal, preventing it
from requesting service again before all other devicesÐ
both UART and other bus devicesÐare finished.
Terminal Count Interrupt
A signal to the CPU that a file or block of data has complet-
ed transmission or reception is a crucial feature of a practi-
cal DMA-serviced serial port. It is necessary because the
entire transfer process is completely transparent to the
CPU. The CPU must be notified one or all files being trans-
ferred are done so that it can start a new transfer, process
received data, notify the user, etc. The DMA controller pro-
vides a Terminal Count (TC) pulse when it has transferred
the number of bytes programmed into its Terminal Count
Register (see Software). The PC16552C Adapter uses this
pulse to generate an IRQ3 interrupt and disable the DMA
request line of the UART channel that completed its trans-
fer. The TC signal is common to all devices on the Micro
Channel so it was necessary to decode the signal and cre-
ate a TC unique to the UART channel that generated it.
Since the DMA controller generates the TC pulse during the
final read or write to the I/O address it is servicing, this was
accomplished by decoding TC along with the adapter’s IOR,
IOW, CS1 and CS2 signals. For example, TC, IOR and CS1
active generates TC pulse unique to the UART’s channel 1
receiver (RXRDY1).
The channel-unique TC pulses are connected to the CL in-
puts of the DMAÐEN register’s 74LS74 latches. The TC
pulse clears the adapter card enable bit for the decoded
channel and prevents any further DMA request from that
channel until the CPU has re-intialized the system for a new
file transfer.
All four UART TC pulses are OR’ed together to set a 1-bit
read-only register called Interrupt Status Register (ISR). The
output of ISR is connected to the INTR GAL and generates
an IRQ3 interrupt (see Adapter Interrupts). ISR was imple-
mented because the Micro Channel requires that adapters
generating interrupts have a status register that the CPU
can poll to determine which adapter caused the interrupt.
The ISR is implemented with two 74LS74 latches connect-
ed in a master-slave arrangement. This provides a self-
clearing mechanism when the register is read. The register
is located at I/O address 2f7H along with DMAÐEN. Its
read strobe is generated by a logical AND of the 2f7H de-
coder output and the IOR signal. The read strobe is con-
nected to the clock input of the slave latch and the inverted
strobe is connected to the master’s clock. The strobe is
also connected to the gate input of a 74LS125 buffer which
gates the output of the slave latch onto the Adapter Data
Bus bit 0. The falling edge of the read strobe gates the
register onto the data bus and clears the master latch. The
rising edge clears the slave latch.
SOFTWARE
Programming the Micro Channel DMA Controller
The Micro Channel DMA controller is register and software
compatible with the IBM Personal Computer AT DMA chan-
nels, but also has an extended mode of operation. Control-
ler registers can be read and written in the extended mode
using two registers, the Function register and the Execute
Function register. To perform an extended mode register
read/write, the CPU must write to the Function register a 4-
bit command code in the upper nibble and the channel num-
ber in the lower nibble. The command is executed by read-
ing or writing the Execute Function register. The driver pro-
grams included in this package illustrate this register access
process.
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