National Semiconductor PC16552C Page 8 Manual Download

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2. Device A detects a mismatch on ARB3 so it ceases driv-

ing all lower order bits. Device B sees a mismatch on
ARB2 so it stops driving its lower order bits. The bus now
shows 0111.

3. Device B now sees a match on ARB2 so it continues to

drive its lower order bits (only ARB0 in this case).

4. The bus now stabilizes at a value of 0110 and device B

has won control of the channel.

PC16552C ADAPTER DMA INTERFACE DESIGN

Design Considerations

The PC16552C Adapter contains not one but four indepen-
dent devices which may request DMA service. These ‘‘de-
vices’’ are the four on-board FIFOs (two Transmit and two
Receive). Each FIFO has an independent request signal
which indicates when it is empty (transmitters) or when it is
full

(receivers).

These

signals

are

named

TXRDY1,

TXRDY2, RXRDY1 and RXRDY2. This creates some free-
dom in the design of the interface between the UART re-
quests and the Micro Channel. However, there is a severe
timing limitation concerning the termination of a burst cycle
that adds constraints to the design.

The design freedom lies in where the competition between
the four UART request takes place. One possibility is to
have them compete against each at the system level during
the central arbitration cycle. This requires the adapter to
implement four Local Arbiters, one for each UART request.
At the other end of the spectrum, the adapter may imple-
ment prioritization logic that allows only one of the requests
to compete for the channel at a time. Thus only one Local
Arbiter is needed. The designer may also choose a compro-
mise such as prioritizing the receiver and transmitter re-
quests separately and using two Local Arbiters. Using four
separate Local Arbiters simplifies the overall design by elim-

inating the UART request prioritization. However, it creates
duplication of functionality (the same logic implemented four
times) and will generate a higher component cost. The
PC16552C Adapter is designed with the latter implementa-
tion.

One particular timing specification required by the Micro
Channel when a DMA slave terminates a burst cycle is the
most critical issue in the design of a useful DMA-serviced
serial port. The goal of the DMA interface design is to be
able to transfer four files simultaneously in two directions
with attention from the CPU only at the beginning and end
of the file transfers. This can only be accomplished by con-
tinually performing FIFO-sized burst transfers (16 bytes) in
response to UART FIFO requests until the DMA controller
reaches its programmed Terminal Count (end of the file).
This type of operation is called slave-terminated burst mode
and requires the UART to terminate a burst as soon as its
FIFO has been filled or emptied by the controller.

DMA controller-terminated transfers can also be used but
requires the DMA controller to be programmed with the
number of bytes to be transferred to or from a FIFO instead
of with the total number of bytes in a file. The controller
must be reprogrammed after every transfer which requires
much more attention from the CPU than with slave-terminat-
ed transfers.

When the DMA controller writes the byte that fills a Transmit
FIFO or reads the last byte in a Receiver FIFO, the
PC16552C deasserts the appropriate DMA request. The re-
quest signal passes through the logic on the adapter and
deasserts the BURST signal. The Micro Channel specifies a
minimum time that BURST be inactive high before the end
of a bus cycle in order to stop a burst without an additional
byte transfer. This is the critical timing issue. The timing
diagram in

Figure 1 illustrates the signals and delays in-

volved.

TL/F/11195 – 2

Timing Parameters:

tR/W:

Time to decode S0, S1 and M/IO signals into IOR and IOW strobes.

tRXI/tWXI:

RXRDYTXRDY inactive from leading edge of read and write strobes respectively (PC16552C DMA request signal spec).

tLOG:

Propagation delay of request signal through logic controlling BURST.

tRC:

RC restoration of BURST on the Micro Channel.