National Semiconductor PC16552C, Manual

Page: 9 / 24

Without extending the bus cycle, the maximum delay time
from the leading edge of CMD to BURST inactive is
55 ns. The two delays which must be minimized in the DMA
interface design are tR/W and tLOG. tRXI/tWXI are con-
trolled by the PC16552C and tRC is created by the Micro
Channel. It is a quantity that is unknown to this designer as it
is not specified in the IBM Technical Reference Manual.
The PC16552C TXRDY signals were designed to be re-
leased by the rising edge of the last IOW strobe. This makes
it impossible to meet the BURST inactive setup time and
therefore perform slave-terminated bursts. The PC16552C
has since been redesigned so that TXRDY is released by
the RXRDY signals. The RXTXI.C driver program included in
this package uses DMA controller terminated burst transfers
for the transmitter FIFOs, a method which must be used
with the older revision of the PC16552C. The new revision
of the PC16552C was not available when this documenta-
tion was completed. However, slave-terminated transfers
were run with the old revision and the adapter performed
correctly
except that due to the lateness of the
BURST deassertion, a 17th byte was always transferred to
the transmit FIFO. The last byte was lost since the FIFO
was already full. Therefore, the RXTXI.C driver program
should be used with all current PC16552C parts.
A second issue with the PC16552C is the length of both
tRXI and tWXI which are specified as 78 ns and 60 ns
(max). These times plus the delays in the logic implemented
on this adapter forces the use of an extended cycle (wait
state). Using the Synchronous Extended cycle as explained
in the Micro Channel Control Signals section, adds 100 ns
to the length of the CMD strobe, providing enough time to
meet the BURST inactive specification.
Adding a wait state is obviously undesirable since it increas-
es the bus cycle length by 50% (200 ns to 300 ns). One way
for a designer to avoid needing a wait state is to minimize
tLOG and tR/W. Besides using fast logic, the delay through
the DMA logic interface can be reduced by implementing
the design with four Local Arbiters. This eliminates the delay
created by the prioritization of the UART requests. Also, an
effort is being made to reduce the tRXI and tWXI specs on
the PC16552C. Finally, the IBM documentation is not clear
as to whether the t56 spec must be met for both IO read/
memory write and memory read/IO write transfers. The
spec is marked on the timing diagrams for both types of
transfers, but a separate note says that the spec must be
guaranteed for IO write cycles with no mention of the IO
read cycles. It is likely that the spec need not be met for IO
read cycles because the read to the IO device occurs long
before the end of the byte transfer since the byte must still
be written to memory.
While it did not meet worst-case specifications, the
PC16552C Adapter (with the old PC16552C rev) was also
tested without a wait state and ran I/O read DMA transfers
without errors. A test of the IO write transfers was futile
because only the older PC16552C was available making
slave-terminated transfers impossible.
The design chosen for implementation uses just one Local
Arbiter and prioritizes the UART DMA requests on the
adapter. This design was chosen because it is more inform-
ative example and has a lower chip count. This section de-
scribes the following functions of the interface logic: en-
able/disable of UART DMA requests; prioritization of the
four DMA requests; selection of the proper arbitration vec-
tor; local bus arbitration; fairness and Terminal Count inter-
rupt generation. Refer to the block diagram and schematics
for the PC16552C Adapter during the following discussions.
DMA Request Enable
A 4-bit write-only DMA request enable/disable register
(DMAÐEN) is implemented on the PC16552C Adapter us-
ing four 74LS74 latches. The complemented outputs of the
latches are used to gate the PC16552C’s DMA request sig-
nals RXRDY and TXRDY. To enable DMA request signals,
the system CPU must write a 1 to the bit locations corre-
sponding to those requests. Table I summarizes the regis-
ter’s function.
TABLE I
DMAÐEN Bits
7 6 5 4 3 2 1 0
X X X X 0 0 0 0 All DMA Request Disabled
X X X X 0 0 0 1 TXRDY2 Enabled
X X X X 0 0 1 0 TXRDY1 Enabled
X X X X 0 1 0 0 RXRDY2 Enabled
X X X X 1 0 0 0 RXRDY1 Enabled
DMAÐEN is necessary to prevent errant DMA requests to
the Micro Channel (such as the immediate transmitter re-
quests after reset) and to maintain compatibility with stan-
dard CPU-serviced serial port operation. A hardware disable
is also implemented and is described in the TC Interrupt
section.
DMAÐEN is located at I/O address 2F7h. This location is
not used by IBM and was chosen because of its similarity to
the COM2 address block made the decode simpler. The
active low output of the register’s address decoder is gated
with the IOW signal to produce a write strobe to the CLK
inputs of the 74LS74 latches.
DMA Request Prioritization
If the adapter card is used at its full capability i.e. four simul-
taneous DMA-serviced file transfers, the four UART DMA
request strobes will operate as fully independent, asynchro-
nous signals. The asynchronous state machine, Lockout,
implemented in a 16L8D GAL, is used to select the highest
priority active DMA request and lock out all other requests
until that request has been serviced. The state diagram for
Lockout is illustrated in
Figure 2 . The state machine resides
in the Idle state until one or more DMA requests go active.
The requests are the active high gated versions of the
RXRDY and TXRDY signals and are called RX1, TX1, RX2,
and TX2. An active request moves Lockout to the corre-
sponding request state. If more than one request are active
at once, the machine will move to the highest priority state.
The requests are prioritized as follows: RX1 (highest), RX2,
TX1 and TX2. Note that this prioritization mechanism pro-
vides adapter-level arbitration between the requests leaving
only one which competes for the bus at the system level
(Central Arbitration).
9