TL/F/11195 – 4
FIGURE 3. Busarb State Machine
An asynchronous state machine, Busarb, implemented in a
20V8D GAL, controls the bus arbitration. It connects directly
to the ARB/GNT, PREEMPT, BURST and CHRESET Micro
Channel signals. The following describes Busarb’s states
and operation.
Figure 3 illustrates the state diagram.
IDLE:
No DMA requests from UART (DREQ
e
1).
REQ:
UART is requesting DMA service. PREEMPT is as-
serted to request control of the bus.
ARB:
Central Arbiter has begun arbitration cycle. ENARB
is asserted causing Arbcon to start competing for
the bus. PREEMPT still active.
LOSE: Central Arbiter ends arbitration cycle. Arbcon did not
win vector arbitration so BUSWIN was not asserted.
ENARB is deasserted causing Arbcon to degate its
vector. PREEMPT remains active. When the winning
device is finished, the Central Arbiter will start a new
arbitration cycle and Busarb will move back into the
ARB state.
XFR1: The PC16552C Adapter has won arbitration. This is
an intermediate state to XFR2 needed to prevent
more than one bit from changing between states.
The state transitions from intermediate states
(XFR1 and XFR2) are unconditional and marked
‘‘uct’’ on the state diagram. PREEMPT deasserted.
XFR2: BURST is asserted and DMA controller begins
transfer.
XFR3: DREQ has gone inactive signifying completion of
transfer. BURST is deasserted. This is an intermedi-
ate state to IDLE.
Fairness
IBM’s Fairness algorithm is enabled when POS register 102
bit 7 is set. An asynchronous state machine for each of the
four UART DMA request signals, implemented in 2 PALs,
Fair1 and Fair2, ensures that the four requests obey the
Fairness algorithm by disabling them when Fairness re-
quires them to wait.
All four machines have the same 7 inputs: CHRESET, FAIR,
PREEMPT and the four gated UART requests: RX1, RX2,
TX1 and TX2. The machines have one unique output, FR,
that is a second UART request gating signal along with the
DMAÐEN output. The Fairness state machines have the
following states:
[
1,1
]
IDLE:
Reset state. Particular DMA request (RX1,
TX1, RX2, TX2) not active. Output: none.
[
1,0
]
XFR:
DMA request active. Output: none.
[
0,0
]
FAIR:
DMA request goes inactive, FAIR
e
1 (en-
abled) and at least one other UART request or
PREEMPT is active. Output: FR degating sig-
nal is active.
[
0,1
]
TEMP: All requests for bus have gone inactive. This is
an intermediate state to IDLE. Output: FR still
asserted (deasserted upon transition to IDLE).
Figure 4 shows the state diagrams for the RX1 and TX1
state machines. The machines for RX2 and TX2 are identi-
cal. On the adapter card, RX1 and RX2 machines are imple-
mented in the 16L8A PAL Fair1 and TX1 and TX2 in Fair2.
11
Summary of Contents for PC16552C
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